1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20120316"
34
35 #define DRIVER_MAJOR 1
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 0
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 spinlock_t lock;
50 struct list_head channels;
51 struct nouveau_vm *vm;
52 };
53
54 static inline struct nouveau_fpriv *
nouveau_fpriv(struct drm_file * file_priv)55 nouveau_fpriv(struct drm_file *file_priv)
56 {
57 return file_priv ? file_priv->driver_priv : NULL;
58 }
59
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
61
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
66
67 struct nouveau_grctx;
68 struct nouveau_mem;
69 #include "nouveau_vm.h"
70
71 #define MAX_NUM_DCB_ENTRIES 16
72
73 #define NOUVEAU_MAX_CHANNEL_NR 128
74 #define NOUVEAU_MAX_TILE_NR 15
75
76 struct nouveau_mem {
77 struct drm_device *dev;
78
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
81 u8 page_shift;
82
83 struct drm_mm_node *tag;
84 struct list_head regions;
85 dma_addr_t *pages;
86 u32 memtype;
87 u64 offset;
88 u64 size;
89 };
90
91 struct nouveau_tile_reg {
92 bool used;
93 uint32_t addr;
94 uint32_t limit;
95 uint32_t pitch;
96 uint32_t zcomp;
97 struct drm_mm_node *tag_mem;
98 struct nouveau_fence *fence;
99 };
100
101 struct nouveau_bo {
102 struct ttm_buffer_object bo;
103 struct ttm_placement placement;
104 u32 valid_domains;
105 u32 placements[3];
106 u32 busy_placements[3];
107 struct ttm_bo_kmap_obj kmap;
108 struct list_head head;
109
110 /* protected by ttm_bo_reserve() */
111 struct drm_file *reserved_by;
112 struct list_head entry;
113 int pbbo_index;
114 bool validate_mapped;
115
116 struct list_head vma_list;
117 unsigned page_shift;
118
119 uint32_t tile_mode;
120 uint32_t tile_flags;
121 struct nouveau_tile_reg *tile;
122
123 struct drm_gem_object *gem;
124 int pin_refcnt;
125 };
126
127 #define nouveau_bo_tile_layout(nvbo) \
128 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
129
130 static inline struct nouveau_bo *
nouveau_bo(struct ttm_buffer_object * bo)131 nouveau_bo(struct ttm_buffer_object *bo)
132 {
133 return container_of(bo, struct nouveau_bo, bo);
134 }
135
136 static inline struct nouveau_bo *
nouveau_gem_object(struct drm_gem_object * gem)137 nouveau_gem_object(struct drm_gem_object *gem)
138 {
139 return gem ? gem->driver_private : NULL;
140 }
141
142 /* TODO: submit equivalent to TTM generic API upstream? */
143 static inline void __iomem *
nvbo_kmap_obj_iovirtual(struct nouveau_bo * nvbo)144 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
145 {
146 bool is_iomem;
147 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
148 &nvbo->kmap, &is_iomem);
149 WARN_ON_ONCE(ioptr && !is_iomem);
150 return ioptr;
151 }
152
153 enum nouveau_flags {
154 NV_NFORCE = 0x10000000,
155 NV_NFORCE2 = 0x20000000
156 };
157
158 #define NVOBJ_ENGINE_SW 0
159 #define NVOBJ_ENGINE_GR 1
160 #define NVOBJ_ENGINE_CRYPT 2
161 #define NVOBJ_ENGINE_COPY0 3
162 #define NVOBJ_ENGINE_COPY1 4
163 #define NVOBJ_ENGINE_MPEG 5
164 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
165 #define NVOBJ_ENGINE_BSP 6
166 #define NVOBJ_ENGINE_VP 7
167 #define NVOBJ_ENGINE_DISPLAY 15
168 #define NVOBJ_ENGINE_NR 16
169
170 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
171 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
172 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
173 #define NVOBJ_FLAG_VM (1 << 3)
174 #define NVOBJ_FLAG_VM_USER (1 << 4)
175
176 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
177
178 struct nouveau_gpuobj {
179 struct drm_device *dev;
180 struct kref refcount;
181 struct list_head list;
182
183 void *node;
184 u32 *suspend;
185
186 uint32_t flags;
187
188 u32 size;
189 u32 pinst; /* PRAMIN BAR offset */
190 u32 cinst; /* Channel offset */
191 u64 vinst; /* VRAM address */
192 u64 linst; /* VM address */
193
194 uint32_t engine;
195 uint32_t class;
196
197 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
198 void *priv;
199 };
200
201 struct nouveau_page_flip_state {
202 struct list_head head;
203 struct drm_pending_vblank_event *event;
204 int crtc, bpp, pitch, x, y;
205 uint64_t offset;
206 };
207
208 enum nouveau_channel_mutex_class {
209 NOUVEAU_UCHANNEL_MUTEX,
210 NOUVEAU_KCHANNEL_MUTEX
211 };
212
213 struct nouveau_channel {
214 struct drm_device *dev;
215 struct list_head list;
216 int id;
217
218 /* references to the channel data structure */
219 struct kref ref;
220 /* users of the hardware channel resources, the hardware
221 * context will be kicked off when it reaches zero. */
222 atomic_t users;
223 struct mutex mutex;
224
225 /* owner of this fifo */
226 struct drm_file *file_priv;
227 /* mapping of the fifo itself */
228 struct drm_local_map *map;
229
230 /* mapping of the regs controlling the fifo */
231 void __iomem *user;
232 uint32_t user_get;
233 uint32_t user_get_hi;
234 uint32_t user_put;
235
236 /* Fencing */
237 struct {
238 /* lock protects the pending list only */
239 spinlock_t lock;
240 struct list_head pending;
241 uint32_t sequence;
242 uint32_t sequence_ack;
243 atomic_t last_sequence_irq;
244 struct nouveau_vma vma;
245 } fence;
246
247 /* DMA push buffer */
248 struct nouveau_gpuobj *pushbuf;
249 struct nouveau_bo *pushbuf_bo;
250 struct nouveau_vma pushbuf_vma;
251 uint64_t pushbuf_base;
252
253 /* Notifier memory */
254 struct nouveau_bo *notifier_bo;
255 struct nouveau_vma notifier_vma;
256 struct drm_mm notifier_heap;
257
258 /* PFIFO context */
259 struct nouveau_gpuobj *ramfc;
260 struct nouveau_gpuobj *cache;
261 void *fifo_priv;
262
263 /* Execution engine contexts */
264 void *engctx[NVOBJ_ENGINE_NR];
265
266 /* NV50 VM */
267 struct nouveau_vm *vm;
268 struct nouveau_gpuobj *vm_pd;
269
270 /* Objects */
271 struct nouveau_gpuobj *ramin; /* Private instmem */
272 struct drm_mm ramin_heap; /* Private PRAMIN heap */
273 struct nouveau_ramht *ramht; /* Hash table */
274
275 /* GPU object info for stuff used in-kernel (mm_enabled) */
276 uint32_t m2mf_ntfy;
277 uint32_t vram_handle;
278 uint32_t gart_handle;
279 bool accel_done;
280
281 /* Push buffer state (only for drm's channel on !mm_enabled) */
282 struct {
283 int max;
284 int free;
285 int cur;
286 int put;
287 /* access via pushbuf_bo */
288
289 int ib_base;
290 int ib_max;
291 int ib_free;
292 int ib_put;
293 } dma;
294
295 uint32_t sw_subchannel[8];
296
297 struct nouveau_vma dispc_vma[4];
298 struct {
299 struct nouveau_gpuobj *vblsem;
300 uint32_t vblsem_head;
301 uint32_t vblsem_offset;
302 uint32_t vblsem_rval;
303 struct list_head vbl_wait;
304 struct list_head flip;
305 } nvsw;
306
307 struct {
308 bool active;
309 char name[32];
310 struct drm_info_list info;
311 } debugfs;
312 };
313
314 struct nouveau_exec_engine {
315 void (*destroy)(struct drm_device *, int engine);
316 int (*init)(struct drm_device *, int engine);
317 int (*fini)(struct drm_device *, int engine, bool suspend);
318 int (*context_new)(struct nouveau_channel *, int engine);
319 void (*context_del)(struct nouveau_channel *, int engine);
320 int (*object_new)(struct nouveau_channel *, int engine,
321 u32 handle, u16 class);
322 void (*set_tile_region)(struct drm_device *dev, int i);
323 void (*tlb_flush)(struct drm_device *, int engine);
324 };
325
326 struct nouveau_instmem_engine {
327 void *priv;
328
329 int (*init)(struct drm_device *dev);
330 void (*takedown)(struct drm_device *dev);
331 int (*suspend)(struct drm_device *dev);
332 void (*resume)(struct drm_device *dev);
333
334 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
335 u32 size, u32 align);
336 void (*put)(struct nouveau_gpuobj *);
337 int (*map)(struct nouveau_gpuobj *);
338 void (*unmap)(struct nouveau_gpuobj *);
339
340 void (*flush)(struct drm_device *);
341 };
342
343 struct nouveau_mc_engine {
344 int (*init)(struct drm_device *dev);
345 void (*takedown)(struct drm_device *dev);
346 };
347
348 struct nouveau_timer_engine {
349 int (*init)(struct drm_device *dev);
350 void (*takedown)(struct drm_device *dev);
351 uint64_t (*read)(struct drm_device *dev);
352 };
353
354 struct nouveau_fb_engine {
355 int num_tiles;
356 struct drm_mm tag_heap;
357 void *priv;
358
359 int (*init)(struct drm_device *dev);
360 void (*takedown)(struct drm_device *dev);
361
362 void (*init_tile_region)(struct drm_device *dev, int i,
363 uint32_t addr, uint32_t size,
364 uint32_t pitch, uint32_t flags);
365 void (*set_tile_region)(struct drm_device *dev, int i);
366 void (*free_tile_region)(struct drm_device *dev, int i);
367 };
368
369 struct nouveau_fifo_engine {
370 void *priv;
371 int channels;
372
373 struct nouveau_gpuobj *playlist[2];
374 int cur_playlist;
375
376 int (*init)(struct drm_device *);
377 void (*takedown)(struct drm_device *);
378
379 void (*disable)(struct drm_device *);
380 void (*enable)(struct drm_device *);
381 bool (*reassign)(struct drm_device *, bool enable);
382 bool (*cache_pull)(struct drm_device *dev, bool enable);
383
384 int (*channel_id)(struct drm_device *);
385
386 int (*create_context)(struct nouveau_channel *);
387 void (*destroy_context)(struct nouveau_channel *);
388 int (*load_context)(struct nouveau_channel *);
389 int (*unload_context)(struct drm_device *);
390 void (*tlb_flush)(struct drm_device *dev);
391 };
392
393 struct nouveau_display_engine {
394 void *priv;
395 int (*early_init)(struct drm_device *);
396 void (*late_takedown)(struct drm_device *);
397 int (*create)(struct drm_device *);
398 void (*destroy)(struct drm_device *);
399 int (*init)(struct drm_device *);
400 void (*fini)(struct drm_device *);
401
402 struct drm_property *dithering_mode;
403 struct drm_property *dithering_depth;
404 struct drm_property *underscan_property;
405 struct drm_property *underscan_hborder_property;
406 struct drm_property *underscan_vborder_property;
407 /* not really hue and saturation: */
408 struct drm_property *vibrant_hue_property;
409 struct drm_property *color_vibrance_property;
410 };
411
412 struct nouveau_gpio_engine {
413 spinlock_t lock;
414 struct list_head isr;
415 int (*init)(struct drm_device *);
416 void (*fini)(struct drm_device *);
417 int (*drive)(struct drm_device *, int line, int dir, int out);
418 int (*sense)(struct drm_device *, int line);
419 void (*irq_enable)(struct drm_device *, int line, bool);
420 };
421
422 struct nouveau_pm_voltage_level {
423 u32 voltage; /* microvolts */
424 u8 vid;
425 };
426
427 struct nouveau_pm_voltage {
428 bool supported;
429 u8 version;
430 u8 vid_mask;
431
432 struct nouveau_pm_voltage_level *level;
433 int nr_level;
434 };
435
436 /* Exclusive upper limits */
437 #define NV_MEM_CL_DDR2_MAX 8
438 #define NV_MEM_WR_DDR2_MAX 9
439 #define NV_MEM_CL_DDR3_MAX 17
440 #define NV_MEM_WR_DDR3_MAX 17
441 #define NV_MEM_CL_GDDR3_MAX 16
442 #define NV_MEM_WR_GDDR3_MAX 18
443 #define NV_MEM_CL_GDDR5_MAX 21
444 #define NV_MEM_WR_GDDR5_MAX 20
445
446 struct nouveau_pm_memtiming {
447 int id;
448
449 u32 reg[9];
450 u32 mr[4];
451
452 u8 tCWL;
453
454 u8 odt;
455 u8 drive_strength;
456 };
457
458 struct nouveau_pm_tbl_header {
459 u8 version;
460 u8 header_len;
461 u8 entry_cnt;
462 u8 entry_len;
463 };
464
465 struct nouveau_pm_tbl_entry {
466 u8 tWR;
467 u8 tWTR;
468 u8 tCL;
469 u8 tRC;
470 u8 empty_4;
471 u8 tRFC; /* Byte 5 */
472 u8 empty_6;
473 u8 tRAS; /* Byte 7 */
474 u8 empty_8;
475 u8 tRP; /* Byte 9 */
476 u8 tRCDRD;
477 u8 tRCDWR;
478 u8 tRRD;
479 u8 tUNK_13;
480 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
481 u8 empty_15;
482 u8 tUNK_16;
483 u8 empty_17;
484 u8 tUNK_18;
485 u8 tCWL;
486 u8 tUNK_20, tUNK_21;
487 };
488
489 struct nouveau_pm_profile;
490 struct nouveau_pm_profile_func {
491 void (*destroy)(struct nouveau_pm_profile *);
492 void (*init)(struct nouveau_pm_profile *);
493 void (*fini)(struct nouveau_pm_profile *);
494 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
495 };
496
497 struct nouveau_pm_profile {
498 const struct nouveau_pm_profile_func *func;
499 struct list_head head;
500 char name[8];
501 };
502
503 #define NOUVEAU_PM_MAX_LEVEL 8
504 struct nouveau_pm_level {
505 struct nouveau_pm_profile profile;
506 struct device_attribute dev_attr;
507 char name[32];
508 int id;
509
510 struct nouveau_pm_memtiming timing;
511 u32 memory;
512 u16 memscript;
513
514 u32 core;
515 u32 shader;
516 u32 rop;
517 u32 copy;
518 u32 daemon;
519 u32 vdec;
520 u32 dom6;
521 u32 unka0; /* nva3:nvc0 */
522 u32 hub01; /* nvc0- */
523 u32 hub06; /* nvc0- */
524 u32 hub07; /* nvc0- */
525
526 u32 volt_min; /* microvolts */
527 u32 volt_max;
528 u8 fanspeed;
529 };
530
531 struct nouveau_pm_temp_sensor_constants {
532 u16 offset_constant;
533 s16 offset_mult;
534 s16 offset_div;
535 s16 slope_mult;
536 s16 slope_div;
537 };
538
539 struct nouveau_pm_threshold_temp {
540 s16 critical;
541 s16 down_clock;
542 s16 fan_boost;
543 };
544
545 struct nouveau_pm_fan {
546 u32 percent;
547 u32 min_duty;
548 u32 max_duty;
549 u32 pwm_freq;
550 u32 pwm_divisor;
551 };
552
553 struct nouveau_pm_engine {
554 struct nouveau_pm_voltage voltage;
555 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
556 int nr_perflvl;
557 struct nouveau_pm_temp_sensor_constants sensor_constants;
558 struct nouveau_pm_threshold_temp threshold_temp;
559 struct nouveau_pm_fan fan;
560
561 struct nouveau_pm_profile *profile_ac;
562 struct nouveau_pm_profile *profile_dc;
563 struct nouveau_pm_profile *profile;
564 struct list_head profiles;
565
566 struct nouveau_pm_level boot;
567 struct nouveau_pm_level *cur;
568
569 struct device *hwmon;
570 struct notifier_block acpi_nb;
571
572 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
573 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
574 int (*clocks_set)(struct drm_device *, void *);
575
576 int (*voltage_get)(struct drm_device *);
577 int (*voltage_set)(struct drm_device *, int voltage);
578 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
579 int (*pwm_set)(struct drm_device *, int line, u32, u32);
580 int (*temp_get)(struct drm_device *);
581 };
582
583 struct nouveau_vram_engine {
584 struct nouveau_mm mm;
585
586 int (*init)(struct drm_device *);
587 void (*takedown)(struct drm_device *dev);
588 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
589 u32 type, struct nouveau_mem **);
590 void (*put)(struct drm_device *, struct nouveau_mem **);
591
592 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
593 };
594
595 struct nouveau_engine {
596 struct nouveau_instmem_engine instmem;
597 struct nouveau_mc_engine mc;
598 struct nouveau_timer_engine timer;
599 struct nouveau_fb_engine fb;
600 struct nouveau_fifo_engine fifo;
601 struct nouveau_display_engine display;
602 struct nouveau_gpio_engine gpio;
603 struct nouveau_pm_engine pm;
604 struct nouveau_vram_engine vram;
605 };
606
607 struct nouveau_pll_vals {
608 union {
609 struct {
610 #ifdef __BIG_ENDIAN
611 uint8_t N1, M1, N2, M2;
612 #else
613 uint8_t M1, N1, M2, N2;
614 #endif
615 };
616 struct {
617 uint16_t NM1, NM2;
618 } __attribute__((packed));
619 };
620 int log2P;
621
622 int refclk;
623 };
624
625 enum nv04_fp_display_regs {
626 FP_DISPLAY_END,
627 FP_TOTAL,
628 FP_CRTC,
629 FP_SYNC_START,
630 FP_SYNC_END,
631 FP_VALID_START,
632 FP_VALID_END
633 };
634
635 struct nv04_crtc_reg {
636 unsigned char MiscOutReg;
637 uint8_t CRTC[0xa0];
638 uint8_t CR58[0x10];
639 uint8_t Sequencer[5];
640 uint8_t Graphics[9];
641 uint8_t Attribute[21];
642 unsigned char DAC[768];
643
644 /* PCRTC regs */
645 uint32_t fb_start;
646 uint32_t crtc_cfg;
647 uint32_t cursor_cfg;
648 uint32_t gpio_ext;
649 uint32_t crtc_830;
650 uint32_t crtc_834;
651 uint32_t crtc_850;
652 uint32_t crtc_eng_ctrl;
653
654 /* PRAMDAC regs */
655 uint32_t nv10_cursync;
656 struct nouveau_pll_vals pllvals;
657 uint32_t ramdac_gen_ctrl;
658 uint32_t ramdac_630;
659 uint32_t ramdac_634;
660 uint32_t tv_setup;
661 uint32_t tv_vtotal;
662 uint32_t tv_vskew;
663 uint32_t tv_vsync_delay;
664 uint32_t tv_htotal;
665 uint32_t tv_hskew;
666 uint32_t tv_hsync_delay;
667 uint32_t tv_hsync_delay2;
668 uint32_t fp_horiz_regs[7];
669 uint32_t fp_vert_regs[7];
670 uint32_t dither;
671 uint32_t fp_control;
672 uint32_t dither_regs[6];
673 uint32_t fp_debug_0;
674 uint32_t fp_debug_1;
675 uint32_t fp_debug_2;
676 uint32_t fp_margin_color;
677 uint32_t ramdac_8c0;
678 uint32_t ramdac_a20;
679 uint32_t ramdac_a24;
680 uint32_t ramdac_a34;
681 uint32_t ctv_regs[38];
682 };
683
684 struct nv04_output_reg {
685 uint32_t output;
686 int head;
687 };
688
689 struct nv04_mode_state {
690 struct nv04_crtc_reg crtc_reg[2];
691 uint32_t pllsel;
692 uint32_t sel_clk;
693 };
694
695 enum nouveau_card_type {
696 NV_04 = 0x04,
697 NV_10 = 0x10,
698 NV_20 = 0x20,
699 NV_30 = 0x30,
700 NV_40 = 0x40,
701 NV_50 = 0x50,
702 NV_C0 = 0xc0,
703 NV_D0 = 0xd0,
704 NV_E0 = 0xe0,
705 };
706
707 struct drm_nouveau_private {
708 struct drm_device *dev;
709 bool noaccel;
710
711 /* the card type, takes NV_* as values */
712 enum nouveau_card_type card_type;
713 /* exact chipset, derived from NV_PMC_BOOT_0 */
714 int chipset;
715 int flags;
716 u32 crystal;
717
718 void __iomem *mmio;
719
720 spinlock_t ramin_lock;
721 void __iomem *ramin;
722 u32 ramin_size;
723 u32 ramin_base;
724 bool ramin_available;
725 struct drm_mm ramin_heap;
726 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
727 struct list_head gpuobj_list;
728 struct list_head classes;
729
730 struct nouveau_bo *vga_ram;
731
732 /* interrupt handling */
733 void (*irq_handler[32])(struct drm_device *);
734 bool msi_enabled;
735
736 struct list_head vbl_waiting;
737
738 struct {
739 struct drm_global_reference mem_global_ref;
740 struct ttm_bo_global_ref bo_global_ref;
741 struct ttm_bo_device bdev;
742 atomic_t validate_sequence;
743 } ttm;
744
745 struct {
746 spinlock_t lock;
747 struct drm_mm heap;
748 struct nouveau_bo *bo;
749 } fence;
750
751 struct {
752 spinlock_t lock;
753 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
754 } channels;
755
756 struct nouveau_engine engine;
757 struct nouveau_channel *channel;
758
759 /* For PFIFO and PGRAPH. */
760 spinlock_t context_switch_lock;
761
762 /* VM/PRAMIN flush, legacy PRAMIN aperture */
763 spinlock_t vm_lock;
764
765 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
766 struct nouveau_ramht *ramht;
767 struct nouveau_gpuobj *ramfc;
768 struct nouveau_gpuobj *ramro;
769
770 uint32_t ramin_rsvd_vram;
771
772 struct {
773 enum {
774 NOUVEAU_GART_NONE = 0,
775 NOUVEAU_GART_AGP, /* AGP */
776 NOUVEAU_GART_PDMA, /* paged dma object */
777 NOUVEAU_GART_HW /* on-chip gart/vm */
778 } type;
779 uint64_t aper_base;
780 uint64_t aper_size;
781 uint64_t aper_free;
782
783 struct ttm_backend_func *func;
784
785 struct {
786 struct page *page;
787 dma_addr_t addr;
788 } dummy;
789
790 struct nouveau_gpuobj *sg_ctxdma;
791 } gart_info;
792
793 /* nv10-nv40 tiling regions */
794 struct {
795 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
796 spinlock_t lock;
797 } tile;
798
799 /* VRAM/fb configuration */
800 enum {
801 NV_MEM_TYPE_UNKNOWN = 0,
802 NV_MEM_TYPE_STOLEN,
803 NV_MEM_TYPE_SGRAM,
804 NV_MEM_TYPE_SDRAM,
805 NV_MEM_TYPE_DDR1,
806 NV_MEM_TYPE_DDR2,
807 NV_MEM_TYPE_DDR3,
808 NV_MEM_TYPE_GDDR2,
809 NV_MEM_TYPE_GDDR3,
810 NV_MEM_TYPE_GDDR4,
811 NV_MEM_TYPE_GDDR5
812 } vram_type;
813 uint64_t vram_size;
814 uint64_t vram_sys_base;
815 bool vram_rank_B;
816
817 uint64_t fb_available_size;
818 uint64_t fb_mappable_pages;
819 uint64_t fb_aper_free;
820 int fb_mtrr;
821
822 /* BAR control (NV50-) */
823 struct nouveau_vm *bar1_vm;
824 struct nouveau_vm *bar3_vm;
825
826 /* G8x/G9x virtual address space */
827 struct nouveau_vm *chan_vm;
828
829 struct nvbios vbios;
830 u8 *mxms;
831 struct list_head i2c_ports;
832
833 struct nv04_mode_state mode_reg;
834 struct nv04_mode_state saved_reg;
835 uint32_t saved_vga_font[4][16384];
836 uint32_t crtc_owner;
837 uint32_t dac_users[4];
838
839 struct backlight_device *backlight;
840
841 struct {
842 struct dentry *channel_root;
843 } debugfs;
844
845 struct nouveau_fbdev *nfbdev;
846 struct apertures_struct *apertures;
847 };
848
849 static inline struct drm_nouveau_private *
nouveau_private(struct drm_device * dev)850 nouveau_private(struct drm_device *dev)
851 {
852 return dev->dev_private;
853 }
854
855 static inline struct drm_nouveau_private *
nouveau_bdev(struct ttm_bo_device * bd)856 nouveau_bdev(struct ttm_bo_device *bd)
857 {
858 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
859 }
860
861 static inline int
nouveau_bo_ref(struct nouveau_bo * ref,struct nouveau_bo ** pnvbo)862 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
863 {
864 struct nouveau_bo *prev;
865
866 if (!pnvbo)
867 return -EINVAL;
868 prev = *pnvbo;
869
870 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
871 if (prev) {
872 struct ttm_buffer_object *bo = &prev->bo;
873
874 ttm_bo_unref(&bo);
875 }
876
877 return 0;
878 }
879
880 /* nouveau_drv.c */
881 extern int nouveau_modeset;
882 extern int nouveau_agpmode;
883 extern int nouveau_duallink;
884 extern int nouveau_uscript_lvds;
885 extern int nouveau_uscript_tmds;
886 extern int nouveau_vram_pushbuf;
887 extern int nouveau_vram_notify;
888 extern char *nouveau_vram_type;
889 extern int nouveau_fbpercrtc;
890 extern int nouveau_tv_disable;
891 extern char *nouveau_tv_norm;
892 extern int nouveau_reg_debug;
893 extern char *nouveau_vbios;
894 extern int nouveau_ignorelid;
895 extern int nouveau_nofbaccel;
896 extern int nouveau_noaccel;
897 extern int nouveau_force_post;
898 extern int nouveau_override_conntype;
899 extern char *nouveau_perflvl;
900 extern int nouveau_perflvl_wr;
901 extern int nouveau_msi;
902 extern int nouveau_ctxfw;
903 extern int nouveau_mxmdcb;
904
905 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
906 extern int nouveau_pci_resume(struct pci_dev *pdev);
907
908 /* nouveau_state.c */
909 extern int nouveau_open(struct drm_device *, struct drm_file *);
910 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
911 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
912 extern int nouveau_load(struct drm_device *, unsigned long flags);
913 extern int nouveau_firstopen(struct drm_device *);
914 extern void nouveau_lastclose(struct drm_device *);
915 extern int nouveau_unload(struct drm_device *);
916 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
917 struct drm_file *);
918 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
919 struct drm_file *);
920 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
921 uint32_t reg, uint32_t mask, uint32_t val);
922 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
923 uint32_t reg, uint32_t mask, uint32_t val);
924 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
925 bool (*cond)(void *), void *);
926 extern bool nouveau_wait_for_idle(struct drm_device *);
927 extern int nouveau_card_init(struct drm_device *);
928
929 /* nouveau_mem.c */
930 extern int nouveau_mem_vram_init(struct drm_device *);
931 extern void nouveau_mem_vram_fini(struct drm_device *);
932 extern int nouveau_mem_gart_init(struct drm_device *);
933 extern void nouveau_mem_gart_fini(struct drm_device *);
934 extern int nouveau_mem_init_agp(struct drm_device *);
935 extern int nouveau_mem_reset_agp(struct drm_device *);
936 extern void nouveau_mem_close(struct drm_device *);
937 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
938 extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
939 struct nouveau_pm_memtiming *);
940 extern void nouveau_mem_timing_read(struct drm_device *,
941 struct nouveau_pm_memtiming *);
942 extern int nouveau_mem_vbios_type(struct drm_device *);
943 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
944 struct drm_device *dev, uint32_t addr, uint32_t size,
945 uint32_t pitch, uint32_t flags);
946 extern void nv10_mem_put_tile_region(struct drm_device *dev,
947 struct nouveau_tile_reg *tile,
948 struct nouveau_fence *fence);
949 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
950 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
951
952 /* nouveau_notifier.c */
953 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
954 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
955 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
956 int cout, uint32_t start, uint32_t end,
957 uint32_t *offset);
958 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
959 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
960 struct drm_file *);
961 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
962 struct drm_file *);
963
964 /* nouveau_channel.c */
965 extern struct drm_ioctl_desc nouveau_ioctls[];
966 extern int nouveau_max_ioctl;
967 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
968 extern int nouveau_channel_alloc(struct drm_device *dev,
969 struct nouveau_channel **chan,
970 struct drm_file *file_priv,
971 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
972 extern struct nouveau_channel *
973 nouveau_channel_get_unlocked(struct nouveau_channel *);
974 extern struct nouveau_channel *
975 nouveau_channel_get(struct drm_file *, int id);
976 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
977 extern void nouveau_channel_put(struct nouveau_channel **);
978 extern void nouveau_channel_ref(struct nouveau_channel *chan,
979 struct nouveau_channel **pchan);
980 extern void nouveau_channel_idle(struct nouveau_channel *chan);
981
982 /* nouveau_object.c */
983 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
984 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
985 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
986 } while (0)
987
988 #define NVOBJ_ENGINE_DEL(d, e) do { \
989 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
990 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
991 } while (0)
992
993 #define NVOBJ_CLASS(d, c, e) do { \
994 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
995 if (ret) \
996 return ret; \
997 } while (0)
998
999 #define NVOBJ_MTHD(d, c, m, e) do { \
1000 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
1001 if (ret) \
1002 return ret; \
1003 } while (0)
1004
1005 extern int nouveau_gpuobj_early_init(struct drm_device *);
1006 extern int nouveau_gpuobj_init(struct drm_device *);
1007 extern void nouveau_gpuobj_takedown(struct drm_device *);
1008 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
1009 extern void nouveau_gpuobj_resume(struct drm_device *dev);
1010 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
1011 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
1012 int (*exec)(struct nouveau_channel *,
1013 u32 class, u32 mthd, u32 data));
1014 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
1015 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
1016 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
1017 uint32_t vram_h, uint32_t tt_h);
1018 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
1019 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
1020 uint32_t size, int align, uint32_t flags,
1021 struct nouveau_gpuobj **);
1022 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
1023 struct nouveau_gpuobj **);
1024 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
1025 u32 size, u32 flags,
1026 struct nouveau_gpuobj **);
1027 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
1028 uint64_t offset, uint64_t size, int access,
1029 int target, struct nouveau_gpuobj **);
1030 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
1031 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
1032 u64 size, int target, int access, u32 type,
1033 u32 comp, struct nouveau_gpuobj **pobj);
1034 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
1035 int class, u64 base, u64 size, int target,
1036 int access, u32 type, u32 comp);
1037 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
1038 struct drm_file *);
1039 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
1040 struct drm_file *);
1041
1042 /* nouveau_irq.c */
1043 extern int nouveau_irq_init(struct drm_device *);
1044 extern void nouveau_irq_fini(struct drm_device *);
1045 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
1046 extern void nouveau_irq_register(struct drm_device *, int status_bit,
1047 void (*)(struct drm_device *));
1048 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
1049 extern void nouveau_irq_preinstall(struct drm_device *);
1050 extern int nouveau_irq_postinstall(struct drm_device *);
1051 extern void nouveau_irq_uninstall(struct drm_device *);
1052
1053 /* nouveau_sgdma.c */
1054 extern int nouveau_sgdma_init(struct drm_device *);
1055 extern void nouveau_sgdma_takedown(struct drm_device *);
1056 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1057 uint32_t offset);
1058 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1059 unsigned long size,
1060 uint32_t page_flags,
1061 struct page *dummy_read_page);
1062
1063 /* nouveau_debugfs.c */
1064 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1065 extern int nouveau_debugfs_init(struct drm_minor *);
1066 extern void nouveau_debugfs_takedown(struct drm_minor *);
1067 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1068 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1069 #else
1070 static inline int
nouveau_debugfs_init(struct drm_minor * minor)1071 nouveau_debugfs_init(struct drm_minor *minor)
1072 {
1073 return 0;
1074 }
1075
nouveau_debugfs_takedown(struct drm_minor * minor)1076 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1077 {
1078 }
1079
1080 static inline int
nouveau_debugfs_channel_init(struct nouveau_channel * chan)1081 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1082 {
1083 return 0;
1084 }
1085
1086 static inline void
nouveau_debugfs_channel_fini(struct nouveau_channel * chan)1087 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1088 {
1089 }
1090 #endif
1091
1092 /* nouveau_dma.c */
1093 extern void nouveau_dma_init(struct nouveau_channel *);
1094 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1095
1096 /* nouveau_acpi.c */
1097 #define ROM_BIOS_PAGE 4096
1098 #if defined(CONFIG_ACPI)
1099 void nouveau_register_dsm_handler(void);
1100 void nouveau_unregister_dsm_handler(void);
1101 void nouveau_switcheroo_optimus_dsm(void);
1102 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1103 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1104 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1105 #else
nouveau_register_dsm_handler(void)1106 static inline void nouveau_register_dsm_handler(void) {}
nouveau_unregister_dsm_handler(void)1107 static inline void nouveau_unregister_dsm_handler(void) {}
nouveau_switcheroo_optimus_dsm(void)1108 static inline void nouveau_switcheroo_optimus_dsm(void) {}
nouveau_acpi_rom_supported(struct pci_dev * pdev)1109 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
nouveau_acpi_get_bios_chunk(uint8_t * bios,int offset,int len)1110 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
nouveau_acpi_edid(struct drm_device * dev,struct drm_connector * connector)1111 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1112 #endif
1113
1114 /* nouveau_backlight.c */
1115 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1116 extern int nouveau_backlight_init(struct drm_device *);
1117 extern void nouveau_backlight_exit(struct drm_device *);
1118 #else
nouveau_backlight_init(struct drm_device * dev)1119 static inline int nouveau_backlight_init(struct drm_device *dev)
1120 {
1121 return 0;
1122 }
1123
nouveau_backlight_exit(struct drm_device * dev)1124 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1125 #endif
1126
1127 /* nouveau_bios.c */
1128 extern int nouveau_bios_init(struct drm_device *);
1129 extern void nouveau_bios_takedown(struct drm_device *dev);
1130 extern int nouveau_run_vbios_init(struct drm_device *);
1131 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1132 struct dcb_entry *, int crtc);
1133 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1134 extern struct dcb_connector_table_entry *
1135 nouveau_bios_connector_entry(struct drm_device *, int index);
1136 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1137 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1138 struct pll_lims *);
1139 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1140 struct dcb_entry *, int crtc);
1141 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1142 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1143 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1144 bool *dl, bool *if_is_24bit);
1145 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1146 int head, int pxclk);
1147 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1148 enum LVDS_script, int pxclk);
1149 bool bios_encoder_match(struct dcb_entry *, u32 hash);
1150
1151 /* nouveau_mxm.c */
1152 int nouveau_mxm_init(struct drm_device *dev);
1153 void nouveau_mxm_fini(struct drm_device *dev);
1154
1155 /* nouveau_ttm.c */
1156 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1157 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1158 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1159
1160 /* nouveau_hdmi.c */
1161 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1162
1163 /* nv04_fb.c */
1164 extern int nv04_fb_vram_init(struct drm_device *);
1165 extern int nv04_fb_init(struct drm_device *);
1166 extern void nv04_fb_takedown(struct drm_device *);
1167
1168 /* nv10_fb.c */
1169 extern int nv10_fb_vram_init(struct drm_device *dev);
1170 extern int nv1a_fb_vram_init(struct drm_device *dev);
1171 extern int nv10_fb_init(struct drm_device *);
1172 extern void nv10_fb_takedown(struct drm_device *);
1173 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1174 uint32_t addr, uint32_t size,
1175 uint32_t pitch, uint32_t flags);
1176 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1177 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1178
1179 /* nv20_fb.c */
1180 extern int nv20_fb_vram_init(struct drm_device *dev);
1181 extern int nv20_fb_init(struct drm_device *);
1182 extern void nv20_fb_takedown(struct drm_device *);
1183 extern void nv20_fb_init_tile_region(struct drm_device *dev, int i,
1184 uint32_t addr, uint32_t size,
1185 uint32_t pitch, uint32_t flags);
1186 extern void nv20_fb_set_tile_region(struct drm_device *dev, int i);
1187 extern void nv20_fb_free_tile_region(struct drm_device *dev, int i);
1188
1189 /* nv30_fb.c */
1190 extern int nv30_fb_init(struct drm_device *);
1191 extern void nv30_fb_takedown(struct drm_device *);
1192 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1193 uint32_t addr, uint32_t size,
1194 uint32_t pitch, uint32_t flags);
1195 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1196
1197 /* nv40_fb.c */
1198 extern int nv40_fb_vram_init(struct drm_device *dev);
1199 extern int nv40_fb_init(struct drm_device *);
1200 extern void nv40_fb_takedown(struct drm_device *);
1201 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1202
1203 /* nv50_fb.c */
1204 extern int nv50_fb_init(struct drm_device *);
1205 extern void nv50_fb_takedown(struct drm_device *);
1206 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1207
1208 /* nvc0_fb.c */
1209 extern int nvc0_fb_init(struct drm_device *);
1210 extern void nvc0_fb_takedown(struct drm_device *);
1211
1212 /* nv04_fifo.c */
1213 extern int nv04_fifo_init(struct drm_device *);
1214 extern void nv04_fifo_fini(struct drm_device *);
1215 extern void nv04_fifo_disable(struct drm_device *);
1216 extern void nv04_fifo_enable(struct drm_device *);
1217 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1218 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1219 extern int nv04_fifo_channel_id(struct drm_device *);
1220 extern int nv04_fifo_create_context(struct nouveau_channel *);
1221 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1222 extern int nv04_fifo_load_context(struct nouveau_channel *);
1223 extern int nv04_fifo_unload_context(struct drm_device *);
1224 extern void nv04_fifo_isr(struct drm_device *);
1225
1226 /* nv10_fifo.c */
1227 extern int nv10_fifo_init(struct drm_device *);
1228 extern int nv10_fifo_channel_id(struct drm_device *);
1229 extern int nv10_fifo_create_context(struct nouveau_channel *);
1230 extern int nv10_fifo_load_context(struct nouveau_channel *);
1231 extern int nv10_fifo_unload_context(struct drm_device *);
1232
1233 /* nv40_fifo.c */
1234 extern int nv40_fifo_init(struct drm_device *);
1235 extern int nv40_fifo_create_context(struct nouveau_channel *);
1236 extern int nv40_fifo_load_context(struct nouveau_channel *);
1237 extern int nv40_fifo_unload_context(struct drm_device *);
1238
1239 /* nv50_fifo.c */
1240 extern int nv50_fifo_init(struct drm_device *);
1241 extern void nv50_fifo_takedown(struct drm_device *);
1242 extern int nv50_fifo_channel_id(struct drm_device *);
1243 extern int nv50_fifo_create_context(struct nouveau_channel *);
1244 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1245 extern int nv50_fifo_load_context(struct nouveau_channel *);
1246 extern int nv50_fifo_unload_context(struct drm_device *);
1247 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1248
1249 /* nvc0_fifo.c */
1250 extern int nvc0_fifo_init(struct drm_device *);
1251 extern void nvc0_fifo_takedown(struct drm_device *);
1252 extern void nvc0_fifo_disable(struct drm_device *);
1253 extern void nvc0_fifo_enable(struct drm_device *);
1254 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1255 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1256 extern int nvc0_fifo_channel_id(struct drm_device *);
1257 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1258 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1259 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1260 extern int nvc0_fifo_unload_context(struct drm_device *);
1261
1262 /* nv04_graph.c */
1263 extern int nv04_graph_create(struct drm_device *);
1264 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1265 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1266 u32 class, u32 mthd, u32 data);
1267 extern struct nouveau_bitfield nv04_graph_nsource[];
1268
1269 /* nv10_graph.c */
1270 extern int nv10_graph_create(struct drm_device *);
1271 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1272 extern struct nouveau_bitfield nv10_graph_intr[];
1273 extern struct nouveau_bitfield nv10_graph_nstatus[];
1274
1275 /* nv20_graph.c */
1276 extern int nv20_graph_create(struct drm_device *);
1277
1278 /* nv40_graph.c */
1279 extern int nv40_graph_create(struct drm_device *);
1280 extern void nv40_grctx_init(struct nouveau_grctx *);
1281
1282 /* nv50_graph.c */
1283 extern int nv50_graph_create(struct drm_device *);
1284 extern int nv50_grctx_init(struct nouveau_grctx *);
1285 extern struct nouveau_enum nv50_data_error_names[];
1286 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1287
1288 /* nvc0_graph.c */
1289 extern int nvc0_graph_create(struct drm_device *);
1290 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1291
1292 /* nv84_crypt.c */
1293 extern int nv84_crypt_create(struct drm_device *);
1294
1295 /* nv98_crypt.c */
1296 extern int nv98_crypt_create(struct drm_device *dev);
1297
1298 /* nva3_copy.c */
1299 extern int nva3_copy_create(struct drm_device *dev);
1300
1301 /* nvc0_copy.c */
1302 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1303
1304 /* nv31_mpeg.c */
1305 extern int nv31_mpeg_create(struct drm_device *dev);
1306
1307 /* nv50_mpeg.c */
1308 extern int nv50_mpeg_create(struct drm_device *dev);
1309
1310 /* nv84_bsp.c */
1311 /* nv98_bsp.c */
1312 extern int nv84_bsp_create(struct drm_device *dev);
1313
1314 /* nv84_vp.c */
1315 /* nv98_vp.c */
1316 extern int nv84_vp_create(struct drm_device *dev);
1317
1318 /* nv98_ppp.c */
1319 extern int nv98_ppp_create(struct drm_device *dev);
1320
1321 /* nv04_instmem.c */
1322 extern int nv04_instmem_init(struct drm_device *);
1323 extern void nv04_instmem_takedown(struct drm_device *);
1324 extern int nv04_instmem_suspend(struct drm_device *);
1325 extern void nv04_instmem_resume(struct drm_device *);
1326 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1327 u32 size, u32 align);
1328 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1329 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1330 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1331 extern void nv04_instmem_flush(struct drm_device *);
1332
1333 /* nv50_instmem.c */
1334 extern int nv50_instmem_init(struct drm_device *);
1335 extern void nv50_instmem_takedown(struct drm_device *);
1336 extern int nv50_instmem_suspend(struct drm_device *);
1337 extern void nv50_instmem_resume(struct drm_device *);
1338 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1339 u32 size, u32 align);
1340 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1341 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1342 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1343 extern void nv50_instmem_flush(struct drm_device *);
1344 extern void nv84_instmem_flush(struct drm_device *);
1345
1346 /* nvc0_instmem.c */
1347 extern int nvc0_instmem_init(struct drm_device *);
1348 extern void nvc0_instmem_takedown(struct drm_device *);
1349 extern int nvc0_instmem_suspend(struct drm_device *);
1350 extern void nvc0_instmem_resume(struct drm_device *);
1351
1352 /* nv04_mc.c */
1353 extern int nv04_mc_init(struct drm_device *);
1354 extern void nv04_mc_takedown(struct drm_device *);
1355
1356 /* nv40_mc.c */
1357 extern int nv40_mc_init(struct drm_device *);
1358 extern void nv40_mc_takedown(struct drm_device *);
1359
1360 /* nv50_mc.c */
1361 extern int nv50_mc_init(struct drm_device *);
1362 extern void nv50_mc_takedown(struct drm_device *);
1363
1364 /* nv04_timer.c */
1365 extern int nv04_timer_init(struct drm_device *);
1366 extern uint64_t nv04_timer_read(struct drm_device *);
1367 extern void nv04_timer_takedown(struct drm_device *);
1368
1369 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1370 unsigned long arg);
1371
1372 /* nv04_dac.c */
1373 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1374 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1375 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1376 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1377 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1378
1379 /* nv04_dfp.c */
1380 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1381 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1382 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1383 int head, bool dl);
1384 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1385 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1386
1387 /* nv04_tv.c */
1388 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1389 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1390
1391 /* nv17_tv.c */
1392 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1393
1394 /* nv04_display.c */
1395 extern int nv04_display_early_init(struct drm_device *);
1396 extern void nv04_display_late_takedown(struct drm_device *);
1397 extern int nv04_display_create(struct drm_device *);
1398 extern void nv04_display_destroy(struct drm_device *);
1399 extern int nv04_display_init(struct drm_device *);
1400 extern void nv04_display_fini(struct drm_device *);
1401
1402 /* nvd0_display.c */
1403 extern int nvd0_display_create(struct drm_device *);
1404 extern void nvd0_display_destroy(struct drm_device *);
1405 extern int nvd0_display_init(struct drm_device *);
1406 extern void nvd0_display_fini(struct drm_device *);
1407 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1408 void nvd0_display_flip_stop(struct drm_crtc *);
1409 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1410 struct nouveau_channel *, u32 swap_interval);
1411
1412 /* nv04_crtc.c */
1413 extern int nv04_crtc_create(struct drm_device *, int index);
1414
1415 /* nouveau_bo.c */
1416 extern struct ttm_bo_driver nouveau_bo_driver;
1417 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1418 uint32_t flags, uint32_t tile_mode,
1419 uint32_t tile_flags, struct nouveau_bo **);
1420 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1421 extern int nouveau_bo_unpin(struct nouveau_bo *);
1422 extern int nouveau_bo_map(struct nouveau_bo *);
1423 extern void nouveau_bo_unmap(struct nouveau_bo *);
1424 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1425 uint32_t busy);
1426 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1427 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1428 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1429 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1430 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1431 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1432 bool no_wait_reserve, bool no_wait_gpu);
1433
1434 extern struct nouveau_vma *
1435 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1436 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1437 struct nouveau_vma *);
1438 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1439
1440 /* nouveau_fence.c */
1441 struct nouveau_fence;
1442 extern int nouveau_fence_init(struct drm_device *);
1443 extern void nouveau_fence_fini(struct drm_device *);
1444 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1445 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1446 extern void nouveau_fence_update(struct nouveau_channel *);
1447 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1448 bool emit);
1449 extern int nouveau_fence_emit(struct nouveau_fence *);
1450 extern void nouveau_fence_work(struct nouveau_fence *fence,
1451 void (*work)(void *priv, bool signalled),
1452 void *priv);
1453 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1454
1455 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1456 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1457 extern int __nouveau_fence_flush(void *obj, void *arg);
1458 extern void __nouveau_fence_unref(void **obj);
1459 extern void *__nouveau_fence_ref(void *obj);
1460
nouveau_fence_signalled(struct nouveau_fence * obj)1461 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1462 {
1463 return __nouveau_fence_signalled(obj, NULL);
1464 }
1465 static inline int
nouveau_fence_wait(struct nouveau_fence * obj,bool lazy,bool intr)1466 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1467 {
1468 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1469 }
1470 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
nouveau_fence_flush(struct nouveau_fence * obj)1471 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1472 {
1473 return __nouveau_fence_flush(obj, NULL);
1474 }
nouveau_fence_unref(struct nouveau_fence ** obj)1475 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1476 {
1477 __nouveau_fence_unref((void **)obj);
1478 }
nouveau_fence_ref(struct nouveau_fence * obj)1479 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1480 {
1481 return __nouveau_fence_ref(obj);
1482 }
1483
1484 /* nouveau_gem.c */
1485 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1486 uint32_t domain, uint32_t tile_mode,
1487 uint32_t tile_flags, struct nouveau_bo **);
1488 extern int nouveau_gem_object_new(struct drm_gem_object *);
1489 extern void nouveau_gem_object_del(struct drm_gem_object *);
1490 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1491 extern void nouveau_gem_object_close(struct drm_gem_object *,
1492 struct drm_file *);
1493 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1494 struct drm_file *);
1495 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1496 struct drm_file *);
1497 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1498 struct drm_file *);
1499 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1500 struct drm_file *);
1501 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1502 struct drm_file *);
1503
1504 /* nouveau_display.c */
1505 int nouveau_display_create(struct drm_device *dev);
1506 void nouveau_display_destroy(struct drm_device *dev);
1507 int nouveau_display_init(struct drm_device *dev);
1508 void nouveau_display_fini(struct drm_device *dev);
1509 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1510 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1511 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1512 struct drm_pending_vblank_event *event);
1513 int nouveau_finish_page_flip(struct nouveau_channel *,
1514 struct nouveau_page_flip_state *);
1515 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1516 struct drm_mode_create_dumb *args);
1517 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1518 uint32_t handle, uint64_t *offset);
1519 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1520 uint32_t handle);
1521
1522 /* nv10_gpio.c */
1523 int nv10_gpio_init(struct drm_device *dev);
1524 void nv10_gpio_fini(struct drm_device *dev);
1525 int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1526 int nv10_gpio_sense(struct drm_device *dev, int line);
1527 void nv10_gpio_irq_enable(struct drm_device *, int line, bool on);
1528
1529 /* nv50_gpio.c */
1530 int nv50_gpio_init(struct drm_device *dev);
1531 void nv50_gpio_fini(struct drm_device *dev);
1532 int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1533 int nv50_gpio_sense(struct drm_device *dev, int line);
1534 void nv50_gpio_irq_enable(struct drm_device *, int line, bool on);
1535 int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1536 int nvd0_gpio_sense(struct drm_device *dev, int line);
1537
1538 /* nv50_calc.c */
1539 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1540 int *N1, int *M1, int *N2, int *M2, int *P);
1541 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1542 int clk, int *N, int *fN, int *M, int *P);
1543
1544 #ifndef ioread32_native
1545 #ifdef __BIG_ENDIAN
1546 #define ioread16_native ioread16be
1547 #define iowrite16_native iowrite16be
1548 #define ioread32_native ioread32be
1549 #define iowrite32_native iowrite32be
1550 #else /* def __BIG_ENDIAN */
1551 #define ioread16_native ioread16
1552 #define iowrite16_native iowrite16
1553 #define ioread32_native ioread32
1554 #define iowrite32_native iowrite32
1555 #endif /* def __BIG_ENDIAN else */
1556 #endif /* !ioread32_native */
1557
1558 /* channel control reg access */
nvchan_rd32(struct nouveau_channel * chan,unsigned reg)1559 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1560 {
1561 return ioread32_native(chan->user + reg);
1562 }
1563
nvchan_wr32(struct nouveau_channel * chan,unsigned reg,u32 val)1564 static inline void nvchan_wr32(struct nouveau_channel *chan,
1565 unsigned reg, u32 val)
1566 {
1567 iowrite32_native(val, chan->user + reg);
1568 }
1569
1570 /* register access */
nv_rd32(struct drm_device * dev,unsigned reg)1571 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1572 {
1573 struct drm_nouveau_private *dev_priv = dev->dev_private;
1574 return ioread32_native(dev_priv->mmio + reg);
1575 }
1576
nv_wr32(struct drm_device * dev,unsigned reg,u32 val)1577 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1578 {
1579 struct drm_nouveau_private *dev_priv = dev->dev_private;
1580 iowrite32_native(val, dev_priv->mmio + reg);
1581 }
1582
nv_mask(struct drm_device * dev,u32 reg,u32 mask,u32 val)1583 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1584 {
1585 u32 tmp = nv_rd32(dev, reg);
1586 nv_wr32(dev, reg, (tmp & ~mask) | val);
1587 return tmp;
1588 }
1589
nv_rd08(struct drm_device * dev,unsigned reg)1590 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1591 {
1592 struct drm_nouveau_private *dev_priv = dev->dev_private;
1593 return ioread8(dev_priv->mmio + reg);
1594 }
1595
nv_wr08(struct drm_device * dev,unsigned reg,u8 val)1596 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1597 {
1598 struct drm_nouveau_private *dev_priv = dev->dev_private;
1599 iowrite8(val, dev_priv->mmio + reg);
1600 }
1601
1602 #define nv_wait(dev, reg, mask, val) \
1603 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1604 #define nv_wait_ne(dev, reg, mask, val) \
1605 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1606 #define nv_wait_cb(dev, func, data) \
1607 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1608
1609 /* PRAMIN access */
nv_ri32(struct drm_device * dev,unsigned offset)1610 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1611 {
1612 struct drm_nouveau_private *dev_priv = dev->dev_private;
1613 return ioread32_native(dev_priv->ramin + offset);
1614 }
1615
nv_wi32(struct drm_device * dev,unsigned offset,u32 val)1616 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1617 {
1618 struct drm_nouveau_private *dev_priv = dev->dev_private;
1619 iowrite32_native(val, dev_priv->ramin + offset);
1620 }
1621
1622 /* object access */
1623 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1624 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1625
1626 /*
1627 * Logging
1628 * Argument d is (struct drm_device *).
1629 */
1630 #define NV_PRINTK(level, d, fmt, arg...) \
1631 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1632 pci_name(d->pdev), ##arg)
1633 #ifndef NV_DEBUG_NOTRACE
1634 #define NV_DEBUG(d, fmt, arg...) do { \
1635 if (drm_debug & DRM_UT_DRIVER) { \
1636 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1637 __LINE__, ##arg); \
1638 } \
1639 } while (0)
1640 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1641 if (drm_debug & DRM_UT_KMS) { \
1642 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1643 __LINE__, ##arg); \
1644 } \
1645 } while (0)
1646 #else
1647 #define NV_DEBUG(d, fmt, arg...) do { \
1648 if (drm_debug & DRM_UT_DRIVER) \
1649 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1650 } while (0)
1651 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1652 if (drm_debug & DRM_UT_KMS) \
1653 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1654 } while (0)
1655 #endif
1656 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1657 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1658 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1659 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1660 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1661 #define NV_WARNONCE(d, fmt, arg...) do { \
1662 static int _warned = 0; \
1663 if (!_warned) { \
1664 NV_WARN(d, fmt, ##arg); \
1665 _warned = 1; \
1666 } \
1667 } while(0)
1668
1669 /* nouveau_reg_debug bitmask */
1670 enum {
1671 NOUVEAU_REG_DEBUG_MC = 0x1,
1672 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1673 NOUVEAU_REG_DEBUG_FB = 0x4,
1674 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1675 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1676 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1677 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1678 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1679 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1680 NOUVEAU_REG_DEBUG_EVO = 0x200,
1681 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1682 };
1683
1684 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1685 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1686 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1687 } while (0)
1688
1689 static inline bool
nv_two_heads(struct drm_device * dev)1690 nv_two_heads(struct drm_device *dev)
1691 {
1692 struct drm_nouveau_private *dev_priv = dev->dev_private;
1693 const int impl = dev->pci_device & 0x0ff0;
1694
1695 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1696 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1697 return true;
1698
1699 return false;
1700 }
1701
1702 static inline bool
nv_gf4_disp_arch(struct drm_device * dev)1703 nv_gf4_disp_arch(struct drm_device *dev)
1704 {
1705 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1706 }
1707
1708 static inline bool
nv_two_reg_pll(struct drm_device * dev)1709 nv_two_reg_pll(struct drm_device *dev)
1710 {
1711 struct drm_nouveau_private *dev_priv = dev->dev_private;
1712 const int impl = dev->pci_device & 0x0ff0;
1713
1714 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1715 return true;
1716 return false;
1717 }
1718
1719 static inline bool
nv_match_device(struct drm_device * dev,unsigned device,unsigned sub_vendor,unsigned sub_device)1720 nv_match_device(struct drm_device *dev, unsigned device,
1721 unsigned sub_vendor, unsigned sub_device)
1722 {
1723 return dev->pdev->device == device &&
1724 dev->pdev->subsystem_vendor == sub_vendor &&
1725 dev->pdev->subsystem_device == sub_device;
1726 }
1727
1728 static inline void *
nv_engine(struct drm_device * dev,int engine)1729 nv_engine(struct drm_device *dev, int engine)
1730 {
1731 struct drm_nouveau_private *dev_priv = dev->dev_private;
1732 return (void *)dev_priv->eng[engine];
1733 }
1734
1735 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1736 * helpful to determine a number of other hardware features
1737 */
1738 static inline int
nv44_graph_class(struct drm_device * dev)1739 nv44_graph_class(struct drm_device *dev)
1740 {
1741 struct drm_nouveau_private *dev_priv = dev->dev_private;
1742
1743 if ((dev_priv->chipset & 0xf0) == 0x60)
1744 return 1;
1745
1746 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1747 }
1748
1749 /* memory type/access flags, do not match hardware values */
1750 #define NV_MEM_ACCESS_RO 1
1751 #define NV_MEM_ACCESS_WO 2
1752 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1753 #define NV_MEM_ACCESS_SYS 4
1754 #define NV_MEM_ACCESS_VM 8
1755 #define NV_MEM_ACCESS_NOSNOOP 16
1756
1757 #define NV_MEM_TARGET_VRAM 0
1758 #define NV_MEM_TARGET_PCI 1
1759 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1760 #define NV_MEM_TARGET_VM 3
1761 #define NV_MEM_TARGET_GART 4
1762
1763 #define NV_MEM_TYPE_VM 0x7f
1764 #define NV_MEM_COMP_VM 0x03
1765
1766 /* FIFO methods */
1767 #define NV01_SUBCHAN_OBJECT 0x00000000
1768 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
1769 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
1770 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
1771 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
1772 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
1773 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
1774 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
1775 #define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
1776 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
1777 #define NV10_SUBCHAN_REF_CNT 0x00000050
1778 #define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
1779 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
1780 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
1781 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
1782 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
1783 #define NV40_SUBCHAN_YIELD 0x00000080
1784
1785 /* NV_SW object class */
1786 #define NV_SW 0x0000506e
1787 #define NV_SW_DMA_VBLSEM 0x0000018c
1788 #define NV_SW_VBLSEM_OFFSET 0x00000400
1789 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1790 #define NV_SW_VBLSEM_RELEASE 0x00000408
1791 #define NV_SW_PAGE_FLIP 0x00000500
1792
1793 #endif /* __NOUVEAU_DRV_H__ */
1794