1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #ifndef MBOX_H
9 #define MBOX_H
10 
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13 
14 #include "rvu_struct.h"
15 #include "common.h"
16 
17 #define MBOX_SIZE		SZ_64K
18 
19 /* AF/PF: PF initiated, PF/VF VF initiated */
20 #define MBOX_DOWN_RX_START	0
21 #define MBOX_DOWN_RX_SIZE	(46 * SZ_1K)
22 #define MBOX_DOWN_TX_START	(MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
23 #define MBOX_DOWN_TX_SIZE	(16 * SZ_1K)
24 /* AF/PF: AF initiated, PF/VF PF initiated */
25 #define MBOX_UP_RX_START	(MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
26 #define MBOX_UP_RX_SIZE		SZ_1K
27 #define MBOX_UP_TX_START	(MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
28 #define MBOX_UP_TX_SIZE		SZ_1K
29 
30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
31 # error "incorrect mailbox area sizes"
32 #endif
33 
34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
35 
36 #define MBOX_RSP_TIMEOUT	3000 /* Time(ms) to wait for mbox response */
37 
38 #define MBOX_MSG_ALIGN		16  /* Align mbox msg start to 16bytes */
39 
40 /* Mailbox directions */
41 #define MBOX_DIR_AFPF		0  /* AF replies to PF */
42 #define MBOX_DIR_PFAF		1  /* PF sends messages to AF */
43 #define MBOX_DIR_PFVF		2  /* PF replies to VF */
44 #define MBOX_DIR_VFPF		3  /* VF sends messages to PF */
45 #define MBOX_DIR_AFPF_UP	4  /* AF sends messages to PF */
46 #define MBOX_DIR_PFAF_UP	5  /* PF replies to AF */
47 #define MBOX_DIR_PFVF_UP	6  /* PF sends messages to VF */
48 #define MBOX_DIR_VFPF_UP	7  /* VF replies to PF */
49 
50 struct otx2_mbox_dev {
51 	void	    *mbase;   /* This dev's mbox region */
52 	void	    *hwbase;
53 	spinlock_t  mbox_lock;
54 	u16         msg_size; /* Total msg size to be sent */
55 	u16         rsp_size; /* Total rsp size to be sure the reply is ok */
56 	u16         num_msgs; /* No of msgs sent or waiting for response */
57 	u16         msgs_acked; /* No of msgs for which response is received */
58 };
59 
60 struct otx2_mbox {
61 	struct pci_dev *pdev;
62 	void   *hwbase;  /* Mbox region advertised by HW */
63 	void   *reg_base;/* CSR base for this dev */
64 	u64    trigger;  /* Trigger mbox notification */
65 	u16    tr_shift; /* Mbox trigger shift */
66 	u64    rx_start; /* Offset of Rx region in mbox memory */
67 	u64    tx_start; /* Offset of Tx region in mbox memory */
68 	u16    rx_size;  /* Size of Rx region */
69 	u16    tx_size;  /* Size of Tx region */
70 	u16    ndevs;    /* The number of peers */
71 	struct otx2_mbox_dev *dev;
72 };
73 
74 /* Header which precedes all mbox messages */
75 struct mbox_hdr {
76 	u64 msg_size;	/* Total msgs size embedded */
77 	u16  num_msgs;   /* No of msgs embedded */
78 };
79 
80 /* Header which precedes every msg and is also part of it */
81 struct mbox_msghdr {
82 	u16 pcifunc;     /* Who's sending this msg */
83 	u16 id;          /* Mbox message ID */
84 #define OTX2_MBOX_REQ_SIG (0xdead)
85 #define OTX2_MBOX_RSP_SIG (0xbeef)
86 	u16 sig;         /* Signature, for validating corrupted msgs */
87 #define OTX2_MBOX_VERSION (0x000a)
88 	u16 ver;         /* Version of msg's structure for this ID */
89 	u16 next_msgoff; /* Offset of next msg within mailbox region */
90 	int rc;          /* Msg process'ed response code */
91 };
92 
93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 		   struct pci_dev *pdev, void __force *reg_base,
98 		   int direction, int ndevs);
99 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
100 			   struct pci_dev *pdev, void __force *reg_base,
101 			   int direction, int ndevs);
102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
106 					    int size, int size_rsp);
107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
108 				      struct mbox_msghdr *msg);
109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
111 			   u16 pcifunc, u16 id);
112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
113 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
115 						      int devid, int size)
116 {
117 	return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
118 }
119 
120 /* Mailbox message types */
121 #define MBOX_MSG_MASK				0xFFFF
122 #define MBOX_MSG_INVALID			0xFFFE
123 #define MBOX_MSG_MAX				0xFFFF
124 
125 #define MBOX_MESSAGES							\
126 /* Generic mbox IDs (range 0x000 - 0x1FF) */				\
127 M(READY,		0x001, ready, msg_req, ready_msg_rsp)		\
128 M(ATTACH_RESOURCES,	0x002, attach_resources, rsrc_attach, msg_rsp)	\
129 M(DETACH_RESOURCES,	0x003, detach_resources, rsrc_detach, msg_rsp)	\
130 M(FREE_RSRC_CNT,	0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp)	\
131 M(MSIX_OFFSET,		0x005, msix_offset, msg_req, msix_offset_rsp)	\
132 M(VF_FLR,		0x006, vf_flr, msg_req, msg_rsp)		\
133 M(PTP_OP,		0x007, ptp_op, ptp_req, ptp_rsp)		\
134 M(GET_HW_CAP,		0x008, get_hw_cap, msg_req, get_hw_cap_rsp)	\
135 M(LMTST_TBL_SETUP,	0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req,    \
136 				msg_rsp)				\
137 M(SET_VF_PERM,		0x00b, set_vf_perm, set_vf_perm, msg_rsp)	\
138 /* CGX mbox IDs (range 0x200 - 0x3FF) */				\
139 M(CGX_START_RXTX,	0x200, cgx_start_rxtx, msg_req, msg_rsp)	\
140 M(CGX_STOP_RXTX,	0x201, cgx_stop_rxtx, msg_req, msg_rsp)		\
141 M(CGX_STATS,		0x202, cgx_stats, msg_req, cgx_stats_rsp)	\
142 M(CGX_MAC_ADDR_SET,	0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,    \
143 				cgx_mac_addr_set_or_get)		\
144 M(CGX_MAC_ADDR_GET,	0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,    \
145 				cgx_mac_addr_set_or_get)		\
146 M(CGX_PROMISC_ENABLE,	0x205, cgx_promisc_enable, msg_req, msg_rsp)	\
147 M(CGX_PROMISC_DISABLE,	0x206, cgx_promisc_disable, msg_req, msg_rsp)	\
148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp)	\
149 M(CGX_STOP_LINKEVENTS,	0x208, cgx_stop_linkevents, msg_req, msg_rsp)	\
150 M(CGX_GET_LINKINFO,	0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
151 M(CGX_INTLBK_ENABLE,	0x20A, cgx_intlbk_enable, msg_req, msg_rsp)	\
152 M(CGX_INTLBK_DISABLE,	0x20B, cgx_intlbk_disable, msg_req, msg_rsp)	\
153 M(CGX_PTP_RX_ENABLE,	0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp)	\
154 M(CGX_PTP_RX_DISABLE,	0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp)	\
155 M(CGX_CFG_PAUSE_FRM,	0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg,	\
156 			       cgx_pause_frm_cfg)			\
157 M(CGX_FW_DATA_GET,	0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
158 M(CGX_FEC_SET,		0x210, cgx_set_fec_param, fec_mode, fec_mode) \
159 M(CGX_MAC_ADDR_ADD,	0x211, cgx_mac_addr_add, cgx_mac_addr_add_req,    \
160 				cgx_mac_addr_add_rsp)		\
161 M(CGX_MAC_ADDR_DEL,	0x212, cgx_mac_addr_del, cgx_mac_addr_del_req,    \
162 			       msg_rsp)		\
163 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req,    \
164 				  cgx_max_dmac_entries_get_rsp)		\
165 M(CGX_FEC_STATS,	0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
166 M(CGX_SET_LINK_MODE,	0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
167 			       cgx_set_link_mode_rsp)	\
168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
169 M(CGX_FEATURES_GET,	0x21B, cgx_features_get, msg_req,		\
170 			       cgx_features_info_msg)			\
171 M(RPM_STATS,		0x21C, rpm_stats, msg_req, rpm_stats_rsp)	\
172 M(CGX_MAC_ADDR_RESET,	0x21D, cgx_mac_addr_reset, msg_req, msg_rsp)	\
173 M(CGX_MAC_ADDR_UPDATE,	0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
174 			       msg_rsp)					\
175 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg,  \
176 				 cgx_pfc_rsp)                               \
177 /* NPA mbox IDs (range 0x400 - 0x5FF) */				\
178 M(NPA_LF_ALLOC,		0x400, npa_lf_alloc,				\
179 				npa_lf_alloc_req, npa_lf_alloc_rsp)	\
180 M(NPA_LF_FREE,		0x401, npa_lf_free, msg_req, msg_rsp)		\
181 M(NPA_AQ_ENQ,		0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)   \
182 M(NPA_HWCTX_DISABLE,	0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
183 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */				\
184 /* TIM mbox IDs (range 0x800 - 0x9FF) */				\
185 /* CPT mbox IDs (range 0xA00 - 0xBFF) */				\
186 M(CPT_LF_ALLOC,		0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg,	\
187 			       msg_rsp)					\
188 M(CPT_LF_FREE,		0xA01, cpt_lf_free, msg_req, msg_rsp)		\
189 M(CPT_RD_WR_REGISTER,	0xA02, cpt_rd_wr_register,  cpt_rd_wr_reg_msg,	\
190 			       cpt_rd_wr_reg_msg)			\
191 M(CPT_INLINE_IPSEC_CFG,	0xA04, cpt_inline_ipsec_cfg,			\
192 			       cpt_inline_ipsec_cfg_msg, msg_rsp)	\
193 M(CPT_STATS,            0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp)	\
194 M(CPT_RXC_TIME_CFG,     0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req,  \
195 			       msg_rsp)                                 \
196 M(CPT_CTX_CACHE_SYNC,   0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp)    \
197 /* SDP mbox IDs (range 0x1000 - 0x11FF) */				\
198 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
199 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
200 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\
201 M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
202 				npc_mcam_alloc_entry_rsp)		\
203 M(NPC_MCAM_FREE_ENTRY,	0x6001, npc_mcam_free_entry,			\
204 				 npc_mcam_free_entry_req, msg_rsp)	\
205 M(NPC_MCAM_WRITE_ENTRY,	0x6002, npc_mcam_write_entry,			\
206 				 npc_mcam_write_entry_req, msg_rsp)	\
207 M(NPC_MCAM_ENA_ENTRY,   0x6003, npc_mcam_ena_entry,			\
208 				 npc_mcam_ena_dis_entry_req, msg_rsp)	\
209 M(NPC_MCAM_DIS_ENTRY,   0x6004, npc_mcam_dis_entry,			\
210 				 npc_mcam_ena_dis_entry_req, msg_rsp)	\
211 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
212 				npc_mcam_shift_entry_rsp)		\
213 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter,		\
214 					npc_mcam_alloc_counter_req,	\
215 					npc_mcam_alloc_counter_rsp)	\
216 M(NPC_MCAM_FREE_COUNTER,  0x6007, npc_mcam_free_counter,		\
217 				    npc_mcam_oper_counter_req, msg_rsp)	\
218 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter,		\
219 				   npc_mcam_unmap_counter_req, msg_rsp)	\
220 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter,		\
221 				   npc_mcam_oper_counter_req, msg_rsp)	\
222 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats,		\
223 				   npc_mcam_oper_counter_req,		\
224 				   npc_mcam_oper_counter_rsp)		\
225 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,      \
226 					  npc_mcam_alloc_and_write_entry_req,  \
227 					  npc_mcam_alloc_and_write_entry_rsp)  \
228 M(NPC_GET_KEX_CFG,	  0x600c, npc_get_kex_cfg,			\
229 				   msg_req, npc_get_kex_cfg_rsp)	\
230 M(NPC_INSTALL_FLOW,	  0x600d, npc_install_flow,			       \
231 				  npc_install_flow_req, npc_install_flow_rsp)  \
232 M(NPC_DELETE_FLOW,	  0x600e, npc_delete_flow,			\
233 				  npc_delete_flow_req, msg_rsp)		\
234 M(NPC_MCAM_READ_ENTRY,	  0x600f, npc_mcam_read_entry,			\
235 				  npc_mcam_read_entry_req,		\
236 				  npc_mcam_read_entry_rsp)		\
237 M(NPC_SET_PKIND,        0x6010,   npc_set_pkind,                        \
238 				  npc_set_pkind, msg_rsp)               \
239 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule,            \
240 				   msg_req, npc_mcam_read_base_rule_rsp)  \
241 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats,                     \
242 				   npc_mcam_get_stats_req,              \
243 				   npc_mcam_get_stats_rsp)              \
244 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */				\
245 M(NIX_LF_ALLOC,		0x8000, nix_lf_alloc,				\
246 				 nix_lf_alloc_req, nix_lf_alloc_rsp)	\
247 M(NIX_LF_FREE,		0x8001, nix_lf_free, nix_lf_free_req, msg_rsp)	\
248 M(NIX_AQ_ENQ,		0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp)  \
249 M(NIX_HWCTX_DISABLE,	0x8003, nix_hwctx_disable,			\
250 				 hwctx_disable_req, msg_rsp)		\
251 M(NIX_TXSCH_ALLOC,	0x8004, nix_txsch_alloc,			\
252 				 nix_txsch_alloc_req, nix_txsch_alloc_rsp)   \
253 M(NIX_TXSCH_FREE,	0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
254 M(NIX_TXSCHQ_CFG,	0x8006, nix_txschq_cfg, nix_txschq_config,	\
255 				nix_txschq_config)			\
256 M(NIX_STATS_RST,	0x8007, nix_stats_rst, msg_req, msg_rsp)	\
257 M(NIX_VTAG_CFG,		0x8008, nix_vtag_cfg, nix_vtag_config,		\
258 				 nix_vtag_config_rsp)			\
259 M(NIX_RSS_FLOWKEY_CFG,  0x8009, nix_rss_flowkey_cfg,			\
260 				 nix_rss_flowkey_cfg,			\
261 				 nix_rss_flowkey_cfg_rsp)		\
262 M(NIX_SET_MAC_ADDR,	0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
263 M(NIX_SET_RX_MODE,	0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp)	\
264 M(NIX_SET_HW_FRS,	0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp)	\
265 M(NIX_LF_START_RX,	0x800d, nix_lf_start_rx, msg_req, msg_rsp)	\
266 M(NIX_LF_STOP_RX,	0x800e, nix_lf_stop_rx, msg_req, msg_rsp)	\
267 M(NIX_MARK_FORMAT_CFG,	0x800f, nix_mark_format_cfg,			\
268 				 nix_mark_format_cfg,			\
269 				 nix_mark_format_cfg_rsp)		\
270 M(NIX_SET_RX_CFG,	0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp)	\
271 M(NIX_LSO_FORMAT_CFG,	0x8011, nix_lso_format_cfg,			\
272 				 nix_lso_format_cfg,			\
273 				 nix_lso_format_cfg_rsp)		\
274 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp)	\
275 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
276 M(NIX_BP_ENABLE,	0x8016, nix_bp_enable, nix_bp_cfg_req,	\
277 				nix_bp_cfg_rsp)	\
278 M(NIX_BP_DISABLE,	0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
279 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
280 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg,			\
281 				nix_inline_ipsec_cfg, msg_rsp)		\
282 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg,		\
283 				nix_inline_ipsec_lf_cfg, msg_rsp)	\
284 M(NIX_CN10K_AQ_ENQ,	0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
285 				nix_cn10k_aq_enq_rsp)			\
286 M(NIX_GET_HW_INFO,	0x801c, nix_get_hw_info, msg_req, nix_hw_info)	\
287 M(NIX_BANDPROF_ALLOC,	0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
288 				nix_bandprof_alloc_rsp)			    \
289 M(NIX_BANDPROF_FREE,	0x801e, nix_bandprof_free, nix_bandprof_free_req,   \
290 				msg_rsp)				    \
291 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req,		\
292 				nix_bandprof_get_hwinfo_rsp)
293 
294 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
295 #define MBOX_UP_CGX_MESSAGES						\
296 M(CGX_LINK_EVENT,	0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
297 
298 #define MBOX_UP_CPT_MESSAGES						\
299 M(CPT_INST_LMTST,	0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
300 
301 enum {
302 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
303 MBOX_MESSAGES
304 MBOX_UP_CGX_MESSAGES
305 MBOX_UP_CPT_MESSAGES
306 #undef M
307 };
308 
309 /* Mailbox message formats */
310 
311 #define RVU_DEFAULT_PF_FUNC     0xFFFF
312 
313 /* Generic request msg used for those mbox messages which
314  * don't send any data in the request.
315  */
316 struct msg_req {
317 	struct mbox_msghdr hdr;
318 };
319 
320 /* Generic response msg used an ack or response for those mbox
321  * messages which don't have a specific rsp msg format.
322  */
323 struct msg_rsp {
324 	struct mbox_msghdr hdr;
325 };
326 
327 /* RVU mailbox error codes
328  * Range 256 - 300.
329  */
330 enum rvu_af_status {
331 	RVU_INVALID_VF_ID           = -256,
332 };
333 
334 struct ready_msg_rsp {
335 	struct mbox_msghdr hdr;
336 	u16    sclk_freq;	/* SCLK frequency (in MHz) */
337 	u16    rclk_freq;	/* RCLK frequency (in MHz) */
338 };
339 
340 /* Structure for requesting resource provisioning.
341  * 'modify' flag to be used when either requesting more
342  * or to detach partial of a certain resource type.
343  * Rest of the fields specify how many of what type to
344  * be attached.
345  * To request LFs from two blocks of same type this mailbox
346  * can be sent twice as below:
347  *      struct rsrc_attach *attach;
348  *       .. Allocate memory for message ..
349  *       attach->cptlfs = 3; <3 LFs from CPT0>
350  *       .. Send message ..
351  *       .. Allocate memory for message ..
352  *       attach->modify = 1;
353  *       attach->cpt_blkaddr = BLKADDR_CPT1;
354  *       attach->cptlfs = 2; <2 LFs from CPT1>
355  *       .. Send message ..
356  */
357 struct rsrc_attach {
358 	struct mbox_msghdr hdr;
359 	u8   modify:1;
360 	u8   npalf:1;
361 	u8   nixlf:1;
362 	u16  sso;
363 	u16  ssow;
364 	u16  timlfs;
365 	u16  cptlfs;
366 	int  cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
367 };
368 
369 /* Structure for relinquishing resources.
370  * 'partial' flag to be used when relinquishing all resources
371  * but only of a certain type. If not set, all resources of all
372  * types provisioned to the RVU function will be detached.
373  */
374 struct rsrc_detach {
375 	struct mbox_msghdr hdr;
376 	u8 partial:1;
377 	u8 npalf:1;
378 	u8 nixlf:1;
379 	u8 sso:1;
380 	u8 ssow:1;
381 	u8 timlfs:1;
382 	u8 cptlfs:1;
383 };
384 
385 /* Number of resources available to the caller.
386  * In reply to MBOX_MSG_FREE_RSRC_CNT.
387  */
388 struct free_rsrcs_rsp {
389 	struct mbox_msghdr hdr;
390 	u16 schq[NIX_TXSCH_LVL_CNT];
391 	u16  sso;
392 	u16  tim;
393 	u16  ssow;
394 	u16  cpt;
395 	u8   npa;
396 	u8   nix;
397 	u16  schq_nix1[NIX_TXSCH_LVL_CNT];
398 	u8   nix1;
399 	u8   cpt1;
400 	u8   ree0;
401 	u8   ree1;
402 };
403 
404 #define MSIX_VECTOR_INVALID	0xFFFF
405 #define MAX_RVU_BLKLF_CNT	256
406 
407 struct msix_offset_rsp {
408 	struct mbox_msghdr hdr;
409 	u16  npa_msixoff;
410 	u16  nix_msixoff;
411 	u16  sso;
412 	u16  ssow;
413 	u16  timlfs;
414 	u16  cptlfs;
415 	u16  sso_msixoff[MAX_RVU_BLKLF_CNT];
416 	u16  ssow_msixoff[MAX_RVU_BLKLF_CNT];
417 	u16  timlf_msixoff[MAX_RVU_BLKLF_CNT];
418 	u16  cptlf_msixoff[MAX_RVU_BLKLF_CNT];
419 	u16  cpt1_lfs;
420 	u16  ree0_lfs;
421 	u16  ree1_lfs;
422 	u16  cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
423 	u16  ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
424 	u16  ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
425 };
426 
427 struct get_hw_cap_rsp {
428 	struct mbox_msghdr hdr;
429 	u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
430 	u8 nix_shaping;		     /* Is shaping and coloring supported */
431 };
432 
433 /* CGX mbox message formats */
434 
435 struct cgx_stats_rsp {
436 	struct mbox_msghdr hdr;
437 #define CGX_RX_STATS_COUNT	9
438 #define CGX_TX_STATS_COUNT	18
439 	u64 rx_stats[CGX_RX_STATS_COUNT];
440 	u64 tx_stats[CGX_TX_STATS_COUNT];
441 };
442 
443 struct cgx_fec_stats_rsp {
444 	struct mbox_msghdr hdr;
445 	u64 fec_corr_blks;
446 	u64 fec_uncorr_blks;
447 };
448 /* Structure for requesting the operation for
449  * setting/getting mac address in the CGX interface
450  */
451 struct cgx_mac_addr_set_or_get {
452 	struct mbox_msghdr hdr;
453 	u8 mac_addr[ETH_ALEN];
454 };
455 
456 /* Structure for requesting the operation to
457  * add DMAC filter entry into CGX interface
458  */
459 struct cgx_mac_addr_add_req {
460 	struct mbox_msghdr hdr;
461 	u8 mac_addr[ETH_ALEN];
462 };
463 
464 /* Structure for response against the operation to
465  * add DMAC filter entry into CGX interface
466  */
467 struct cgx_mac_addr_add_rsp {
468 	struct mbox_msghdr hdr;
469 	u8 index;
470 };
471 
472 /* Structure for requesting the operation to
473  * delete DMAC filter entry from CGX interface
474  */
475 struct cgx_mac_addr_del_req {
476 	struct mbox_msghdr hdr;
477 	u8 index;
478 };
479 
480 /* Structure for response against the operation to
481  * get maximum supported DMAC filter entries
482  */
483 struct cgx_max_dmac_entries_get_rsp {
484 	struct mbox_msghdr hdr;
485 	u8 max_dmac_filters;
486 };
487 
488 struct cgx_link_user_info {
489 	uint64_t link_up:1;
490 	uint64_t full_duplex:1;
491 	uint64_t lmac_type_id:4;
492 	uint64_t speed:20; /* speed in Mbps */
493 	uint64_t an:1;		/* AN supported or not */
494 	uint64_t fec:2;	 /* FEC type if enabled else 0 */
495 #define LMACTYPE_STR_LEN 16
496 	char lmac_type[LMACTYPE_STR_LEN];
497 };
498 
499 struct cgx_link_info_msg {
500 	struct mbox_msghdr hdr;
501 	struct cgx_link_user_info link_info;
502 };
503 
504 struct cgx_pause_frm_cfg {
505 	struct mbox_msghdr hdr;
506 	u8 set;
507 	/* set = 1 if the request is to config pause frames */
508 	/* set = 0 if the request is to fetch pause frames config */
509 	u8 rx_pause;
510 	u8 tx_pause;
511 };
512 
513 enum fec_type {
514 	OTX2_FEC_NONE,
515 	OTX2_FEC_BASER,
516 	OTX2_FEC_RS,
517 	OTX2_FEC_STATS_CNT = 2,
518 	OTX2_FEC_OFF,
519 };
520 
521 struct fec_mode {
522 	struct mbox_msghdr hdr;
523 	int fec;
524 };
525 
526 struct sfp_eeprom_s {
527 #define SFP_EEPROM_SIZE 256
528 	u16 sff_id;
529 	u8 buf[SFP_EEPROM_SIZE];
530 	u64 reserved;
531 };
532 
533 struct phy_s {
534 	struct {
535 		u64 can_change_mod_type:1;
536 		u64 mod_type:1;
537 		u64 has_fec_stats:1;
538 	} misc;
539 	struct fec_stats_s {
540 		u32 rsfec_corr_cws;
541 		u32 rsfec_uncorr_cws;
542 		u32 brfec_corr_blks;
543 		u32 brfec_uncorr_blks;
544 	} fec_stats;
545 };
546 
547 struct cgx_lmac_fwdata_s {
548 	u16 rw_valid;
549 	u64 supported_fec;
550 	u64 supported_an;
551 	u64 supported_link_modes;
552 	/* only applicable if AN is supported */
553 	u64 advertised_fec;
554 	u64 advertised_link_modes;
555 	/* Only applicable if SFP/QSFP slot is present */
556 	struct sfp_eeprom_s sfp_eeprom;
557 	struct phy_s phy;
558 #define LMAC_FWDATA_RESERVED_MEM 1021
559 	u64 reserved[LMAC_FWDATA_RESERVED_MEM];
560 };
561 
562 struct cgx_fw_data {
563 	struct mbox_msghdr hdr;
564 	struct cgx_lmac_fwdata_s fwdata;
565 };
566 
567 struct cgx_set_link_mode_args {
568 	u32 speed;
569 	u8 duplex;
570 	u8 an;
571 	u8 ports;
572 	u64 mode;
573 };
574 
575 struct cgx_set_link_mode_req {
576 #define AUTONEG_UNKNOWN		0xff
577 	struct mbox_msghdr hdr;
578 	struct cgx_set_link_mode_args args;
579 };
580 
581 struct cgx_set_link_mode_rsp {
582 	struct mbox_msghdr hdr;
583 	int status;
584 };
585 
586 struct cgx_mac_addr_update_req {
587 	struct mbox_msghdr hdr;
588 	u8 mac_addr[ETH_ALEN];
589 	u8 index;
590 };
591 
592 #define RVU_LMAC_FEAT_FC		BIT_ULL(0) /* pause frames */
593 #define	RVU_LMAC_FEAT_HIGIG2		BIT_ULL(1)
594 			/* flow control from physical link higig2 messages */
595 #define RVU_LMAC_FEAT_PTP		BIT_ULL(2) /* precison time protocol */
596 #define RVU_LMAC_FEAT_DMACF		BIT_ULL(3) /* DMAC FILTER */
597 #define RVU_MAC_VERSION			BIT_ULL(4)
598 #define RVU_MAC_CGX			BIT_ULL(5)
599 #define RVU_MAC_RPM			BIT_ULL(6)
600 
601 struct cgx_features_info_msg {
602 	struct mbox_msghdr hdr;
603 	u64    lmac_features;
604 };
605 
606 struct rpm_stats_rsp {
607 	struct mbox_msghdr hdr;
608 #define RPM_RX_STATS_COUNT		43
609 #define RPM_TX_STATS_COUNT		34
610 	u64 rx_stats[RPM_RX_STATS_COUNT];
611 	u64 tx_stats[RPM_TX_STATS_COUNT];
612 };
613 
614 struct cgx_pfc_cfg {
615 	struct mbox_msghdr hdr;
616 	u8 rx_pause;
617 	u8 tx_pause;
618 	u16 pfc_en; /*  bitmap indicating pfc enabled traffic classes */
619 };
620 
621 struct cgx_pfc_rsp {
622 	struct mbox_msghdr hdr;
623 	u8 rx_pause;
624 	u8 tx_pause;
625 };
626 
627  /* NPA mbox message formats */
628 
629 struct npc_set_pkind {
630 	struct mbox_msghdr hdr;
631 #define OTX2_PRIV_FLAGS_DEFAULT  BIT_ULL(0)
632 #define OTX2_PRIV_FLAGS_CUSTOM   BIT_ULL(63)
633 	u64 mode;
634 #define PKIND_TX		BIT_ULL(0)
635 #define PKIND_RX		BIT_ULL(1)
636 	u8 dir;
637 	u8 pkind; /* valid only in case custom flag */
638 	u8 var_len_off; /* Offset of custom header length field.
639 			 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
640 			 */
641 	u8 var_len_off_mask; /* Mask for length with in offset */
642 	u8 shift_dir; /* shift direction to get length of the header at var_len_off */
643 };
644 
645 /* NPA mbox message formats */
646 
647 /* NPA mailbox error codes
648  * Range 301 - 400.
649  */
650 enum npa_af_status {
651 	NPA_AF_ERR_PARAM            = -301,
652 	NPA_AF_ERR_AQ_FULL          = -302,
653 	NPA_AF_ERR_AQ_ENQUEUE       = -303,
654 	NPA_AF_ERR_AF_LF_INVALID    = -304,
655 	NPA_AF_ERR_AF_LF_ALLOC      = -305,
656 	NPA_AF_ERR_LF_RESET         = -306,
657 };
658 
659 /* For NPA LF context alloc and init */
660 struct npa_lf_alloc_req {
661 	struct mbox_msghdr hdr;
662 	int node;
663 	int aura_sz;  /* No of auras */
664 	u32 nr_pools; /* No of pools */
665 	u64 way_mask;
666 };
667 
668 struct npa_lf_alloc_rsp {
669 	struct mbox_msghdr hdr;
670 	u32 stack_pg_ptrs;  /* No of ptrs per stack page */
671 	u32 stack_pg_bytes; /* Size of stack page */
672 	u16 qints; /* NPA_AF_CONST::QINTS */
673 	u8 cache_lines; /*BATCH ALLOC DMA */
674 };
675 
676 /* NPA AQ enqueue msg */
677 struct npa_aq_enq_req {
678 	struct mbox_msghdr hdr;
679 	u32 aura_id;
680 	u8 ctype;
681 	u8 op;
682 	union {
683 		/* Valid when op == WRITE/INIT and ctype == AURA.
684 		 * LF fills the pool_id in aura.pool_addr. AF will translate
685 		 * the pool_id to pool context pointer.
686 		 */
687 		struct npa_aura_s aura;
688 		/* Valid when op == WRITE/INIT and ctype == POOL */
689 		struct npa_pool_s pool;
690 	};
691 	/* Mask data when op == WRITE (1=write, 0=don't write) */
692 	union {
693 		/* Valid when op == WRITE and ctype == AURA */
694 		struct npa_aura_s aura_mask;
695 		/* Valid when op == WRITE and ctype == POOL */
696 		struct npa_pool_s pool_mask;
697 	};
698 };
699 
700 struct npa_aq_enq_rsp {
701 	struct mbox_msghdr hdr;
702 	union {
703 		/* Valid when op == READ and ctype == AURA */
704 		struct npa_aura_s aura;
705 		/* Valid when op == READ and ctype == POOL */
706 		struct npa_pool_s pool;
707 	};
708 };
709 
710 /* Disable all contexts of type 'ctype' */
711 struct hwctx_disable_req {
712 	struct mbox_msghdr hdr;
713 	u8 ctype;
714 };
715 
716 /* NIX mbox message formats */
717 
718 /* NIX mailbox error codes
719  * Range 401 - 500.
720  */
721 enum nix_af_status {
722 	NIX_AF_ERR_PARAM            = -401,
723 	NIX_AF_ERR_AQ_FULL          = -402,
724 	NIX_AF_ERR_AQ_ENQUEUE       = -403,
725 	NIX_AF_ERR_AF_LF_INVALID    = -404,
726 	NIX_AF_ERR_AF_LF_ALLOC      = -405,
727 	NIX_AF_ERR_TLX_ALLOC_FAIL   = -406,
728 	NIX_AF_ERR_TLX_INVALID      = -407,
729 	NIX_AF_ERR_RSS_SIZE_INVALID = -408,
730 	NIX_AF_ERR_RSS_GRPS_INVALID = -409,
731 	NIX_AF_ERR_FRS_INVALID      = -410,
732 	NIX_AF_ERR_RX_LINK_INVALID  = -411,
733 	NIX_AF_INVAL_TXSCHQ_CFG     = -412,
734 	NIX_AF_SMQ_FLUSH_FAILED     = -413,
735 	NIX_AF_ERR_LF_RESET         = -414,
736 	NIX_AF_ERR_RSS_NOSPC_FIELD  = -415,
737 	NIX_AF_ERR_RSS_NOSPC_ALGO   = -416,
738 	NIX_AF_ERR_MARK_CFG_FAIL    = -417,
739 	NIX_AF_ERR_LSO_CFG_FAIL     = -418,
740 	NIX_AF_INVAL_NPA_PF_FUNC    = -419,
741 	NIX_AF_INVAL_SSO_PF_FUNC    = -420,
742 	NIX_AF_ERR_TX_VTAG_NOSPC    = -421,
743 	NIX_AF_ERR_RX_VTAG_INUSE    = -422,
744 	NIX_AF_ERR_PTP_CONFIG_FAIL  = -423,
745 	NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
746 	NIX_AF_ERR_INVALID_NIXBLK   = -425,
747 	NIX_AF_ERR_INVALID_BANDPROF = -426,
748 	NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
749 	NIX_AF_ERR_BANDPROF_INVAL_REQ  = -428,
750 	NIX_AF_ERR_CQ_CTX_WRITE_ERR  = -429,
751 	NIX_AF_ERR_AQ_CTX_RETRY_WRITE  = -430,
752 	NIX_AF_ERR_LINK_CREDITS  = -431,
753 };
754 
755 /* For NIX RX vtag action  */
756 enum nix_rx_vtag0_type {
757 	NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
758 	NIX_AF_LFX_RX_VTAG_TYPE1,
759 	NIX_AF_LFX_RX_VTAG_TYPE2,
760 	NIX_AF_LFX_RX_VTAG_TYPE3,
761 	NIX_AF_LFX_RX_VTAG_TYPE4,
762 	NIX_AF_LFX_RX_VTAG_TYPE5,
763 	NIX_AF_LFX_RX_VTAG_TYPE6,
764 	NIX_AF_LFX_RX_VTAG_TYPE7,
765 };
766 
767 /* For NIX LF context alloc and init */
768 struct nix_lf_alloc_req {
769 	struct mbox_msghdr hdr;
770 	int node;
771 	u32 rq_cnt;   /* No of receive queues */
772 	u32 sq_cnt;   /* No of send queues */
773 	u32 cq_cnt;   /* No of completion queues */
774 	u8  xqe_sz;
775 	u16 rss_sz;
776 	u8  rss_grps;
777 	u16 npa_func;
778 	u16 sso_func;
779 	u64 rx_cfg;   /* See NIX_AF_LF(0..127)_RX_CFG */
780 	u64 way_mask;
781 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
782 #define NIX_LF_LBK_BLK_SEL	    BIT_ULL(1)
783 	u64 flags;
784 };
785 
786 struct nix_lf_alloc_rsp {
787 	struct mbox_msghdr hdr;
788 	u16	sqb_size;
789 	u16	rx_chan_base;
790 	u16	tx_chan_base;
791 	u8      rx_chan_cnt; /* total number of RX channels */
792 	u8      tx_chan_cnt; /* total number of TX channels */
793 	u8	lso_tsov4_idx;
794 	u8	lso_tsov6_idx;
795 	u8      mac_addr[ETH_ALEN];
796 	u8	lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
797 	u8	lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
798 	u16	cints; /* NIX_AF_CONST2::CINTS */
799 	u16	qints; /* NIX_AF_CONST2::QINTS */
800 	u8	cgx_links;  /* No. of CGX links present in HW */
801 	u8	lbk_links;  /* No. of LBK links present in HW */
802 	u8	sdp_links;  /* No. of SDP links present in HW */
803 	u8	tx_link;    /* Transmit channel link number */
804 };
805 
806 struct nix_lf_free_req {
807 	struct mbox_msghdr hdr;
808 #define NIX_LF_DISABLE_FLOWS		BIT_ULL(0)
809 #define NIX_LF_DONT_FREE_TX_VTAG	BIT_ULL(1)
810 	u64 flags;
811 };
812 
813 /* CN10K NIX AQ enqueue msg */
814 struct nix_cn10k_aq_enq_req {
815 	struct mbox_msghdr hdr;
816 	u32  qidx;
817 	u8 ctype;
818 	u8 op;
819 	union {
820 		struct nix_cn10k_rq_ctx_s rq;
821 		struct nix_cn10k_sq_ctx_s sq;
822 		struct nix_cq_ctx_s cq;
823 		struct nix_rsse_s   rss;
824 		struct nix_rx_mce_s mce;
825 		struct nix_bandprof_s prof;
826 	};
827 	union {
828 		struct nix_cn10k_rq_ctx_s rq_mask;
829 		struct nix_cn10k_sq_ctx_s sq_mask;
830 		struct nix_cq_ctx_s cq_mask;
831 		struct nix_rsse_s   rss_mask;
832 		struct nix_rx_mce_s mce_mask;
833 		struct nix_bandprof_s prof_mask;
834 	};
835 };
836 
837 struct nix_cn10k_aq_enq_rsp {
838 	struct mbox_msghdr hdr;
839 	union {
840 		struct nix_cn10k_rq_ctx_s rq;
841 		struct nix_cn10k_sq_ctx_s sq;
842 		struct nix_cq_ctx_s cq;
843 		struct nix_rsse_s   rss;
844 		struct nix_rx_mce_s mce;
845 		struct nix_bandprof_s prof;
846 	};
847 };
848 
849 /* NIX AQ enqueue msg */
850 struct nix_aq_enq_req {
851 	struct mbox_msghdr hdr;
852 	u32  qidx;
853 	u8 ctype;
854 	u8 op;
855 	union {
856 		struct nix_rq_ctx_s rq;
857 		struct nix_sq_ctx_s sq;
858 		struct nix_cq_ctx_s cq;
859 		struct nix_rsse_s   rss;
860 		struct nix_rx_mce_s mce;
861 		u64 prof;
862 	};
863 	union {
864 		struct nix_rq_ctx_s rq_mask;
865 		struct nix_sq_ctx_s sq_mask;
866 		struct nix_cq_ctx_s cq_mask;
867 		struct nix_rsse_s   rss_mask;
868 		struct nix_rx_mce_s mce_mask;
869 		u64 prof_mask;
870 	};
871 };
872 
873 struct nix_aq_enq_rsp {
874 	struct mbox_msghdr hdr;
875 	union {
876 		struct nix_rq_ctx_s rq;
877 		struct nix_sq_ctx_s sq;
878 		struct nix_cq_ctx_s cq;
879 		struct nix_rsse_s   rss;
880 		struct nix_rx_mce_s mce;
881 		struct nix_bandprof_s prof;
882 	};
883 };
884 
885 /* Tx scheduler/shaper mailbox messages */
886 
887 #define MAX_TXSCHQ_PER_FUNC		128
888 
889 struct nix_txsch_alloc_req {
890 	struct mbox_msghdr hdr;
891 	/* Scheduler queue count request at each level */
892 	u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
893 	u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
894 };
895 
896 struct nix_txsch_alloc_rsp {
897 	struct mbox_msghdr hdr;
898 	/* Scheduler queue count allocated at each level */
899 	u16 schq_contig[NIX_TXSCH_LVL_CNT];
900 	u16 schq[NIX_TXSCH_LVL_CNT];
901 	/* Scheduler queue list allocated at each level */
902 	u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
903 	u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
904 	u8  aggr_level; /* Traffic aggregation scheduler level */
905 	u8  aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
906 	u8  link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
907 };
908 
909 struct nix_txsch_free_req {
910 	struct mbox_msghdr hdr;
911 #define TXSCHQ_FREE_ALL BIT_ULL(0)
912 	u16 flags;
913 	/* Scheduler queue level to be freed */
914 	u16 schq_lvl;
915 	/* List of scheduler queues to be freed */
916 	u16 schq;
917 };
918 
919 struct nix_txschq_config {
920 	struct mbox_msghdr hdr;
921 	u8 lvl;	/* SMQ/MDQ/TL4/TL3/TL2/TL1 */
922 	u8 read;
923 #define TXSCHQ_IDX_SHIFT	16
924 #define TXSCHQ_IDX_MASK		(BIT_ULL(10) - 1)
925 #define TXSCHQ_IDX(reg, shift)	(((reg) >> (shift)) & TXSCHQ_IDX_MASK)
926 	u8 num_regs;
927 #define MAX_REGS_PER_MBOX_MSG	20
928 	u64 reg[MAX_REGS_PER_MBOX_MSG];
929 	u64 regval[MAX_REGS_PER_MBOX_MSG];
930 	/* All 0's => overwrite with new value */
931 	u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
932 };
933 
934 struct nix_vtag_config {
935 	struct mbox_msghdr hdr;
936 	/* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
937 	u8 vtag_size;
938 	/* cfg_type is '0' for tx vlan cfg
939 	 * cfg_type is '1' for rx vlan cfg
940 	 */
941 	u8 cfg_type;
942 	union {
943 		/* valid when cfg_type is '0' */
944 		struct {
945 			u64 vtag0;
946 			u64 vtag1;
947 
948 			/* cfg_vtag0 & cfg_vtag1 fields are valid
949 			 * when free_vtag0 & free_vtag1 are '0's.
950 			 */
951 			/* cfg_vtag0 = 1 to configure vtag0 */
952 			u8 cfg_vtag0 :1;
953 			/* cfg_vtag1 = 1 to configure vtag1 */
954 			u8 cfg_vtag1 :1;
955 
956 			/* vtag0_idx & vtag1_idx are only valid when
957 			 * both cfg_vtag0 & cfg_vtag1 are '0's,
958 			 * these fields are used along with free_vtag0
959 			 * & free_vtag1 to free the nix lf's tx_vlan
960 			 * configuration.
961 			 *
962 			 * Denotes the indices of tx_vtag def registers
963 			 * that needs to be cleared and freed.
964 			 */
965 			int vtag0_idx;
966 			int vtag1_idx;
967 
968 			/* free_vtag0 & free_vtag1 fields are valid
969 			 * when cfg_vtag0 & cfg_vtag1 are '0's.
970 			 */
971 			/* free_vtag0 = 1 clears vtag0 configuration
972 			 * vtag0_idx denotes the index to be cleared.
973 			 */
974 			u8 free_vtag0 :1;
975 			/* free_vtag1 = 1 clears vtag1 configuration
976 			 * vtag1_idx denotes the index to be cleared.
977 			 */
978 			u8 free_vtag1 :1;
979 		} tx;
980 
981 		/* valid when cfg_type is '1' */
982 		struct {
983 			/* rx vtag type index, valid values are in 0..7 range */
984 			u8 vtag_type;
985 			/* rx vtag strip */
986 			u8 strip_vtag :1;
987 			/* rx vtag capture */
988 			u8 capture_vtag :1;
989 		} rx;
990 	};
991 };
992 
993 struct nix_vtag_config_rsp {
994 	struct mbox_msghdr hdr;
995 	int vtag0_idx;
996 	int vtag1_idx;
997 	/* Indices of tx_vtag def registers used to configure
998 	 * tx vtag0 & vtag1 headers, these indices are valid
999 	 * when nix_vtag_config mbox requested for vtag0 and/
1000 	 * or vtag1 configuration.
1001 	 */
1002 };
1003 
1004 struct nix_rss_flowkey_cfg {
1005 	struct mbox_msghdr hdr;
1006 	int	mcam_index;  /* MCAM entry index to modify */
1007 #define NIX_FLOW_KEY_TYPE_PORT	BIT(0)
1008 #define NIX_FLOW_KEY_TYPE_IPV4	BIT(1)
1009 #define NIX_FLOW_KEY_TYPE_IPV6	BIT(2)
1010 #define NIX_FLOW_KEY_TYPE_TCP	BIT(3)
1011 #define NIX_FLOW_KEY_TYPE_UDP	BIT(4)
1012 #define NIX_FLOW_KEY_TYPE_SCTP	BIT(5)
1013 #define NIX_FLOW_KEY_TYPE_NVGRE    BIT(6)
1014 #define NIX_FLOW_KEY_TYPE_VXLAN    BIT(7)
1015 #define NIX_FLOW_KEY_TYPE_GENEVE   BIT(8)
1016 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1017 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1018 #define NIX_FLOW_KEY_TYPE_GTPU       BIT(11)
1019 #define NIX_FLOW_KEY_TYPE_INNR_IPV4     BIT(12)
1020 #define NIX_FLOW_KEY_TYPE_INNR_IPV6     BIT(13)
1021 #define NIX_FLOW_KEY_TYPE_INNR_TCP      BIT(14)
1022 #define NIX_FLOW_KEY_TYPE_INNR_UDP      BIT(15)
1023 #define NIX_FLOW_KEY_TYPE_INNR_SCTP     BIT(16)
1024 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1025 #define NIX_FLOW_KEY_TYPE_VLAN		BIT(20)
1026 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO	BIT(21)
1027 #define NIX_FLOW_KEY_TYPE_AH		BIT(22)
1028 #define NIX_FLOW_KEY_TYPE_ESP		BIT(23)
1029 	u32	flowkey_cfg; /* Flowkey types selected */
1030 	u8	group;       /* RSS context or group */
1031 };
1032 
1033 struct nix_rss_flowkey_cfg_rsp {
1034 	struct mbox_msghdr hdr;
1035 	u8	alg_idx; /* Selected algo index */
1036 };
1037 
1038 struct nix_set_mac_addr {
1039 	struct mbox_msghdr hdr;
1040 	u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1041 };
1042 
1043 struct nix_get_mac_addr_rsp {
1044 	struct mbox_msghdr hdr;
1045 	u8 mac_addr[ETH_ALEN];
1046 };
1047 
1048 struct nix_mark_format_cfg {
1049 	struct mbox_msghdr hdr;
1050 	u8 offset;
1051 	u8 y_mask;
1052 	u8 y_val;
1053 	u8 r_mask;
1054 	u8 r_val;
1055 };
1056 
1057 struct nix_mark_format_cfg_rsp {
1058 	struct mbox_msghdr hdr;
1059 	u8 mark_format_idx;
1060 };
1061 
1062 struct nix_rx_mode {
1063 	struct mbox_msghdr hdr;
1064 #define NIX_RX_MODE_UCAST	BIT(0)
1065 #define NIX_RX_MODE_PROMISC	BIT(1)
1066 #define NIX_RX_MODE_ALLMULTI	BIT(2)
1067 #define NIX_RX_MODE_USE_MCE	BIT(3)
1068 	u16	mode;
1069 };
1070 
1071 struct nix_rx_cfg {
1072 	struct mbox_msghdr hdr;
1073 #define NIX_RX_OL3_VERIFY   BIT(0)
1074 #define NIX_RX_OL4_VERIFY   BIT(1)
1075 	u8 len_verify; /* Outer L3/L4 len check */
1076 #define NIX_RX_CSUM_OL4_VERIFY  BIT(0)
1077 	u8 csum_verify; /* Outer L4 checksum verification */
1078 };
1079 
1080 struct nix_frs_cfg {
1081 	struct mbox_msghdr hdr;
1082 	u8	update_smq;    /* Update SMQ's min/max lens */
1083 	u8	update_minlen; /* Set minlen also */
1084 	u8	sdp_link;      /* Set SDP RX link */
1085 	u16	maxlen;
1086 	u16	minlen;
1087 };
1088 
1089 struct nix_lso_format_cfg {
1090 	struct mbox_msghdr hdr;
1091 	u64 field_mask;
1092 #define NIX_LSO_FIELD_MAX	8
1093 	u64 fields[NIX_LSO_FIELD_MAX];
1094 };
1095 
1096 struct nix_lso_format_cfg_rsp {
1097 	struct mbox_msghdr hdr;
1098 	u8 lso_format_idx;
1099 };
1100 
1101 struct nix_bp_cfg_req {
1102 	struct mbox_msghdr hdr;
1103 	u16	chan_base; /* Starting channel number */
1104 	u8	chan_cnt; /* Number of channels */
1105 	u8	bpid_per_chan;
1106 	/* bpid_per_chan = 0 assigns single bp id for range of channels */
1107 	/* bpid_per_chan = 1 assigns separate bp id for each channel */
1108 };
1109 
1110 /* PF can be mapped to either CGX or LBK interface,
1111  * so maximum 64 channels are possible.
1112  */
1113 #define NIX_MAX_BPID_CHAN	64
1114 struct nix_bp_cfg_rsp {
1115 	struct mbox_msghdr hdr;
1116 	u16	chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1117 	u8	chan_cnt; /* Number of channel for which bpids are assigned */
1118 };
1119 
1120 /* Global NIX inline IPSec configuration */
1121 struct nix_inline_ipsec_cfg {
1122 	struct mbox_msghdr hdr;
1123 	u32 cpt_credit;
1124 	struct {
1125 		u8 egrp;
1126 		u8 opcode;
1127 		u16 param1;
1128 		u16 param2;
1129 	} gen_cfg;
1130 	struct {
1131 		u16 cpt_pf_func;
1132 		u8 cpt_slot;
1133 	} inst_qsel;
1134 	u8 enable;
1135 };
1136 
1137 /* Per NIX LF inline IPSec configuration */
1138 struct nix_inline_ipsec_lf_cfg {
1139 	struct mbox_msghdr hdr;
1140 	u64 sa_base_addr;
1141 	struct {
1142 		u32 tag_const;
1143 		u16 lenm1_max;
1144 		u8 sa_pow2_size;
1145 		u8 tt;
1146 	} ipsec_cfg0;
1147 	struct {
1148 		u32 sa_idx_max;
1149 		u8 sa_idx_w;
1150 	} ipsec_cfg1;
1151 	u8 enable;
1152 };
1153 
1154 struct nix_hw_info {
1155 	struct mbox_msghdr hdr;
1156 	u16 rsvs16;
1157 	u16 max_mtu;
1158 	u16 min_mtu;
1159 	u32 rpm_dwrr_mtu;
1160 	u32 sdp_dwrr_mtu;
1161 	u64 rsvd[16]; /* Add reserved fields for future expansion */
1162 };
1163 
1164 struct nix_bandprof_alloc_req {
1165 	struct mbox_msghdr hdr;
1166 	/* Count of profiles needed per layer */
1167 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1168 };
1169 
1170 struct nix_bandprof_alloc_rsp {
1171 	struct mbox_msghdr hdr;
1172 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1173 
1174 	/* There is no need to allocate morethan 1 bandwidth profile
1175 	 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1176 	 * profiles to 64 per PF_FUNC.
1177 	 */
1178 #define MAX_BANDPROF_PER_PFFUNC	64
1179 	u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1180 };
1181 
1182 struct nix_bandprof_free_req {
1183 	struct mbox_msghdr hdr;
1184 	u8 free_all;
1185 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1186 	u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1187 };
1188 
1189 struct nix_bandprof_get_hwinfo_rsp {
1190 	struct mbox_msghdr hdr;
1191 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1192 	u32 policer_timeunit;
1193 };
1194 
1195 /* NPC mbox message structs */
1196 
1197 #define NPC_MCAM_ENTRY_INVALID	0xFFFF
1198 #define NPC_MCAM_INVALID_MAP	0xFFFF
1199 
1200 /* NPC mailbox error codes
1201  * Range 701 - 800.
1202  */
1203 enum npc_af_status {
1204 	NPC_MCAM_INVALID_REQ	= -701,
1205 	NPC_MCAM_ALLOC_DENIED	= -702,
1206 	NPC_MCAM_ALLOC_FAILED	= -703,
1207 	NPC_MCAM_PERM_DENIED	= -704,
1208 	NPC_FLOW_INTF_INVALID	= -707,
1209 	NPC_FLOW_CHAN_INVALID	= -708,
1210 	NPC_FLOW_NO_NIXLF	= -709,
1211 	NPC_FLOW_NOT_SUPPORTED	= -710,
1212 	NPC_FLOW_VF_PERM_DENIED	= -711,
1213 	NPC_FLOW_VF_NOT_INIT	= -712,
1214 	NPC_FLOW_VF_OVERLAP	= -713,
1215 };
1216 
1217 struct npc_mcam_alloc_entry_req {
1218 	struct mbox_msghdr hdr;
1219 #define NPC_MAX_NONCONTIG_ENTRIES	256
1220 	u8  contig;   /* Contiguous entries ? */
1221 #define NPC_MCAM_ANY_PRIO		0
1222 #define NPC_MCAM_LOWER_PRIO		1
1223 #define NPC_MCAM_HIGHER_PRIO		2
1224 	u8  priority; /* Lower or higher w.r.t ref_entry */
1225 	u16 ref_entry;
1226 	u16 count;    /* Number of entries requested */
1227 };
1228 
1229 struct npc_mcam_alloc_entry_rsp {
1230 	struct mbox_msghdr hdr;
1231 	u16 entry; /* Entry allocated or start index if contiguous.
1232 		    * Invalid incase of non-contiguous.
1233 		    */
1234 	u16 count; /* Number of entries allocated */
1235 	u16 free_count; /* Number of entries available */
1236 	u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1237 };
1238 
1239 struct npc_mcam_free_entry_req {
1240 	struct mbox_msghdr hdr;
1241 	u16 entry; /* Entry index to be freed */
1242 	u8  all;   /* If all entries allocated to this PFVF to be freed */
1243 };
1244 
1245 struct mcam_entry {
1246 #define NPC_MAX_KWS_IN_KEY	7 /* Number of keywords in max keywidth */
1247 	u64	kw[NPC_MAX_KWS_IN_KEY];
1248 	u64	kw_mask[NPC_MAX_KWS_IN_KEY];
1249 	u64	action;
1250 	u64	vtag_action;
1251 };
1252 
1253 struct npc_mcam_write_entry_req {
1254 	struct mbox_msghdr hdr;
1255 	struct mcam_entry entry_data;
1256 	u16 entry;	 /* MCAM entry to write this match key */
1257 	u16 cntr;	 /* Counter for this MCAM entry */
1258 	u8  intf;	 /* Rx or Tx interface */
1259 	u8  enable_entry;/* Enable this MCAM entry ? */
1260 	u8  set_cntr;    /* Set counter for this entry ? */
1261 };
1262 
1263 /* Enable/Disable a given entry */
1264 struct npc_mcam_ena_dis_entry_req {
1265 	struct mbox_msghdr hdr;
1266 	u16 entry;
1267 };
1268 
1269 struct npc_mcam_shift_entry_req {
1270 	struct mbox_msghdr hdr;
1271 #define NPC_MCAM_MAX_SHIFTS	64
1272 	u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1273 	u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1274 	u16 shift_count; /* Number of entries to shift */
1275 };
1276 
1277 struct npc_mcam_shift_entry_rsp {
1278 	struct mbox_msghdr hdr;
1279 	u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1280 };
1281 
1282 struct npc_mcam_alloc_counter_req {
1283 	struct mbox_msghdr hdr;
1284 	u8  contig;	/* Contiguous counters ? */
1285 #define NPC_MAX_NONCONTIG_COUNTERS       64
1286 	u16 count;	/* Number of counters requested */
1287 };
1288 
1289 struct npc_mcam_alloc_counter_rsp {
1290 	struct mbox_msghdr hdr;
1291 	u16 cntr;   /* Counter allocated or start index if contiguous.
1292 		     * Invalid incase of non-contiguous.
1293 		     */
1294 	u16 count;  /* Number of counters allocated */
1295 	u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1296 };
1297 
1298 struct npc_mcam_oper_counter_req {
1299 	struct mbox_msghdr hdr;
1300 	u16 cntr;   /* Free a counter or clear/fetch it's stats */
1301 };
1302 
1303 struct npc_mcam_oper_counter_rsp {
1304 	struct mbox_msghdr hdr;
1305 	u64 stat;  /* valid only while fetching counter's stats */
1306 };
1307 
1308 struct npc_mcam_unmap_counter_req {
1309 	struct mbox_msghdr hdr;
1310 	u16 cntr;
1311 	u16 entry; /* Entry and counter to be unmapped */
1312 	u8  all;   /* Unmap all entries using this counter ? */
1313 };
1314 
1315 struct npc_mcam_alloc_and_write_entry_req {
1316 	struct mbox_msghdr hdr;
1317 	struct mcam_entry entry_data;
1318 	u16 ref_entry;
1319 	u8  priority;    /* Lower or higher w.r.t ref_entry */
1320 	u8  intf;	 /* Rx or Tx interface */
1321 	u8  enable_entry;/* Enable this MCAM entry ? */
1322 	u8  alloc_cntr;  /* Allocate counter and map ? */
1323 };
1324 
1325 struct npc_mcam_alloc_and_write_entry_rsp {
1326 	struct mbox_msghdr hdr;
1327 	u16 entry;
1328 	u16 cntr;
1329 };
1330 
1331 struct npc_get_kex_cfg_rsp {
1332 	struct mbox_msghdr hdr;
1333 	u64 rx_keyx_cfg;   /* NPC_AF_INTF(0)_KEX_CFG */
1334 	u64 tx_keyx_cfg;   /* NPC_AF_INTF(1)_KEX_CFG */
1335 #define NPC_MAX_INTF	2
1336 #define NPC_MAX_LID	8
1337 #define NPC_MAX_LT	16
1338 #define NPC_MAX_LD	2
1339 #define NPC_MAX_LFL	16
1340 	/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1341 	u64 kex_ld_flags[NPC_MAX_LD];
1342 	/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1343 	u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1344 	/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1345 	u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1346 #define MKEX_NAME_LEN 128
1347 	u8 mkex_pfl_name[MKEX_NAME_LEN];
1348 };
1349 
1350 struct flow_msg {
1351 	unsigned char dmac[6];
1352 	unsigned char smac[6];
1353 	__be16 etype;
1354 	__be16 vlan_etype;
1355 	__be16 vlan_tci;
1356 	union {
1357 		__be32 ip4src;
1358 		__be32 ip6src[4];
1359 	};
1360 	union {
1361 		__be32 ip4dst;
1362 		__be32 ip6dst[4];
1363 	};
1364 	u8 tos;
1365 	u8 ip_ver;
1366 	u8 ip_proto;
1367 	u8 tc;
1368 	__be16 sport;
1369 	__be16 dport;
1370 };
1371 
1372 struct npc_install_flow_req {
1373 	struct mbox_msghdr hdr;
1374 	struct flow_msg packet;
1375 	struct flow_msg mask;
1376 	u64 features;
1377 	u16 entry;
1378 	u16 channel;
1379 	u16 chan_mask;
1380 	u8 intf;
1381 	u8 set_cntr; /* If counter is available set counter for this entry ? */
1382 	u8 default_rule;
1383 	u8 append; /* overwrite(0) or append(1) flow to default rule? */
1384 	u16 vf;
1385 	/* action */
1386 	u32 index;
1387 	u16 match_id;
1388 	u8 flow_key_alg;
1389 	u8 op;
1390 	/* vtag rx action */
1391 	u8 vtag0_type;
1392 	u8 vtag0_valid;
1393 	u8 vtag1_type;
1394 	u8 vtag1_valid;
1395 	/* vtag tx action */
1396 	u16 vtag0_def;
1397 	u8  vtag0_op;
1398 	u16 vtag1_def;
1399 	u8  vtag1_op;
1400 };
1401 
1402 struct npc_install_flow_rsp {
1403 	struct mbox_msghdr hdr;
1404 	int counter; /* negative if no counter else counter number */
1405 };
1406 
1407 struct npc_delete_flow_req {
1408 	struct mbox_msghdr hdr;
1409 	u16 entry;
1410 	u16 start;/*Disable range of entries */
1411 	u16 end;
1412 	u8 all; /* PF + VFs */
1413 };
1414 
1415 struct npc_mcam_read_entry_req {
1416 	struct mbox_msghdr hdr;
1417 	u16 entry;	 /* MCAM entry to read */
1418 };
1419 
1420 struct npc_mcam_read_entry_rsp {
1421 	struct mbox_msghdr hdr;
1422 	struct mcam_entry entry_data;
1423 	u8 intf;
1424 	u8 enable;
1425 };
1426 
1427 struct npc_mcam_read_base_rule_rsp {
1428 	struct mbox_msghdr hdr;
1429 	struct mcam_entry entry;
1430 };
1431 
1432 struct npc_mcam_get_stats_req {
1433 	struct mbox_msghdr hdr;
1434 	u16 entry; /* mcam entry */
1435 };
1436 
1437 struct npc_mcam_get_stats_rsp {
1438 	struct mbox_msghdr hdr;
1439 	u64 stat;  /* counter stats */
1440 	u8 stat_ena; /* enabled */
1441 };
1442 
1443 enum ptp_op {
1444 	PTP_OP_ADJFINE = 0,
1445 	PTP_OP_GET_CLOCK = 1,
1446 	PTP_OP_GET_TSTMP = 2,
1447 	PTP_OP_SET_THRESH = 3,
1448 };
1449 
1450 struct ptp_req {
1451 	struct mbox_msghdr hdr;
1452 	u8 op;
1453 	s64 scaled_ppm;
1454 	u64 thresh;
1455 };
1456 
1457 struct ptp_rsp {
1458 	struct mbox_msghdr hdr;
1459 	u64 clk;
1460 };
1461 
1462 struct set_vf_perm  {
1463 	struct  mbox_msghdr hdr;
1464 	u16	vf;
1465 #define RESET_VF_PERM		BIT_ULL(0)
1466 #define	VF_TRUSTED		BIT_ULL(1)
1467 	u64	flags;
1468 };
1469 
1470 struct lmtst_tbl_setup_req {
1471 	struct mbox_msghdr hdr;
1472 	u64 dis_sched_early_comp :1;
1473 	u64 sch_ena		 :1;
1474 	u64 dis_line_pref	 :1;
1475 	u64 ssow_pf_func	 :13;
1476 	u16 base_pcifunc;
1477 	u8  use_local_lmt_region;
1478 	u64 lmt_iova;
1479 	u64 rsvd[4];
1480 };
1481 
1482 /* CPT mailbox error codes
1483  * Range 901 - 1000.
1484  */
1485 enum cpt_af_status {
1486 	CPT_AF_ERR_PARAM		= -901,
1487 	CPT_AF_ERR_GRP_INVALID		= -902,
1488 	CPT_AF_ERR_LF_INVALID		= -903,
1489 	CPT_AF_ERR_ACCESS_DENIED	= -904,
1490 	CPT_AF_ERR_SSO_PF_FUNC_INVALID	= -905,
1491 	CPT_AF_ERR_NIX_PF_FUNC_INVALID	= -906,
1492 	CPT_AF_ERR_INLINE_IPSEC_INB_ENA	= -907,
1493 	CPT_AF_ERR_INLINE_IPSEC_OUT_ENA	= -908
1494 };
1495 
1496 /* CPT mbox message formats */
1497 struct cpt_rd_wr_reg_msg {
1498 	struct mbox_msghdr hdr;
1499 	u64 reg_offset;
1500 	u64 *ret_val;
1501 	u64 val;
1502 	u8 is_write;
1503 	int blkaddr;
1504 };
1505 
1506 struct cpt_lf_alloc_req_msg {
1507 	struct mbox_msghdr hdr;
1508 	u16 nix_pf_func;
1509 	u16 sso_pf_func;
1510 	u16 eng_grpmsk;
1511 	int blkaddr;
1512 };
1513 
1514 #define CPT_INLINE_INBOUND      0
1515 #define CPT_INLINE_OUTBOUND     1
1516 
1517 /* Mailbox message request format for CPT IPsec
1518  * inline inbound and outbound configuration.
1519  */
1520 struct cpt_inline_ipsec_cfg_msg {
1521 	struct mbox_msghdr hdr;
1522 	u8 enable;
1523 	u8 slot;
1524 	u8 dir;
1525 	u8 sso_pf_func_ovrd;
1526 	u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1527 	u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1528 };
1529 
1530 /* Mailbox message request and response format for CPT stats. */
1531 struct cpt_sts_req {
1532 	struct mbox_msghdr hdr;
1533 	u8 blkaddr;
1534 };
1535 
1536 struct cpt_sts_rsp {
1537 	struct mbox_msghdr hdr;
1538 	u64 inst_req_pc;
1539 	u64 inst_lat_pc;
1540 	u64 rd_req_pc;
1541 	u64 rd_lat_pc;
1542 	u64 rd_uc_pc;
1543 	u64 active_cycles_pc;
1544 	u64 ctx_mis_pc;
1545 	u64 ctx_hit_pc;
1546 	u64 ctx_aop_pc;
1547 	u64 ctx_aop_lat_pc;
1548 	u64 ctx_ifetch_pc;
1549 	u64 ctx_ifetch_lat_pc;
1550 	u64 ctx_ffetch_pc;
1551 	u64 ctx_ffetch_lat_pc;
1552 	u64 ctx_wback_pc;
1553 	u64 ctx_wback_lat_pc;
1554 	u64 ctx_psh_pc;
1555 	u64 ctx_psh_lat_pc;
1556 	u64 ctx_err;
1557 	u64 ctx_enc_id;
1558 	u64 ctx_flush_timer;
1559 	u64 rxc_time;
1560 	u64 rxc_time_cfg;
1561 	u64 rxc_active_sts;
1562 	u64 rxc_zombie_sts;
1563 	u64 busy_sts_ae;
1564 	u64 free_sts_ae;
1565 	u64 busy_sts_se;
1566 	u64 free_sts_se;
1567 	u64 busy_sts_ie;
1568 	u64 free_sts_ie;
1569 	u64 exe_err_info;
1570 	u64 cptclk_cnt;
1571 	u64 diag;
1572 	u64 rxc_dfrg;
1573 	u64 x2p_link_cfg0;
1574 	u64 x2p_link_cfg1;
1575 };
1576 
1577 /* Mailbox message request format to configure reassembly timeout. */
1578 struct cpt_rxc_time_cfg_req {
1579 	struct mbox_msghdr hdr;
1580 	int blkaddr;
1581 	u32 step;
1582 	u16 zombie_thres;
1583 	u16 zombie_limit;
1584 	u16 active_thres;
1585 	u16 active_limit;
1586 };
1587 
1588 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1589 struct cpt_inst_lmtst_req {
1590 	struct mbox_msghdr hdr;
1591 	u64 inst[8];
1592 	u64 rsvd;
1593 };
1594 
1595 struct sdp_node_info {
1596 	/* Node to which this PF belons to */
1597 	u8 node_id;
1598 	u8 max_vfs;
1599 	u8 num_pf_rings;
1600 	u8 pf_srn;
1601 #define SDP_MAX_VFS	128
1602 	u8 vf_rings[SDP_MAX_VFS];
1603 };
1604 
1605 struct sdp_chan_info_msg {
1606 	struct mbox_msghdr hdr;
1607 	struct sdp_node_info info;
1608 };
1609 
1610 struct sdp_get_chan_info_msg {
1611 	struct mbox_msghdr hdr;
1612 	u16 chan_base;
1613 	u16 num_chan;
1614 };
1615 
1616 /* CGX mailbox error codes
1617  * Range 1101 - 1200.
1618  */
1619 enum cgx_af_status {
1620 	LMAC_AF_ERR_INVALID_PARAM	= -1101,
1621 	LMAC_AF_ERR_PF_NOT_MAPPED	= -1102,
1622 	LMAC_AF_ERR_PERM_DENIED		= -1103,
1623 	LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED       = -1104,
1624 	LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1625 };
1626 
1627 #endif /* MBOX_H */
1628