1config ARM 2 bool 3 default y 4 select HAVE_DMA_API_DEBUG 5 select HAVE_IDE if PCI || ISA || PCMCIA 6 select HAVE_MEMBLOCK 7 select RTC_LIB 8 select SYS_SUPPORTS_APM_EMULATION 9 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 10 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 11 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 12 select HAVE_ARCH_KGDB 13 select HAVE_KPROBES if !XIP_KERNEL 14 select HAVE_KRETPROBES if (HAVE_KPROBES) 15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 19 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 20 select HAVE_GENERIC_DMA_COHERENT 21 select HAVE_KERNEL_GZIP 22 select HAVE_KERNEL_LZO 23 select HAVE_KERNEL_LZMA 24 select HAVE_KERNEL_XZ 25 select HAVE_IRQ_WORK 26 select HAVE_PERF_EVENTS 27 select PERF_USE_VMALLOC 28 select HAVE_REGS_AND_STACK_ACCESS_API 29 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 30 select HAVE_C_RECORDMCOUNT 31 select HAVE_GENERIC_HARDIRQS 32 select GENERIC_IRQ_SHOW 33 select CPU_PM if (SUSPEND || CPU_IDLE) 34 select GENERIC_PCI_IOMAP 35 select HAVE_BPF_JIT if NET 36 help 37 The ARM series is a line of low-power-consumption RISC chip designs 38 licensed by ARM Ltd and targeted at embedded applications and 39 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 40 manufactured, but legacy ARM-based PC hardware remains popular in 41 Europe. There is an ARM Linux project with a web page at 42 <http://www.arm.linux.org.uk/>. 43 44config ARM_HAS_SG_CHAIN 45 bool 46 47config HAVE_PWM 48 bool 49 50config MIGHT_HAVE_PCI 51 bool 52 53config SYS_SUPPORTS_APM_EMULATION 54 bool 55 56config GENERIC_GPIO 57 bool 58 59config ARCH_USES_GETTIMEOFFSET 60 bool 61 default n 62 63config GENERIC_CLOCKEVENTS 64 bool 65 66config GENERIC_CLOCKEVENTS_BROADCAST 67 bool 68 depends on GENERIC_CLOCKEVENTS 69 default y if SMP 70 71config KTIME_SCALAR 72 bool 73 default y 74 75config HAVE_TCM 76 bool 77 select GENERIC_ALLOCATOR 78 79config HAVE_PROC_CPU 80 bool 81 82config NO_IOPORT 83 bool 84 85config EISA 86 bool 87 ---help--- 88 The Extended Industry Standard Architecture (EISA) bus was 89 developed as an open alternative to the IBM MicroChannel bus. 90 91 The EISA bus provided some of the features of the IBM MicroChannel 92 bus while maintaining backward compatibility with cards made for 93 the older ISA bus. The EISA bus saw limited use between 1988 and 94 1995 when it was made obsolete by the PCI bus. 95 96 Say Y here if you are building a kernel for an EISA-based machine. 97 98 Otherwise, say N. 99 100config SBUS 101 bool 102 103config MCA 104 bool 105 help 106 MicroChannel Architecture is found in some IBM PS/2 machines and 107 laptops. It is a bus system similar to PCI or ISA. See 108 <file:Documentation/mca.txt> (and especially the web page given 109 there) before attempting to build an MCA bus kernel. 110 111config STACKTRACE_SUPPORT 112 bool 113 default y 114 115config HAVE_LATENCYTOP_SUPPORT 116 bool 117 depends on !SMP 118 default y 119 120config LOCKDEP_SUPPORT 121 bool 122 default y 123 124config TRACE_IRQFLAGS_SUPPORT 125 bool 126 default y 127 128config HARDIRQS_SW_RESEND 129 bool 130 default y 131 132config GENERIC_IRQ_PROBE 133 bool 134 default y 135 136config GENERIC_LOCKBREAK 137 bool 138 default y 139 depends on SMP && PREEMPT 140 141config RWSEM_GENERIC_SPINLOCK 142 bool 143 default y 144 145config RWSEM_XCHGADD_ALGORITHM 146 bool 147 148config ARCH_HAS_ILOG2_U32 149 bool 150 151config ARCH_HAS_ILOG2_U64 152 bool 153 154config ARCH_HAS_CPUFREQ 155 bool 156 help 157 Internal node to signify that the ARCH has CPUFREQ support 158 and that the relevant menu configurations are displayed for 159 it. 160 161config ARCH_HAS_CPU_IDLE_WAIT 162 def_bool y 163 164config GENERIC_HWEIGHT 165 bool 166 default y 167 168config GENERIC_CALIBRATE_DELAY 169 bool 170 default y 171 172config ARCH_MAY_HAVE_PC_FDC 173 bool 174 175config ZONE_DMA 176 bool 177 178config NEED_DMA_MAP_STATE 179 def_bool y 180 181config ARCH_HAS_DMA_SET_COHERENT_MASK 182 bool 183 184config GENERIC_ISA_DMA 185 bool 186 187config FIQ 188 bool 189 190config NEED_RET_TO_USER 191 bool 192 193config ARCH_MTD_XIP 194 bool 195 196config VECTORS_BASE 197 hex 198 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 199 default DRAM_BASE if REMAP_VECTORS_TO_RAM 200 default 0x00000000 201 help 202 The base address of exception vectors. 203 204config ARM_PATCH_PHYS_VIRT 205 bool "Patch physical to virtual translations at runtime" if EMBEDDED 206 default y 207 depends on !XIP_KERNEL && MMU 208 depends on !ARCH_REALVIEW || !SPARSEMEM 209 help 210 Patch phys-to-virt and virt-to-phys translation functions at 211 boot and module load time according to the position of the 212 kernel in system memory. 213 214 This can only be used with non-XIP MMU kernels where the base 215 of physical memory is at a 16MB boundary. 216 217 Only disable this option if you know that you do not require 218 this feature (eg, building a kernel for a single machine) and 219 you need to shrink the kernel to the minimal size. 220 221config NEED_MACH_IO_H 222 bool 223 help 224 Select this when mach/io.h is required to provide special 225 definitions for this platform. The need for mach/io.h should 226 be avoided when possible. 227 228config NEED_MACH_MEMORY_H 229 bool 230 help 231 Select this when mach/memory.h is required to provide special 232 definitions for this platform. The need for mach/memory.h should 233 be avoided when possible. 234 235config PHYS_OFFSET 236 hex "Physical address of main memory" if MMU 237 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 238 default DRAM_BASE if !MMU 239 help 240 Please provide the physical address corresponding to the 241 location of main memory in your system. 242 243config GENERIC_BUG 244 def_bool y 245 depends on BUG 246 247source "init/Kconfig" 248 249source "kernel/Kconfig.freezer" 250 251menu "System Type" 252 253config MMU 254 bool "MMU-based Paged Memory Management Support" 255 default y 256 help 257 Select if you want MMU-based virtualised addressing space 258 support by paged memory management. If unsure, say 'Y'. 259 260# 261# The "ARM system type" choice list is ordered alphabetically by option 262# text. Please add new entries in the option alphabetic order. 263# 264choice 265 prompt "ARM system type" 266 default ARCH_VERSATILE 267 268config ARCH_INTEGRATOR 269 bool "ARM Ltd. Integrator family" 270 select ARM_AMBA 271 select ARCH_HAS_CPUFREQ 272 select CLKDEV_LOOKUP 273 select HAVE_MACH_CLKDEV 274 select HAVE_TCM 275 select ICST 276 select GENERIC_CLOCKEVENTS 277 select PLAT_VERSATILE 278 select PLAT_VERSATILE_FPGA_IRQ 279 select NEED_MACH_IO_H 280 select NEED_MACH_MEMORY_H 281 select SPARSE_IRQ 282 help 283 Support for ARM's Integrator platform. 284 285config ARCH_REALVIEW 286 bool "ARM Ltd. RealView family" 287 select ARM_AMBA 288 select CLKDEV_LOOKUP 289 select HAVE_MACH_CLKDEV 290 select ICST 291 select GENERIC_CLOCKEVENTS 292 select ARCH_WANT_OPTIONAL_GPIOLIB 293 select PLAT_VERSATILE 294 select PLAT_VERSATILE_CLCD 295 select ARM_TIMER_SP804 296 select GPIO_PL061 if GPIOLIB 297 select NEED_MACH_MEMORY_H 298 help 299 This enables support for ARM Ltd RealView boards. 300 301config ARCH_VERSATILE 302 bool "ARM Ltd. Versatile family" 303 select ARM_AMBA 304 select ARM_VIC 305 select CLKDEV_LOOKUP 306 select HAVE_MACH_CLKDEV 307 select ICST 308 select GENERIC_CLOCKEVENTS 309 select ARCH_WANT_OPTIONAL_GPIOLIB 310 select PLAT_VERSATILE 311 select PLAT_VERSATILE_CLCD 312 select PLAT_VERSATILE_FPGA_IRQ 313 select ARM_TIMER_SP804 314 help 315 This enables support for ARM Ltd Versatile board. 316 317config ARCH_VEXPRESS 318 bool "ARM Ltd. Versatile Express family" 319 select ARCH_WANT_OPTIONAL_GPIOLIB 320 select ARM_AMBA 321 select ARM_TIMER_SP804 322 select CLKDEV_LOOKUP 323 select HAVE_MACH_CLKDEV 324 select GENERIC_CLOCKEVENTS 325 select HAVE_CLK 326 select HAVE_PATA_PLATFORM 327 select ICST 328 select NO_IOPORT 329 select PLAT_VERSATILE 330 select PLAT_VERSATILE_CLCD 331 help 332 This enables support for the ARM Ltd Versatile Express boards. 333 334config ARCH_AT91 335 bool "Atmel AT91" 336 select ARCH_REQUIRE_GPIOLIB 337 select HAVE_CLK 338 select CLKDEV_LOOKUP 339 select IRQ_DOMAIN 340 select NEED_MACH_IO_H if PCCARD 341 help 342 This enables support for systems based on the Atmel AT91RM9200, 343 AT91SAM9 processors. 344 345config ARCH_BCMRING 346 bool "Broadcom BCMRING" 347 depends on MMU 348 select CPU_V6 349 select ARM_AMBA 350 select ARM_TIMER_SP804 351 select CLKDEV_LOOKUP 352 select GENERIC_CLOCKEVENTS 353 select ARCH_WANT_OPTIONAL_GPIOLIB 354 help 355 Support for Broadcom's BCMRing platform. 356 357config ARCH_HIGHBANK 358 bool "Calxeda Highbank-based" 359 select ARCH_WANT_OPTIONAL_GPIOLIB 360 select ARM_AMBA 361 select ARM_GIC 362 select ARM_TIMER_SP804 363 select CACHE_L2X0 364 select CLKDEV_LOOKUP 365 select CPU_V7 366 select GENERIC_CLOCKEVENTS 367 select HAVE_ARM_SCU 368 select HAVE_SMP 369 select SPARSE_IRQ 370 select USE_OF 371 help 372 Support for the Calxeda Highbank SoC based boards. 373 374config ARCH_CLPS711X 375 bool "Cirrus Logic CLPS711x/EP721x-based" 376 select CPU_ARM720T 377 select ARCH_USES_GETTIMEOFFSET 378 select NEED_MACH_MEMORY_H 379 help 380 Support for Cirrus Logic 711x/721x based boards. 381 382config ARCH_CNS3XXX 383 bool "Cavium Networks CNS3XXX family" 384 select CPU_V6K 385 select GENERIC_CLOCKEVENTS 386 select ARM_GIC 387 select MIGHT_HAVE_CACHE_L2X0 388 select MIGHT_HAVE_PCI 389 select PCI_DOMAINS if PCI 390 help 391 Support for Cavium Networks CNS3XXX platform. 392 393config ARCH_GEMINI 394 bool "Cortina Systems Gemini" 395 select CPU_FA526 396 select ARCH_REQUIRE_GPIOLIB 397 select ARCH_USES_GETTIMEOFFSET 398 help 399 Support for the Cortina Systems Gemini family SoCs 400 401config ARCH_PRIMA2 402 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 403 select CPU_V7 404 select NO_IOPORT 405 select GENERIC_CLOCKEVENTS 406 select CLKDEV_LOOKUP 407 select GENERIC_IRQ_CHIP 408 select MIGHT_HAVE_CACHE_L2X0 409 select USE_OF 410 select ZONE_DMA 411 help 412 Support for CSR SiRFSoC ARM Cortex A9 Platform 413 414config ARCH_EBSA110 415 bool "EBSA-110" 416 select CPU_SA110 417 select ISA 418 select NO_IOPORT 419 select ARCH_USES_GETTIMEOFFSET 420 select NEED_MACH_IO_H 421 select NEED_MACH_MEMORY_H 422 help 423 This is an evaluation board for the StrongARM processor available 424 from Digital. It has limited hardware on-board, including an 425 Ethernet interface, two PCMCIA sockets, two serial ports and a 426 parallel port. 427 428config ARCH_EP93XX 429 bool "EP93xx-based" 430 select CPU_ARM920T 431 select ARM_AMBA 432 select ARM_VIC 433 select CLKDEV_LOOKUP 434 select ARCH_REQUIRE_GPIOLIB 435 select ARCH_HAS_HOLES_MEMORYMODEL 436 select ARCH_USES_GETTIMEOFFSET 437 select NEED_MACH_MEMORY_H 438 help 439 This enables support for the Cirrus EP93xx series of CPUs. 440 441config ARCH_FOOTBRIDGE 442 bool "FootBridge" 443 select CPU_SA110 444 select FOOTBRIDGE 445 select GENERIC_CLOCKEVENTS 446 select HAVE_IDE 447 select NEED_MACH_IO_H 448 select NEED_MACH_MEMORY_H 449 help 450 Support for systems based on the DC21285 companion chip 451 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 452 453config ARCH_MXC 454 bool "Freescale MXC/iMX-based" 455 select GENERIC_CLOCKEVENTS 456 select ARCH_REQUIRE_GPIOLIB 457 select CLKDEV_LOOKUP 458 select CLKSRC_MMIO 459 select GENERIC_IRQ_CHIP 460 select MULTI_IRQ_HANDLER 461 help 462 Support for Freescale MXC/iMX-based family of processors 463 464config ARCH_MXS 465 bool "Freescale MXS-based" 466 select GENERIC_CLOCKEVENTS 467 select ARCH_REQUIRE_GPIOLIB 468 select CLKDEV_LOOKUP 469 select CLKSRC_MMIO 470 select HAVE_CLK_PREPARE 471 help 472 Support for Freescale MXS-based family of processors 473 474config ARCH_NETX 475 bool "Hilscher NetX based" 476 select CLKSRC_MMIO 477 select CPU_ARM926T 478 select ARM_VIC 479 select GENERIC_CLOCKEVENTS 480 help 481 This enables support for systems based on the Hilscher NetX Soc 482 483config ARCH_H720X 484 bool "Hynix HMS720x-based" 485 select CPU_ARM720T 486 select ISA_DMA_API 487 select ARCH_USES_GETTIMEOFFSET 488 help 489 This enables support for systems based on the Hynix HMS720x 490 491config ARCH_IOP13XX 492 bool "IOP13xx-based" 493 depends on MMU 494 select CPU_XSC3 495 select PLAT_IOP 496 select PCI 497 select ARCH_SUPPORTS_MSI 498 select VMSPLIT_1G 499 select NEED_MACH_IO_H 500 select NEED_MACH_MEMORY_H 501 select NEED_RET_TO_USER 502 help 503 Support for Intel's IOP13XX (XScale) family of processors. 504 505config ARCH_IOP32X 506 bool "IOP32x-based" 507 depends on MMU 508 select CPU_XSCALE 509 select NEED_MACH_IO_H 510 select NEED_RET_TO_USER 511 select PLAT_IOP 512 select PCI 513 select ARCH_REQUIRE_GPIOLIB 514 help 515 Support for Intel's 80219 and IOP32X (XScale) family of 516 processors. 517 518config ARCH_IOP33X 519 bool "IOP33x-based" 520 depends on MMU 521 select CPU_XSCALE 522 select NEED_MACH_IO_H 523 select NEED_RET_TO_USER 524 select PLAT_IOP 525 select PCI 526 select ARCH_REQUIRE_GPIOLIB 527 help 528 Support for Intel's IOP33X (XScale) family of processors. 529 530config ARCH_IXP23XX 531 bool "IXP23XX-based" 532 depends on MMU 533 select CPU_XSC3 534 select PCI 535 select ARCH_USES_GETTIMEOFFSET 536 select NEED_MACH_IO_H 537 select NEED_MACH_MEMORY_H 538 help 539 Support for Intel's IXP23xx (XScale) family of processors. 540 541config ARCH_IXP2000 542 bool "IXP2400/2800-based" 543 depends on MMU 544 select CPU_XSCALE 545 select PCI 546 select ARCH_USES_GETTIMEOFFSET 547 select NEED_MACH_IO_H 548 select NEED_MACH_MEMORY_H 549 help 550 Support for Intel's IXP2400/2800 (XScale) family of processors. 551 552config ARCH_IXP4XX 553 bool "IXP4xx-based" 554 depends on MMU 555 select ARCH_HAS_DMA_SET_COHERENT_MASK 556 select CLKSRC_MMIO 557 select CPU_XSCALE 558 select ARCH_REQUIRE_GPIOLIB 559 select GENERIC_CLOCKEVENTS 560 select MIGHT_HAVE_PCI 561 select NEED_MACH_IO_H 562 select DMABOUNCE if PCI 563 help 564 Support for Intel's IXP4XX (XScale) family of processors. 565 566config ARCH_DOVE 567 bool "Marvell Dove" 568 select CPU_V7 569 select PCI 570 select ARCH_REQUIRE_GPIOLIB 571 select GENERIC_CLOCKEVENTS 572 select NEED_MACH_IO_H 573 select PLAT_ORION 574 help 575 Support for the Marvell Dove SoC 88AP510 576 577config ARCH_KIRKWOOD 578 bool "Marvell Kirkwood" 579 select CPU_FEROCEON 580 select PCI 581 select PCI_QUIRKS 582 select ARCH_REQUIRE_GPIOLIB 583 select GENERIC_CLOCKEVENTS 584 select NEED_MACH_IO_H 585 select PLAT_ORION 586 help 587 Support for the following Marvell Kirkwood series SoCs: 588 88F6180, 88F6192 and 88F6281. 589 590config ARCH_LPC32XX 591 bool "NXP LPC32XX" 592 select CLKSRC_MMIO 593 select CPU_ARM926T 594 select ARCH_REQUIRE_GPIOLIB 595 select HAVE_IDE 596 select ARM_AMBA 597 select USB_ARCH_HAS_OHCI 598 select CLKDEV_LOOKUP 599 select GENERIC_CLOCKEVENTS 600 help 601 Support for the NXP LPC32XX family of processors 602 603config ARCH_MV78XX0 604 bool "Marvell MV78xx0" 605 select CPU_FEROCEON 606 select PCI 607 select ARCH_REQUIRE_GPIOLIB 608 select GENERIC_CLOCKEVENTS 609 select NEED_MACH_IO_H 610 select PLAT_ORION 611 help 612 Support for the following Marvell MV78xx0 series SoCs: 613 MV781x0, MV782x0. 614 615config ARCH_ORION5X 616 bool "Marvell Orion" 617 depends on MMU 618 select CPU_FEROCEON 619 select PCI 620 select ARCH_REQUIRE_GPIOLIB 621 select GENERIC_CLOCKEVENTS 622 select PLAT_ORION 623 help 624 Support for the following Marvell Orion 5x series SoCs: 625 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 626 Orion-2 (5281), Orion-1-90 (6183). 627 628config ARCH_MMP 629 bool "Marvell PXA168/910/MMP2" 630 depends on MMU 631 select ARCH_REQUIRE_GPIOLIB 632 select CLKDEV_LOOKUP 633 select GENERIC_CLOCKEVENTS 634 select GPIO_PXA 635 select TICK_ONESHOT 636 select PLAT_PXA 637 select SPARSE_IRQ 638 select GENERIC_ALLOCATOR 639 help 640 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 641 642config ARCH_KS8695 643 bool "Micrel/Kendin KS8695" 644 select CPU_ARM922T 645 select ARCH_REQUIRE_GPIOLIB 646 select ARCH_USES_GETTIMEOFFSET 647 select NEED_MACH_MEMORY_H 648 help 649 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 650 System-on-Chip devices. 651 652config ARCH_W90X900 653 bool "Nuvoton W90X900 CPU" 654 select CPU_ARM926T 655 select ARCH_REQUIRE_GPIOLIB 656 select CLKDEV_LOOKUP 657 select CLKSRC_MMIO 658 select GENERIC_CLOCKEVENTS 659 help 660 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 661 At present, the w90x900 has been renamed nuc900, regarding 662 the ARM series product line, you can login the following 663 link address to know more. 664 665 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 666 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 667 668config ARCH_TEGRA 669 bool "NVIDIA Tegra" 670 select CLKDEV_LOOKUP 671 select CLKSRC_MMIO 672 select GENERIC_CLOCKEVENTS 673 select GENERIC_GPIO 674 select HAVE_CLK 675 select HAVE_SMP 676 select MIGHT_HAVE_CACHE_L2X0 677 select NEED_MACH_IO_H if PCI 678 select ARCH_HAS_CPUFREQ 679 help 680 This enables support for NVIDIA Tegra based systems (Tegra APX, 681 Tegra 6xx and Tegra 2 series). 682 683config ARCH_PICOXCELL 684 bool "Picochip picoXcell" 685 select ARCH_REQUIRE_GPIOLIB 686 select ARM_PATCH_PHYS_VIRT 687 select ARM_VIC 688 select CPU_V6K 689 select DW_APB_TIMER 690 select GENERIC_CLOCKEVENTS 691 select GENERIC_GPIO 692 select HAVE_TCM 693 select NO_IOPORT 694 select SPARSE_IRQ 695 select USE_OF 696 help 697 This enables support for systems based on the Picochip picoXcell 698 family of Femtocell devices. The picoxcell support requires device tree 699 for all boards. 700 701config ARCH_PNX4008 702 bool "Philips Nexperia PNX4008 Mobile" 703 select CPU_ARM926T 704 select CLKDEV_LOOKUP 705 select ARCH_USES_GETTIMEOFFSET 706 help 707 This enables support for Philips PNX4008 mobile platform. 708 709config ARCH_PXA 710 bool "PXA2xx/PXA3xx-based" 711 depends on MMU 712 select ARCH_MTD_XIP 713 select ARCH_HAS_CPUFREQ 714 select CLKDEV_LOOKUP 715 select CLKSRC_MMIO 716 select ARCH_REQUIRE_GPIOLIB 717 select GENERIC_CLOCKEVENTS 718 select GPIO_PXA 719 select TICK_ONESHOT 720 select PLAT_PXA 721 select SPARSE_IRQ 722 select AUTO_ZRELADDR 723 select MULTI_IRQ_HANDLER 724 select ARM_CPU_SUSPEND if PM 725 select HAVE_IDE 726 help 727 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 728 729config ARCH_MSM 730 bool "Qualcomm MSM" 731 select HAVE_CLK 732 select GENERIC_CLOCKEVENTS 733 select ARCH_REQUIRE_GPIOLIB 734 select CLKDEV_LOOKUP 735 help 736 Support for Qualcomm MSM/QSD based systems. This runs on the 737 apps processor of the MSM/QSD and depends on a shared memory 738 interface to the modem processor which runs the baseband 739 stack and controls some vital subsystems 740 (clock and power control, etc). 741 742config ARCH_SHMOBILE 743 bool "Renesas SH-Mobile / R-Mobile" 744 select HAVE_CLK 745 select CLKDEV_LOOKUP 746 select HAVE_MACH_CLKDEV 747 select HAVE_SMP 748 select GENERIC_CLOCKEVENTS 749 select MIGHT_HAVE_CACHE_L2X0 750 select NO_IOPORT 751 select SPARSE_IRQ 752 select MULTI_IRQ_HANDLER 753 select PM_GENERIC_DOMAINS if PM 754 select NEED_MACH_MEMORY_H 755 help 756 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 757 758config ARCH_RPC 759 bool "RiscPC" 760 select ARCH_ACORN 761 select FIQ 762 select ARCH_MAY_HAVE_PC_FDC 763 select HAVE_PATA_PLATFORM 764 select ISA_DMA_API 765 select NO_IOPORT 766 select ARCH_SPARSEMEM_ENABLE 767 select ARCH_USES_GETTIMEOFFSET 768 select HAVE_IDE 769 select NEED_MACH_IO_H 770 select NEED_MACH_MEMORY_H 771 help 772 On the Acorn Risc-PC, Linux can support the internal IDE disk and 773 CD-ROM interface, serial and parallel port, and the floppy drive. 774 775config ARCH_SA1100 776 bool "SA1100-based" 777 select CLKSRC_MMIO 778 select CPU_SA1100 779 select ISA 780 select ARCH_SPARSEMEM_ENABLE 781 select ARCH_MTD_XIP 782 select ARCH_HAS_CPUFREQ 783 select CPU_FREQ 784 select GENERIC_CLOCKEVENTS 785 select CLKDEV_LOOKUP 786 select TICK_ONESHOT 787 select ARCH_REQUIRE_GPIOLIB 788 select HAVE_IDE 789 select NEED_MACH_MEMORY_H 790 select SPARSE_IRQ 791 help 792 Support for StrongARM 11x0 based boards. 793 794config ARCH_S3C24XX 795 bool "Samsung S3C24XX SoCs" 796 select GENERIC_GPIO 797 select ARCH_HAS_CPUFREQ 798 select HAVE_CLK 799 select CLKDEV_LOOKUP 800 select ARCH_USES_GETTIMEOFFSET 801 select HAVE_S3C2410_I2C if I2C 802 select HAVE_S3C_RTC if RTC_CLASS 803 select HAVE_S3C2410_WATCHDOG if WATCHDOG 804 select NEED_MACH_IO_H 805 help 806 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 807 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 808 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 809 Samsung SMDK2410 development board (and derivatives). 810 811config ARCH_S3C64XX 812 bool "Samsung S3C64XX" 813 select PLAT_SAMSUNG 814 select CPU_V6 815 select ARM_VIC 816 select HAVE_CLK 817 select HAVE_TCM 818 select CLKDEV_LOOKUP 819 select NO_IOPORT 820 select ARCH_USES_GETTIMEOFFSET 821 select ARCH_HAS_CPUFREQ 822 select ARCH_REQUIRE_GPIOLIB 823 select SAMSUNG_CLKSRC 824 select SAMSUNG_IRQ_VIC_TIMER 825 select S3C_GPIO_TRACK 826 select S3C_DEV_NAND 827 select USB_ARCH_HAS_OHCI 828 select SAMSUNG_GPIOLIB_4BIT 829 select HAVE_S3C2410_I2C if I2C 830 select HAVE_S3C2410_WATCHDOG if WATCHDOG 831 help 832 Samsung S3C64XX series based systems 833 834config ARCH_S5P64X0 835 bool "Samsung S5P6440 S5P6450" 836 select CPU_V6 837 select GENERIC_GPIO 838 select HAVE_CLK 839 select CLKDEV_LOOKUP 840 select CLKSRC_MMIO 841 select HAVE_S3C2410_WATCHDOG if WATCHDOG 842 select GENERIC_CLOCKEVENTS 843 select HAVE_S3C2410_I2C if I2C 844 select HAVE_S3C_RTC if RTC_CLASS 845 help 846 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 847 SMDK6450. 848 849config ARCH_S5PC100 850 bool "Samsung S5PC100" 851 select GENERIC_GPIO 852 select HAVE_CLK 853 select CLKDEV_LOOKUP 854 select CPU_V7 855 select ARCH_USES_GETTIMEOFFSET 856 select HAVE_S3C2410_I2C if I2C 857 select HAVE_S3C_RTC if RTC_CLASS 858 select HAVE_S3C2410_WATCHDOG if WATCHDOG 859 help 860 Samsung S5PC100 series based systems 861 862config ARCH_S5PV210 863 bool "Samsung S5PV210/S5PC110" 864 select CPU_V7 865 select ARCH_SPARSEMEM_ENABLE 866 select ARCH_HAS_HOLES_MEMORYMODEL 867 select GENERIC_GPIO 868 select HAVE_CLK 869 select CLKDEV_LOOKUP 870 select CLKSRC_MMIO 871 select ARCH_HAS_CPUFREQ 872 select GENERIC_CLOCKEVENTS 873 select HAVE_S3C2410_I2C if I2C 874 select HAVE_S3C_RTC if RTC_CLASS 875 select HAVE_S3C2410_WATCHDOG if WATCHDOG 876 select NEED_MACH_MEMORY_H 877 help 878 Samsung S5PV210/S5PC110 series based systems 879 880config ARCH_EXYNOS 881 bool "SAMSUNG EXYNOS" 882 select CPU_V7 883 select ARCH_SPARSEMEM_ENABLE 884 select ARCH_HAS_HOLES_MEMORYMODEL 885 select GENERIC_GPIO 886 select HAVE_CLK 887 select CLKDEV_LOOKUP 888 select ARCH_HAS_CPUFREQ 889 select GENERIC_CLOCKEVENTS 890 select HAVE_S3C_RTC if RTC_CLASS 891 select HAVE_S3C2410_I2C if I2C 892 select HAVE_S3C2410_WATCHDOG if WATCHDOG 893 select NEED_MACH_MEMORY_H 894 help 895 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 896 897config ARCH_SHARK 898 bool "Shark" 899 select CPU_SA110 900 select ISA 901 select ISA_DMA 902 select ZONE_DMA 903 select PCI 904 select ARCH_USES_GETTIMEOFFSET 905 select NEED_MACH_MEMORY_H 906 select NEED_MACH_IO_H 907 help 908 Support for the StrongARM based Digital DNARD machine, also known 909 as "Shark" (<http://www.shark-linux.de/shark.html>). 910 911config ARCH_U300 912 bool "ST-Ericsson U300 Series" 913 depends on MMU 914 select CLKSRC_MMIO 915 select CPU_ARM926T 916 select HAVE_TCM 917 select ARM_AMBA 918 select ARM_PATCH_PHYS_VIRT 919 select ARM_VIC 920 select GENERIC_CLOCKEVENTS 921 select CLKDEV_LOOKUP 922 select HAVE_MACH_CLKDEV 923 select GENERIC_GPIO 924 select ARCH_REQUIRE_GPIOLIB 925 help 926 Support for ST-Ericsson U300 series mobile platforms. 927 928config ARCH_U8500 929 bool "ST-Ericsson U8500 Series" 930 depends on MMU 931 select CPU_V7 932 select ARM_AMBA 933 select GENERIC_CLOCKEVENTS 934 select CLKDEV_LOOKUP 935 select ARCH_REQUIRE_GPIOLIB 936 select ARCH_HAS_CPUFREQ 937 select HAVE_SMP 938 select MIGHT_HAVE_CACHE_L2X0 939 help 940 Support for ST-Ericsson's Ux500 architecture 941 942config ARCH_NOMADIK 943 bool "STMicroelectronics Nomadik" 944 select ARM_AMBA 945 select ARM_VIC 946 select CPU_ARM926T 947 select CLKDEV_LOOKUP 948 select GENERIC_CLOCKEVENTS 949 select MIGHT_HAVE_CACHE_L2X0 950 select ARCH_REQUIRE_GPIOLIB 951 help 952 Support for the Nomadik platform by ST-Ericsson 953 954config ARCH_DAVINCI 955 bool "TI DaVinci" 956 select GENERIC_CLOCKEVENTS 957 select ARCH_REQUIRE_GPIOLIB 958 select ZONE_DMA 959 select HAVE_IDE 960 select CLKDEV_LOOKUP 961 select GENERIC_ALLOCATOR 962 select GENERIC_IRQ_CHIP 963 select ARCH_HAS_HOLES_MEMORYMODEL 964 help 965 Support for TI's DaVinci platform. 966 967config ARCH_OMAP 968 bool "TI OMAP" 969 select HAVE_CLK 970 select ARCH_REQUIRE_GPIOLIB 971 select ARCH_HAS_CPUFREQ 972 select CLKSRC_MMIO 973 select GENERIC_CLOCKEVENTS 974 select ARCH_HAS_HOLES_MEMORYMODEL 975 help 976 Support for TI's OMAP platform (OMAP1/2/3/4). 977 978config PLAT_SPEAR 979 bool "ST SPEAr" 980 select ARM_AMBA 981 select ARCH_REQUIRE_GPIOLIB 982 select CLKDEV_LOOKUP 983 select CLKSRC_MMIO 984 select GENERIC_CLOCKEVENTS 985 select HAVE_CLK 986 help 987 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 988 989config ARCH_VT8500 990 bool "VIA/WonderMedia 85xx" 991 select CPU_ARM926T 992 select GENERIC_GPIO 993 select ARCH_HAS_CPUFREQ 994 select GENERIC_CLOCKEVENTS 995 select ARCH_REQUIRE_GPIOLIB 996 select HAVE_PWM 997 help 998 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 999 1000config ARCH_ZYNQ 1001 bool "Xilinx Zynq ARM Cortex A9 Platform" 1002 select CPU_V7 1003 select GENERIC_CLOCKEVENTS 1004 select CLKDEV_LOOKUP 1005 select ARM_GIC 1006 select ARM_AMBA 1007 select ICST 1008 select MIGHT_HAVE_CACHE_L2X0 1009 select USE_OF 1010 help 1011 Support for Xilinx Zynq ARM Cortex A9 Platform 1012endchoice 1013 1014# 1015# This is sorted alphabetically by mach-* pathname. However, plat-* 1016# Kconfigs may be included either alphabetically (according to the 1017# plat- suffix) or along side the corresponding mach-* source. 1018# 1019source "arch/arm/mach-at91/Kconfig" 1020 1021source "arch/arm/mach-bcmring/Kconfig" 1022 1023source "arch/arm/mach-clps711x/Kconfig" 1024 1025source "arch/arm/mach-cns3xxx/Kconfig" 1026 1027source "arch/arm/mach-davinci/Kconfig" 1028 1029source "arch/arm/mach-dove/Kconfig" 1030 1031source "arch/arm/mach-ep93xx/Kconfig" 1032 1033source "arch/arm/mach-footbridge/Kconfig" 1034 1035source "arch/arm/mach-gemini/Kconfig" 1036 1037source "arch/arm/mach-h720x/Kconfig" 1038 1039source "arch/arm/mach-integrator/Kconfig" 1040 1041source "arch/arm/mach-iop32x/Kconfig" 1042 1043source "arch/arm/mach-iop33x/Kconfig" 1044 1045source "arch/arm/mach-iop13xx/Kconfig" 1046 1047source "arch/arm/mach-ixp4xx/Kconfig" 1048 1049source "arch/arm/mach-ixp2000/Kconfig" 1050 1051source "arch/arm/mach-ixp23xx/Kconfig" 1052 1053source "arch/arm/mach-kirkwood/Kconfig" 1054 1055source "arch/arm/mach-ks8695/Kconfig" 1056 1057source "arch/arm/mach-lpc32xx/Kconfig" 1058 1059source "arch/arm/mach-msm/Kconfig" 1060 1061source "arch/arm/mach-mv78xx0/Kconfig" 1062 1063source "arch/arm/plat-mxc/Kconfig" 1064 1065source "arch/arm/mach-mxs/Kconfig" 1066 1067source "arch/arm/mach-netx/Kconfig" 1068 1069source "arch/arm/mach-nomadik/Kconfig" 1070source "arch/arm/plat-nomadik/Kconfig" 1071 1072source "arch/arm/plat-omap/Kconfig" 1073 1074source "arch/arm/mach-omap1/Kconfig" 1075 1076source "arch/arm/mach-omap2/Kconfig" 1077 1078source "arch/arm/mach-orion5x/Kconfig" 1079 1080source "arch/arm/mach-pxa/Kconfig" 1081source "arch/arm/plat-pxa/Kconfig" 1082 1083source "arch/arm/mach-mmp/Kconfig" 1084 1085source "arch/arm/mach-realview/Kconfig" 1086 1087source "arch/arm/mach-sa1100/Kconfig" 1088 1089source "arch/arm/plat-samsung/Kconfig" 1090source "arch/arm/plat-s3c24xx/Kconfig" 1091source "arch/arm/plat-s5p/Kconfig" 1092 1093source "arch/arm/plat-spear/Kconfig" 1094 1095source "arch/arm/mach-s3c24xx/Kconfig" 1096if ARCH_S3C24XX 1097source "arch/arm/mach-s3c2412/Kconfig" 1098source "arch/arm/mach-s3c2440/Kconfig" 1099endif 1100 1101if ARCH_S3C64XX 1102source "arch/arm/mach-s3c64xx/Kconfig" 1103endif 1104 1105source "arch/arm/mach-s5p64x0/Kconfig" 1106 1107source "arch/arm/mach-s5pc100/Kconfig" 1108 1109source "arch/arm/mach-s5pv210/Kconfig" 1110 1111source "arch/arm/mach-exynos/Kconfig" 1112 1113source "arch/arm/mach-shmobile/Kconfig" 1114 1115source "arch/arm/mach-tegra/Kconfig" 1116 1117source "arch/arm/mach-u300/Kconfig" 1118 1119source "arch/arm/mach-ux500/Kconfig" 1120 1121source "arch/arm/mach-versatile/Kconfig" 1122 1123source "arch/arm/mach-vexpress/Kconfig" 1124source "arch/arm/plat-versatile/Kconfig" 1125 1126source "arch/arm/mach-vt8500/Kconfig" 1127 1128source "arch/arm/mach-w90x900/Kconfig" 1129 1130# Definitions to make life easier 1131config ARCH_ACORN 1132 bool 1133 1134config PLAT_IOP 1135 bool 1136 select GENERIC_CLOCKEVENTS 1137 1138config PLAT_ORION 1139 bool 1140 select CLKSRC_MMIO 1141 select GENERIC_IRQ_CHIP 1142 1143config PLAT_PXA 1144 bool 1145 1146config PLAT_VERSATILE 1147 bool 1148 1149config ARM_TIMER_SP804 1150 bool 1151 select CLKSRC_MMIO 1152 select HAVE_SCHED_CLOCK 1153 1154source arch/arm/mm/Kconfig 1155 1156config ARM_NR_BANKS 1157 int 1158 default 16 if ARCH_EP93XX 1159 default 8 1160 1161config IWMMXT 1162 bool "Enable iWMMXt support" 1163 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1164 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1165 help 1166 Enable support for iWMMXt context switching at run time if 1167 running on a CPU that supports it. 1168 1169config XSCALE_PMU 1170 bool 1171 depends on CPU_XSCALE 1172 default y 1173 1174config CPU_HAS_PMU 1175 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1176 (!ARCH_OMAP3 || OMAP3_EMU) 1177 default y 1178 bool 1179 1180config MULTI_IRQ_HANDLER 1181 bool 1182 help 1183 Allow each machine to specify it's own IRQ handler at run time. 1184 1185if !MMU 1186source "arch/arm/Kconfig-nommu" 1187endif 1188 1189config ARM_ERRATA_326103 1190 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1191 depends on CPU_V6 1192 help 1193 Executing a SWP instruction to read-only memory does not set bit 11 1194 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1195 treat the access as a read, preventing a COW from occurring and 1196 causing the faulting task to livelock. 1197 1198config ARM_ERRATA_411920 1199 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1200 depends on CPU_V6 || CPU_V6K 1201 help 1202 Invalidation of the Instruction Cache operation can 1203 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1204 It does not affect the MPCore. This option enables the ARM Ltd. 1205 recommended workaround. 1206 1207config ARM_ERRATA_430973 1208 bool "ARM errata: Stale prediction on replaced interworking branch" 1209 depends on CPU_V7 1210 help 1211 This option enables the workaround for the 430973 Cortex-A8 1212 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1213 interworking branch is replaced with another code sequence at the 1214 same virtual address, whether due to self-modifying code or virtual 1215 to physical address re-mapping, Cortex-A8 does not recover from the 1216 stale interworking branch prediction. This results in Cortex-A8 1217 executing the new code sequence in the incorrect ARM or Thumb state. 1218 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1219 and also flushes the branch target cache at every context switch. 1220 Note that setting specific bits in the ACTLR register may not be 1221 available in non-secure mode. 1222 1223config ARM_ERRATA_458693 1224 bool "ARM errata: Processor deadlock when a false hazard is created" 1225 depends on CPU_V7 1226 help 1227 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1228 erratum. For very specific sequences of memory operations, it is 1229 possible for a hazard condition intended for a cache line to instead 1230 be incorrectly associated with a different cache line. This false 1231 hazard might then cause a processor deadlock. The workaround enables 1232 the L1 caching of the NEON accesses and disables the PLD instruction 1233 in the ACTLR register. Note that setting specific bits in the ACTLR 1234 register may not be available in non-secure mode. 1235 1236config ARM_ERRATA_460075 1237 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1238 depends on CPU_V7 1239 help 1240 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1241 erratum. Any asynchronous access to the L2 cache may encounter a 1242 situation in which recent store transactions to the L2 cache are lost 1243 and overwritten with stale memory contents from external memory. The 1244 workaround disables the write-allocate mode for the L2 cache via the 1245 ACTLR register. Note that setting specific bits in the ACTLR register 1246 may not be available in non-secure mode. 1247 1248config ARM_ERRATA_742230 1249 bool "ARM errata: DMB operation may be faulty" 1250 depends on CPU_V7 && SMP 1251 help 1252 This option enables the workaround for the 742230 Cortex-A9 1253 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1254 between two write operations may not ensure the correct visibility 1255 ordering of the two writes. This workaround sets a specific bit in 1256 the diagnostic register of the Cortex-A9 which causes the DMB 1257 instruction to behave as a DSB, ensuring the correct behaviour of 1258 the two writes. 1259 1260config ARM_ERRATA_742231 1261 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1262 depends on CPU_V7 && SMP 1263 help 1264 This option enables the workaround for the 742231 Cortex-A9 1265 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1266 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1267 accessing some data located in the same cache line, may get corrupted 1268 data due to bad handling of the address hazard when the line gets 1269 replaced from one of the CPUs at the same time as another CPU is 1270 accessing it. This workaround sets specific bits in the diagnostic 1271 register of the Cortex-A9 which reduces the linefill issuing 1272 capabilities of the processor. 1273 1274config PL310_ERRATA_588369 1275 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1276 depends on CACHE_L2X0 1277 help 1278 The PL310 L2 cache controller implements three types of Clean & 1279 Invalidate maintenance operations: by Physical Address 1280 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1281 They are architecturally defined to behave as the execution of a 1282 clean operation followed immediately by an invalidate operation, 1283 both performing to the same memory location. This functionality 1284 is not correctly implemented in PL310 as clean lines are not 1285 invalidated as a result of these operations. 1286 1287config ARM_ERRATA_720789 1288 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1289 depends on CPU_V7 1290 help 1291 This option enables the workaround for the 720789 Cortex-A9 (prior to 1292 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1293 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1294 As a consequence of this erratum, some TLB entries which should be 1295 invalidated are not, resulting in an incoherency in the system page 1296 tables. The workaround changes the TLB flushing routines to invalidate 1297 entries regardless of the ASID. 1298 1299config PL310_ERRATA_727915 1300 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1301 depends on CACHE_L2X0 1302 help 1303 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1304 operation (offset 0x7FC). This operation runs in background so that 1305 PL310 can handle normal accesses while it is in progress. Under very 1306 rare circumstances, due to this erratum, write data can be lost when 1307 PL310 treats a cacheable write transaction during a Clean & 1308 Invalidate by Way operation. 1309 1310config ARM_ERRATA_743622 1311 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1312 depends on CPU_V7 1313 help 1314 This option enables the workaround for the 743622 Cortex-A9 1315 (r2p*) erratum. Under very rare conditions, a faulty 1316 optimisation in the Cortex-A9 Store Buffer may lead to data 1317 corruption. This workaround sets a specific bit in the diagnostic 1318 register of the Cortex-A9 which disables the Store Buffer 1319 optimisation, preventing the defect from occurring. This has no 1320 visible impact on the overall performance or power consumption of the 1321 processor. 1322 1323config ARM_ERRATA_751472 1324 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1325 depends on CPU_V7 1326 help 1327 This option enables the workaround for the 751472 Cortex-A9 (prior 1328 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1329 completion of a following broadcasted operation if the second 1330 operation is received by a CPU before the ICIALLUIS has completed, 1331 potentially leading to corrupted entries in the cache or TLB. 1332 1333config PL310_ERRATA_753970 1334 bool "PL310 errata: cache sync operation may be faulty" 1335 depends on CACHE_PL310 1336 help 1337 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1338 1339 Under some condition the effect of cache sync operation on 1340 the store buffer still remains when the operation completes. 1341 This means that the store buffer is always asked to drain and 1342 this prevents it from merging any further writes. The workaround 1343 is to replace the normal offset of cache sync operation (0x730) 1344 by another offset targeting an unmapped PL310 register 0x740. 1345 This has the same effect as the cache sync operation: store buffer 1346 drain and waiting for all buffers empty. 1347 1348config ARM_ERRATA_754322 1349 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1350 depends on CPU_V7 1351 help 1352 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1353 r3p*) erratum. A speculative memory access may cause a page table walk 1354 which starts prior to an ASID switch but completes afterwards. This 1355 can populate the micro-TLB with a stale entry which may be hit with 1356 the new ASID. This workaround places two dsb instructions in the mm 1357 switching code so that no page table walks can cross the ASID switch. 1358 1359config ARM_ERRATA_754327 1360 bool "ARM errata: no automatic Store Buffer drain" 1361 depends on CPU_V7 && SMP 1362 help 1363 This option enables the workaround for the 754327 Cortex-A9 (prior to 1364 r2p0) erratum. The Store Buffer does not have any automatic draining 1365 mechanism and therefore a livelock may occur if an external agent 1366 continuously polls a memory location waiting to observe an update. 1367 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1368 written polling loops from denying visibility of updates to memory. 1369 1370config ARM_ERRATA_364296 1371 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1372 depends on CPU_V6 && !SMP 1373 help 1374 This options enables the workaround for the 364296 ARM1136 1375 r0p2 erratum (possible cache data corruption with 1376 hit-under-miss enabled). It sets the undocumented bit 31 in 1377 the auxiliary control register and the FI bit in the control 1378 register, thus disabling hit-under-miss without putting the 1379 processor into full low interrupt latency mode. ARM11MPCore 1380 is not affected. 1381 1382config ARM_ERRATA_764369 1383 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1384 depends on CPU_V7 && SMP 1385 help 1386 This option enables the workaround for erratum 764369 1387 affecting Cortex-A9 MPCore with two or more processors (all 1388 current revisions). Under certain timing circumstances, a data 1389 cache line maintenance operation by MVA targeting an Inner 1390 Shareable memory region may fail to proceed up to either the 1391 Point of Coherency or to the Point of Unification of the 1392 system. This workaround adds a DSB instruction before the 1393 relevant cache maintenance functions and sets a specific bit 1394 in the diagnostic control register of the SCU. 1395 1396config PL310_ERRATA_769419 1397 bool "PL310 errata: no automatic Store Buffer drain" 1398 depends on CACHE_L2X0 1399 help 1400 On revisions of the PL310 prior to r3p2, the Store Buffer does 1401 not automatically drain. This can cause normal, non-cacheable 1402 writes to be retained when the memory system is idle, leading 1403 to suboptimal I/O performance for drivers using coherent DMA. 1404 This option adds a write barrier to the cpu_idle loop so that, 1405 on systems with an outer cache, the store buffer is drained 1406 explicitly. 1407 1408config ARM_ERRATA_775420 1409 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1410 depends on CPU_V7 1411 help 1412 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1413 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1414 operation aborts with MMU exception, it might cause the processor 1415 to deadlock. This workaround puts DSB before executing ISB if 1416 an abort may occur on cache maintenance. 1417 1418endmenu 1419 1420source "arch/arm/common/Kconfig" 1421 1422menu "Bus support" 1423 1424config ARM_AMBA 1425 bool 1426 1427config ISA 1428 bool 1429 help 1430 Find out whether you have ISA slots on your motherboard. ISA is the 1431 name of a bus system, i.e. the way the CPU talks to the other stuff 1432 inside your box. Other bus systems are PCI, EISA, MicroChannel 1433 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1434 newer boards don't support it. If you have ISA, say Y, otherwise N. 1435 1436# Select ISA DMA controller support 1437config ISA_DMA 1438 bool 1439 select ISA_DMA_API 1440 1441# Select ISA DMA interface 1442config ISA_DMA_API 1443 bool 1444 1445config PCI 1446 bool "PCI support" if MIGHT_HAVE_PCI 1447 help 1448 Find out whether you have a PCI motherboard. PCI is the name of a 1449 bus system, i.e. the way the CPU talks to the other stuff inside 1450 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1451 VESA. If you have PCI, say Y, otherwise N. 1452 1453config PCI_DOMAINS 1454 bool 1455 depends on PCI 1456 1457config PCI_NANOENGINE 1458 bool "BSE nanoEngine PCI support" 1459 depends on SA1100_NANOENGINE 1460 help 1461 Enable PCI on the BSE nanoEngine board. 1462 1463config PCI_SYSCALL 1464 def_bool PCI 1465 1466# Select the host bridge type 1467config PCI_HOST_VIA82C505 1468 bool 1469 depends on PCI && ARCH_SHARK 1470 default y 1471 1472config PCI_HOST_ITE8152 1473 bool 1474 depends on PCI && MACH_ARMCORE 1475 default y 1476 select DMABOUNCE 1477 1478source "drivers/pci/Kconfig" 1479 1480source "drivers/pcmcia/Kconfig" 1481 1482endmenu 1483 1484menu "Kernel Features" 1485 1486source "kernel/time/Kconfig" 1487 1488config HAVE_SMP 1489 bool 1490 help 1491 This option should be selected by machines which have an SMP- 1492 capable CPU. 1493 1494 The only effect of this option is to make the SMP-related 1495 options available to the user for configuration. 1496 1497config SMP 1498 bool "Symmetric Multi-Processing" 1499 depends on CPU_V6K || CPU_V7 1500 depends on GENERIC_CLOCKEVENTS 1501 depends on HAVE_SMP 1502 depends on MMU 1503 select USE_GENERIC_SMP_HELPERS 1504 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1505 help 1506 This enables support for systems with more than one CPU. If you have 1507 a system with only one CPU, like most personal computers, say N. If 1508 you have a system with more than one CPU, say Y. 1509 1510 If you say N here, the kernel will run on single and multiprocessor 1511 machines, but will use only one CPU of a multiprocessor machine. If 1512 you say Y here, the kernel will run on many, but not all, single 1513 processor machines. On a single processor machine, the kernel will 1514 run faster if you say N here. 1515 1516 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1517 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1518 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1519 1520 If you don't know what to do here, say N. 1521 1522config SMP_ON_UP 1523 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1524 depends on EXPERIMENTAL 1525 depends on SMP && !XIP_KERNEL 1526 default y 1527 help 1528 SMP kernels contain instructions which fail on non-SMP processors. 1529 Enabling this option allows the kernel to modify itself to make 1530 these instructions safe. Disabling it allows about 1K of space 1531 savings. 1532 1533 If you don't know what to do here, say Y. 1534 1535config ARM_CPU_TOPOLOGY 1536 bool "Support cpu topology definition" 1537 depends on SMP && CPU_V7 1538 default y 1539 help 1540 Support ARM cpu topology definition. The MPIDR register defines 1541 affinity between processors which is then used to describe the cpu 1542 topology of an ARM System. 1543 1544config SCHED_MC 1545 bool "Multi-core scheduler support" 1546 depends on ARM_CPU_TOPOLOGY 1547 help 1548 Multi-core scheduler support improves the CPU scheduler's decision 1549 making when dealing with multi-core CPU chips at a cost of slightly 1550 increased overhead in some places. If unsure say N here. 1551 1552config SCHED_SMT 1553 bool "SMT scheduler support" 1554 depends on ARM_CPU_TOPOLOGY 1555 help 1556 Improves the CPU scheduler's decision making when dealing with 1557 MultiThreading at a cost of slightly increased overhead in some 1558 places. If unsure say N here. 1559 1560config HAVE_ARM_SCU 1561 bool 1562 help 1563 This option enables support for the ARM system coherency unit 1564 1565config HAVE_ARM_TWD 1566 bool 1567 depends on SMP 1568 select TICK_ONESHOT 1569 help 1570 This options enables support for the ARM timer and watchdog unit 1571 1572choice 1573 prompt "Memory split" 1574 default VMSPLIT_3G 1575 help 1576 Select the desired split between kernel and user memory. 1577 1578 If you are not absolutely sure what you are doing, leave this 1579 option alone! 1580 1581 config VMSPLIT_3G 1582 bool "3G/1G user/kernel split" 1583 config VMSPLIT_2G 1584 bool "2G/2G user/kernel split" 1585 config VMSPLIT_1G 1586 bool "1G/3G user/kernel split" 1587endchoice 1588 1589config PAGE_OFFSET 1590 hex 1591 default 0x40000000 if VMSPLIT_1G 1592 default 0x80000000 if VMSPLIT_2G 1593 default 0xC0000000 1594 1595config NR_CPUS 1596 int "Maximum number of CPUs (2-32)" 1597 range 2 32 1598 depends on SMP 1599 default "4" 1600 1601config HOTPLUG_CPU 1602 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1603 depends on SMP && HOTPLUG && EXPERIMENTAL 1604 help 1605 Say Y here to experiment with turning CPUs off and on. CPUs 1606 can be controlled through /sys/devices/system/cpu. 1607 1608config LOCAL_TIMERS 1609 bool "Use local timer interrupts" 1610 depends on SMP 1611 default y 1612 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1613 help 1614 Enable support for local timers on SMP platforms, rather then the 1615 legacy IPI broadcast method. Local timers allows the system 1616 accounting to be spread across the timer interval, preventing a 1617 "thundering herd" at every timer tick. 1618 1619config ARCH_NR_GPIO 1620 int 1621 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1622 default 355 if ARCH_U8500 1623 default 264 if MACH_H4700 1624 default 0 1625 help 1626 Maximum number of GPIOs in the system. 1627 1628 If unsure, leave the default value. 1629 1630source kernel/Kconfig.preempt 1631 1632config HZ 1633 int 1634 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1635 ARCH_S5PV210 || ARCH_EXYNOS4 1636 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1637 default AT91_TIMER_HZ if ARCH_AT91 1638 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1639 default 100 1640 1641config THUMB2_KERNEL 1642 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1643 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1644 select AEABI 1645 select ARM_ASM_UNIFIED 1646 select ARM_UNWIND 1647 help 1648 By enabling this option, the kernel will be compiled in 1649 Thumb-2 mode. A compiler/assembler that understand the unified 1650 ARM-Thumb syntax is needed. 1651 1652 If unsure, say N. 1653 1654config THUMB2_AVOID_R_ARM_THM_JUMP11 1655 bool "Work around buggy Thumb-2 short branch relocations in gas" 1656 depends on THUMB2_KERNEL && MODULES 1657 default y 1658 help 1659 Various binutils versions can resolve Thumb-2 branches to 1660 locally-defined, preemptible global symbols as short-range "b.n" 1661 branch instructions. 1662 1663 This is a problem, because there's no guarantee the final 1664 destination of the symbol, or any candidate locations for a 1665 trampoline, are within range of the branch. For this reason, the 1666 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1667 relocation in modules at all, and it makes little sense to add 1668 support. 1669 1670 The symptom is that the kernel fails with an "unsupported 1671 relocation" error when loading some modules. 1672 1673 Until fixed tools are available, passing 1674 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1675 code which hits this problem, at the cost of a bit of extra runtime 1676 stack usage in some cases. 1677 1678 The problem is described in more detail at: 1679 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1680 1681 Only Thumb-2 kernels are affected. 1682 1683 Unless you are sure your tools don't have this problem, say Y. 1684 1685config ARM_ASM_UNIFIED 1686 bool 1687 1688config AEABI 1689 bool "Use the ARM EABI to compile the kernel" 1690 help 1691 This option allows for the kernel to be compiled using the latest 1692 ARM ABI (aka EABI). This is only useful if you are using a user 1693 space environment that is also compiled with EABI. 1694 1695 Since there are major incompatibilities between the legacy ABI and 1696 EABI, especially with regard to structure member alignment, this 1697 option also changes the kernel syscall calling convention to 1698 disambiguate both ABIs and allow for backward compatibility support 1699 (selected with CONFIG_OABI_COMPAT). 1700 1701 To use this you need GCC version 4.0.0 or later. 1702 1703config OABI_COMPAT 1704 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1705 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1706 default y 1707 help 1708 This option preserves the old syscall interface along with the 1709 new (ARM EABI) one. It also provides a compatibility layer to 1710 intercept syscalls that have structure arguments which layout 1711 in memory differs between the legacy ABI and the new ARM EABI 1712 (only for non "thumb" binaries). This option adds a tiny 1713 overhead to all syscalls and produces a slightly larger kernel. 1714 If you know you'll be using only pure EABI user space then you 1715 can say N here. If this option is not selected and you attempt 1716 to execute a legacy ABI binary then the result will be 1717 UNPREDICTABLE (in fact it can be predicted that it won't work 1718 at all). If in doubt say Y. 1719 1720config ARCH_HAS_HOLES_MEMORYMODEL 1721 bool 1722 1723config ARCH_SPARSEMEM_ENABLE 1724 bool 1725 1726config ARCH_SPARSEMEM_DEFAULT 1727 def_bool ARCH_SPARSEMEM_ENABLE 1728 1729config ARCH_SELECT_MEMORY_MODEL 1730 def_bool ARCH_SPARSEMEM_ENABLE 1731 1732config HAVE_ARCH_PFN_VALID 1733 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1734 1735config HIGHMEM 1736 bool "High Memory Support" 1737 depends on MMU 1738 help 1739 The address space of ARM processors is only 4 Gigabytes large 1740 and it has to accommodate user address space, kernel address 1741 space as well as some memory mapped IO. That means that, if you 1742 have a large amount of physical memory and/or IO, not all of the 1743 memory can be "permanently mapped" by the kernel. The physical 1744 memory that is not permanently mapped is called "high memory". 1745 1746 Depending on the selected kernel/user memory split, minimum 1747 vmalloc space and actual amount of RAM, you may not need this 1748 option which should result in a slightly faster kernel. 1749 1750 If unsure, say n. 1751 1752config HIGHPTE 1753 bool "Allocate 2nd-level pagetables from highmem" 1754 depends on HIGHMEM 1755 1756config HW_PERF_EVENTS 1757 bool "Enable hardware performance counter support for perf events" 1758 depends on PERF_EVENTS && CPU_HAS_PMU 1759 default y 1760 help 1761 Enable hardware performance counter support for perf events. If 1762 disabled, perf events will use software events only. 1763 1764source "mm/Kconfig" 1765 1766config FORCE_MAX_ZONEORDER 1767 int "Maximum zone order" if ARCH_SHMOBILE 1768 range 11 64 if ARCH_SHMOBILE 1769 default "9" if SA1111 1770 default "11" 1771 help 1772 The kernel memory allocator divides physically contiguous memory 1773 blocks into "zones", where each zone is a power of two number of 1774 pages. This option selects the largest power of two that the kernel 1775 keeps in the memory allocator. If you need to allocate very large 1776 blocks of physically contiguous memory, then you may need to 1777 increase this value. 1778 1779 This config option is actually maximum order plus one. For example, 1780 a value of 11 means that the largest free memory block is 2^10 pages. 1781 1782config LEDS 1783 bool "Timer and CPU usage LEDs" 1784 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1785 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1786 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1787 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1788 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1789 ARCH_AT91 || ARCH_DAVINCI || \ 1790 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1791 help 1792 If you say Y here, the LEDs on your machine will be used 1793 to provide useful information about your current system status. 1794 1795 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1796 be able to select which LEDs are active using the options below. If 1797 you are compiling a kernel for the EBSA-110 or the LART however, the 1798 red LED will simply flash regularly to indicate that the system is 1799 still functional. It is safe to say Y here if you have a CATS 1800 system, but the driver will do nothing. 1801 1802config LEDS_TIMER 1803 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1804 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1805 || MACH_OMAP_PERSEUS2 1806 depends on LEDS 1807 depends on !GENERIC_CLOCKEVENTS 1808 default y if ARCH_EBSA110 1809 help 1810 If you say Y here, one of the system LEDs (the green one on the 1811 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1812 will flash regularly to indicate that the system is still 1813 operational. This is mainly useful to kernel hackers who are 1814 debugging unstable kernels. 1815 1816 The LART uses the same LED for both Timer LED and CPU usage LED 1817 functions. You may choose to use both, but the Timer LED function 1818 will overrule the CPU usage LED. 1819 1820config LEDS_CPU 1821 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1822 !ARCH_OMAP) \ 1823 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1824 || MACH_OMAP_PERSEUS2 1825 depends on LEDS 1826 help 1827 If you say Y here, the red LED will be used to give a good real 1828 time indication of CPU usage, by lighting whenever the idle task 1829 is not currently executing. 1830 1831 The LART uses the same LED for both Timer LED and CPU usage LED 1832 functions. You may choose to use both, but the Timer LED function 1833 will overrule the CPU usage LED. 1834 1835config ALIGNMENT_TRAP 1836 bool 1837 depends on CPU_CP15_MMU 1838 default y if !ARCH_EBSA110 1839 select HAVE_PROC_CPU if PROC_FS 1840 help 1841 ARM processors cannot fetch/store information which is not 1842 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1843 address divisible by 4. On 32-bit ARM processors, these non-aligned 1844 fetch/store instructions will be emulated in software if you say 1845 here, which has a severe performance impact. This is necessary for 1846 correct operation of some network protocols. With an IP-only 1847 configuration it is safe to say N, otherwise say Y. 1848 1849config UACCESS_WITH_MEMCPY 1850 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1851 depends on MMU && EXPERIMENTAL 1852 default y if CPU_FEROCEON 1853 help 1854 Implement faster copy_to_user and clear_user methods for CPU 1855 cores where a 8-word STM instruction give significantly higher 1856 memory write throughput than a sequence of individual 32bit stores. 1857 1858 A possible side effect is a slight increase in scheduling latency 1859 between threads sharing the same address space if they invoke 1860 such copy operations with large buffers. 1861 1862 However, if the CPU data cache is using a write-allocate mode, 1863 this option is unlikely to provide any performance gain. 1864 1865config SECCOMP 1866 bool 1867 prompt "Enable seccomp to safely compute untrusted bytecode" 1868 ---help--- 1869 This kernel feature is useful for number crunching applications 1870 that may need to compute untrusted bytecode during their 1871 execution. By using pipes or other transports made available to 1872 the process as file descriptors supporting the read/write 1873 syscalls, it's possible to isolate those applications in 1874 their own address space using seccomp. Once seccomp is 1875 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1876 and the task is only allowed to execute a few safe syscalls 1877 defined by each seccomp mode. 1878 1879config CC_STACKPROTECTOR 1880 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1881 depends on EXPERIMENTAL 1882 help 1883 This option turns on the -fstack-protector GCC feature. This 1884 feature puts, at the beginning of functions, a canary value on 1885 the stack just before the return address, and validates 1886 the value just before actually returning. Stack based buffer 1887 overflows (that need to overwrite this return address) now also 1888 overwrite the canary, which gets detected and the attack is then 1889 neutralized via a kernel panic. 1890 This feature requires gcc version 4.2 or above. 1891 1892config DEPRECATED_PARAM_STRUCT 1893 bool "Provide old way to pass kernel parameters" 1894 help 1895 This was deprecated in 2001 and announced to live on for 5 years. 1896 Some old boot loaders still use this way. 1897 1898endmenu 1899 1900menu "Boot options" 1901 1902config USE_OF 1903 bool "Flattened Device Tree support" 1904 select OF 1905 select OF_EARLY_FLATTREE 1906 select IRQ_DOMAIN 1907 help 1908 Include support for flattened device tree machine descriptions. 1909 1910# Compressed boot loader in ROM. Yes, we really want to ask about 1911# TEXT and BSS so we preserve their values in the config files. 1912config ZBOOT_ROM_TEXT 1913 hex "Compressed ROM boot loader base address" 1914 default "0" 1915 help 1916 The physical address at which the ROM-able zImage is to be 1917 placed in the target. Platforms which normally make use of 1918 ROM-able zImage formats normally set this to a suitable 1919 value in their defconfig file. 1920 1921 If ZBOOT_ROM is not enabled, this has no effect. 1922 1923config ZBOOT_ROM_BSS 1924 hex "Compressed ROM boot loader BSS address" 1925 default "0" 1926 help 1927 The base address of an area of read/write memory in the target 1928 for the ROM-able zImage which must be available while the 1929 decompressor is running. It must be large enough to hold the 1930 entire decompressed kernel plus an additional 128 KiB. 1931 Platforms which normally make use of ROM-able zImage formats 1932 normally set this to a suitable value in their defconfig file. 1933 1934 If ZBOOT_ROM is not enabled, this has no effect. 1935 1936config ZBOOT_ROM 1937 bool "Compressed boot loader in ROM/flash" 1938 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1939 help 1940 Say Y here if you intend to execute your compressed kernel image 1941 (zImage) directly from ROM or flash. If unsure, say N. 1942 1943choice 1944 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1945 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1946 default ZBOOT_ROM_NONE 1947 help 1948 Include experimental SD/MMC loading code in the ROM-able zImage. 1949 With this enabled it is possible to write the the ROM-able zImage 1950 kernel image to an MMC or SD card and boot the kernel straight 1951 from the reset vector. At reset the processor Mask ROM will load 1952 the first part of the the ROM-able zImage which in turn loads the 1953 rest the kernel image to RAM. 1954 1955config ZBOOT_ROM_NONE 1956 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1957 help 1958 Do not load image from SD or MMC 1959 1960config ZBOOT_ROM_MMCIF 1961 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1962 help 1963 Load image from MMCIF hardware block. 1964 1965config ZBOOT_ROM_SH_MOBILE_SDHI 1966 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1967 help 1968 Load image from SDHI hardware block 1969 1970endchoice 1971 1972config ARM_APPENDED_DTB 1973 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1974 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1975 help 1976 With this option, the boot code will look for a device tree binary 1977 (DTB) appended to zImage 1978 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1979 1980 This is meant as a backward compatibility convenience for those 1981 systems with a bootloader that can't be upgraded to accommodate 1982 the documented boot protocol using a device tree. 1983 1984 Beware that there is very little in terms of protection against 1985 this option being confused by leftover garbage in memory that might 1986 look like a DTB header after a reboot if no actual DTB is appended 1987 to zImage. Do not leave this option active in a production kernel 1988 if you don't intend to always append a DTB. Proper passing of the 1989 location into r2 of a bootloader provided DTB is always preferable 1990 to this option. 1991 1992config ARM_ATAG_DTB_COMPAT 1993 bool "Supplement the appended DTB with traditional ATAG information" 1994 depends on ARM_APPENDED_DTB 1995 help 1996 Some old bootloaders can't be updated to a DTB capable one, yet 1997 they provide ATAGs with memory configuration, the ramdisk address, 1998 the kernel cmdline string, etc. Such information is dynamically 1999 provided by the bootloader and can't always be stored in a static 2000 DTB. To allow a device tree enabled kernel to be used with such 2001 bootloaders, this option allows zImage to extract the information 2002 from the ATAG list and store it at run time into the appended DTB. 2003 2004config CMDLINE 2005 string "Default kernel command string" 2006 default "" 2007 help 2008 On some architectures (EBSA110 and CATS), there is currently no way 2009 for the boot loader to pass arguments to the kernel. For these 2010 architectures, you should supply some command-line options at build 2011 time by entering them here. As a minimum, you should specify the 2012 memory size and the root device (e.g., mem=64M root=/dev/nfs). 2013 2014choice 2015 prompt "Kernel command line type" if CMDLINE != "" 2016 default CMDLINE_FROM_BOOTLOADER 2017 2018config CMDLINE_FROM_BOOTLOADER 2019 bool "Use bootloader kernel arguments if available" 2020 help 2021 Uses the command-line options passed by the boot loader. If 2022 the boot loader doesn't provide any, the default kernel command 2023 string provided in CMDLINE will be used. 2024 2025config CMDLINE_EXTEND 2026 bool "Extend bootloader kernel arguments" 2027 help 2028 The command-line arguments provided by the boot loader will be 2029 appended to the default kernel command string. 2030 2031config CMDLINE_FORCE 2032 bool "Always use the default kernel command string" 2033 help 2034 Always use the default kernel command string, even if the boot 2035 loader passes other arguments to the kernel. 2036 This is useful if you cannot or don't want to change the 2037 command-line options your boot loader passes to the kernel. 2038endchoice 2039 2040config XIP_KERNEL 2041 bool "Kernel Execute-In-Place from ROM" 2042 depends on !ZBOOT_ROM && !ARM_LPAE 2043 help 2044 Execute-In-Place allows the kernel to run from non-volatile storage 2045 directly addressable by the CPU, such as NOR flash. This saves RAM 2046 space since the text section of the kernel is not loaded from flash 2047 to RAM. Read-write sections, such as the data section and stack, 2048 are still copied to RAM. The XIP kernel is not compressed since 2049 it has to run directly from flash, so it will take more space to 2050 store it. The flash address used to link the kernel object files, 2051 and for storing it, is configuration dependent. Therefore, if you 2052 say Y here, you must know the proper physical address where to 2053 store the kernel image depending on your own flash memory usage. 2054 2055 Also note that the make target becomes "make xipImage" rather than 2056 "make zImage" or "make Image". The final kernel binary to put in 2057 ROM memory will be arch/arm/boot/xipImage. 2058 2059 If unsure, say N. 2060 2061config XIP_PHYS_ADDR 2062 hex "XIP Kernel Physical Location" 2063 depends on XIP_KERNEL 2064 default "0x00080000" 2065 help 2066 This is the physical address in your flash memory the kernel will 2067 be linked for and stored to. This address is dependent on your 2068 own flash usage. 2069 2070config KEXEC 2071 bool "Kexec system call (EXPERIMENTAL)" 2072 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) 2073 help 2074 kexec is a system call that implements the ability to shutdown your 2075 current kernel, and to start another kernel. It is like a reboot 2076 but it is independent of the system firmware. And like a reboot 2077 you can start any kernel with it, not just Linux. 2078 2079 It is an ongoing process to be certain the hardware in a machine 2080 is properly shutdown, so do not be surprised if this code does not 2081 initially work for you. It may help to enable device hotplugging 2082 support. 2083 2084config ATAGS_PROC 2085 bool "Export atags in procfs" 2086 depends on KEXEC 2087 default y 2088 help 2089 Should the atags used to boot the kernel be exported in an "atags" 2090 file in procfs. Useful with kexec. 2091 2092config CRASH_DUMP 2093 bool "Build kdump crash kernel (EXPERIMENTAL)" 2094 depends on EXPERIMENTAL 2095 help 2096 Generate crash dump after being started by kexec. This should 2097 be normally only set in special crash dump kernels which are 2098 loaded in the main kernel with kexec-tools into a specially 2099 reserved region and then later executed after a crash by 2100 kdump/kexec. The crash dump kernel must be compiled to a 2101 memory address not used by the main kernel 2102 2103 For more details see Documentation/kdump/kdump.txt 2104 2105config AUTO_ZRELADDR 2106 bool "Auto calculation of the decompressed kernel image address" 2107 depends on !ZBOOT_ROM && !ARCH_U300 2108 help 2109 ZRELADDR is the physical address where the decompressed kernel 2110 image will be placed. If AUTO_ZRELADDR is selected, the address 2111 will be determined at run-time by masking the current IP with 2112 0xf8000000. This assumes the zImage being placed in the first 128MB 2113 from start of memory. 2114 2115endmenu 2116 2117menu "CPU Power Management" 2118 2119if ARCH_HAS_CPUFREQ 2120 2121source "drivers/cpufreq/Kconfig" 2122 2123config CPU_FREQ_IMX 2124 tristate "CPUfreq driver for i.MX CPUs" 2125 depends on ARCH_MXC && CPU_FREQ 2126 select CPU_FREQ_TABLE 2127 help 2128 This enables the CPUfreq driver for i.MX CPUs. 2129 2130config CPU_FREQ_SA1100 2131 bool 2132 2133config CPU_FREQ_SA1110 2134 bool 2135 2136config CPU_FREQ_INTEGRATOR 2137 tristate "CPUfreq driver for ARM Integrator CPUs" 2138 depends on ARCH_INTEGRATOR && CPU_FREQ 2139 default y 2140 help 2141 This enables the CPUfreq driver for ARM Integrator CPUs. 2142 2143 For details, take a look at <file:Documentation/cpu-freq>. 2144 2145 If in doubt, say Y. 2146 2147config CPU_FREQ_PXA 2148 bool 2149 depends on CPU_FREQ && ARCH_PXA && PXA25x 2150 default y 2151 select CPU_FREQ_TABLE 2152 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2153 2154config CPU_FREQ_S3C 2155 bool 2156 help 2157 Internal configuration node for common cpufreq on Samsung SoC 2158 2159config CPU_FREQ_S3C24XX 2160 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2161 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL 2162 select CPU_FREQ_S3C 2163 help 2164 This enables the CPUfreq driver for the Samsung S3C24XX family 2165 of CPUs. 2166 2167 For details, take a look at <file:Documentation/cpu-freq>. 2168 2169 If in doubt, say N. 2170 2171config CPU_FREQ_S3C24XX_PLL 2172 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2173 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2174 help 2175 Compile in support for changing the PLL frequency from the 2176 S3C24XX series CPUfreq driver. The PLL takes time to settle 2177 after a frequency change, so by default it is not enabled. 2178 2179 This also means that the PLL tables for the selected CPU(s) will 2180 be built which may increase the size of the kernel image. 2181 2182config CPU_FREQ_S3C24XX_DEBUG 2183 bool "Debug CPUfreq Samsung driver core" 2184 depends on CPU_FREQ_S3C24XX 2185 help 2186 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2187 2188config CPU_FREQ_S3C24XX_IODEBUG 2189 bool "Debug CPUfreq Samsung driver IO timing" 2190 depends on CPU_FREQ_S3C24XX 2191 help 2192 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2193 2194config CPU_FREQ_S3C24XX_DEBUGFS 2195 bool "Export debugfs for CPUFreq" 2196 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2197 help 2198 Export status information via debugfs. 2199 2200endif 2201 2202source "drivers/cpuidle/Kconfig" 2203 2204endmenu 2205 2206menu "Floating point emulation" 2207 2208comment "At least one emulation must be selected" 2209 2210config FPE_NWFPE 2211 bool "NWFPE math emulation" 2212 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2213 ---help--- 2214 Say Y to include the NWFPE floating point emulator in the kernel. 2215 This is necessary to run most binaries. Linux does not currently 2216 support floating point hardware so you need to say Y here even if 2217 your machine has an FPA or floating point co-processor podule. 2218 2219 You may say N here if you are going to load the Acorn FPEmulator 2220 early in the bootup. 2221 2222config FPE_NWFPE_XP 2223 bool "Support extended precision" 2224 depends on FPE_NWFPE 2225 help 2226 Say Y to include 80-bit support in the kernel floating-point 2227 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2228 Note that gcc does not generate 80-bit operations by default, 2229 so in most cases this option only enlarges the size of the 2230 floating point emulator without any good reason. 2231 2232 You almost surely want to say N here. 2233 2234config FPE_FASTFPE 2235 bool "FastFPE math emulation (EXPERIMENTAL)" 2236 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2237 ---help--- 2238 Say Y here to include the FAST floating point emulator in the kernel. 2239 This is an experimental much faster emulator which now also has full 2240 precision for the mantissa. It does not support any exceptions. 2241 It is very simple, and approximately 3-6 times faster than NWFPE. 2242 2243 It should be sufficient for most programs. It may be not suitable 2244 for scientific calculations, but you have to check this for yourself. 2245 If you do not feel you need a faster FP emulation you should better 2246 choose NWFPE. 2247 2248config VFP 2249 bool "VFP-format floating point maths" 2250 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2251 help 2252 Say Y to include VFP support code in the kernel. This is needed 2253 if your hardware includes a VFP unit. 2254 2255 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2256 release notes and additional status information. 2257 2258 Say N if your target does not have VFP hardware. 2259 2260config VFPv3 2261 bool 2262 depends on VFP 2263 default y if CPU_V7 2264 2265config NEON 2266 bool "Advanced SIMD (NEON) Extension support" 2267 depends on VFPv3 && CPU_V7 2268 help 2269 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2270 Extension. 2271 2272endmenu 2273 2274menu "Userspace binary formats" 2275 2276source "fs/Kconfig.binfmt" 2277 2278config ARTHUR 2279 tristate "RISC OS personality" 2280 depends on !AEABI 2281 help 2282 Say Y here to include the kernel code necessary if you want to run 2283 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2284 experimental; if this sounds frightening, say N and sleep in peace. 2285 You can also say M here to compile this support as a module (which 2286 will be called arthur). 2287 2288endmenu 2289 2290menu "Power management options" 2291 2292source "kernel/power/Kconfig" 2293 2294config ARCH_SUSPEND_POSSIBLE 2295 depends on !ARCH_S5PC100 2296 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2297 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2298 def_bool y 2299 2300config ARM_CPU_SUSPEND 2301 def_bool PM_SLEEP 2302 2303endmenu 2304 2305source "net/Kconfig" 2306 2307source "drivers/Kconfig" 2308 2309source "fs/Kconfig" 2310 2311source "arch/arm/Kconfig.debug" 2312 2313source "security/Kconfig" 2314 2315source "crypto/Kconfig" 2316 2317source "lib/Kconfig" 2318