1 /*
2 * drivers/mtd/nand/au1550nd.c
3 *
4 * Copyright (C) 2004 Embedded Edge, LLC
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/slab.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/partitions.h>
19 #include <asm/io.h>
20
21 #include <asm/mach-au1x00/au1xxx.h>
22 #include <asm/mach-db1x00/bcsr.h>
23
24 /*
25 * MTD structure for NAND controller
26 */
27 static struct mtd_info *au1550_mtd = NULL;
28 static void __iomem *p_nand;
29 static int nand_width = 1; /* default x8 */
30 static void (*au1550_write_byte)(struct mtd_info *, u_char);
31
32 /*
33 * Define partitions for flash device
34 */
35 static const struct mtd_partition partition_info[] = {
36 {
37 .name = "NAND FS 0",
38 .offset = 0,
39 .size = 8 * 1024 * 1024},
40 {
41 .name = "NAND FS 1",
42 .offset = MTDPART_OFS_APPEND,
43 .size = MTDPART_SIZ_FULL}
44 };
45
46 /**
47 * au_read_byte - read one byte from the chip
48 * @mtd: MTD device structure
49 *
50 * read function for 8bit buswith
51 */
au_read_byte(struct mtd_info * mtd)52 static u_char au_read_byte(struct mtd_info *mtd)
53 {
54 struct nand_chip *this = mtd->priv;
55 u_char ret = readb(this->IO_ADDR_R);
56 au_sync();
57 return ret;
58 }
59
60 /**
61 * au_write_byte - write one byte to the chip
62 * @mtd: MTD device structure
63 * @byte: pointer to data byte to write
64 *
65 * write function for 8it buswith
66 */
au_write_byte(struct mtd_info * mtd,u_char byte)67 static void au_write_byte(struct mtd_info *mtd, u_char byte)
68 {
69 struct nand_chip *this = mtd->priv;
70 writeb(byte, this->IO_ADDR_W);
71 au_sync();
72 }
73
74 /**
75 * au_read_byte16 - read one byte endianess aware from the chip
76 * @mtd: MTD device structure
77 *
78 * read function for 16bit buswith with
79 * endianess conversion
80 */
au_read_byte16(struct mtd_info * mtd)81 static u_char au_read_byte16(struct mtd_info *mtd)
82 {
83 struct nand_chip *this = mtd->priv;
84 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
85 au_sync();
86 return ret;
87 }
88
89 /**
90 * au_write_byte16 - write one byte endianess aware to the chip
91 * @mtd: MTD device structure
92 * @byte: pointer to data byte to write
93 *
94 * write function for 16bit buswith with
95 * endianess conversion
96 */
au_write_byte16(struct mtd_info * mtd,u_char byte)97 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
98 {
99 struct nand_chip *this = mtd->priv;
100 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
101 au_sync();
102 }
103
104 /**
105 * au_read_word - read one word from the chip
106 * @mtd: MTD device structure
107 *
108 * read function for 16bit buswith without
109 * endianess conversion
110 */
au_read_word(struct mtd_info * mtd)111 static u16 au_read_word(struct mtd_info *mtd)
112 {
113 struct nand_chip *this = mtd->priv;
114 u16 ret = readw(this->IO_ADDR_R);
115 au_sync();
116 return ret;
117 }
118
119 /**
120 * au_write_buf - write buffer to chip
121 * @mtd: MTD device structure
122 * @buf: data buffer
123 * @len: number of bytes to write
124 *
125 * write function for 8bit buswith
126 */
au_write_buf(struct mtd_info * mtd,const u_char * buf,int len)127 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
128 {
129 int i;
130 struct nand_chip *this = mtd->priv;
131
132 for (i = 0; i < len; i++) {
133 writeb(buf[i], this->IO_ADDR_W);
134 au_sync();
135 }
136 }
137
138 /**
139 * au_read_buf - read chip data into buffer
140 * @mtd: MTD device structure
141 * @buf: buffer to store date
142 * @len: number of bytes to read
143 *
144 * read function for 8bit buswith
145 */
au_read_buf(struct mtd_info * mtd,u_char * buf,int len)146 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
147 {
148 int i;
149 struct nand_chip *this = mtd->priv;
150
151 for (i = 0; i < len; i++) {
152 buf[i] = readb(this->IO_ADDR_R);
153 au_sync();
154 }
155 }
156
157 /**
158 * au_verify_buf - Verify chip data against buffer
159 * @mtd: MTD device structure
160 * @buf: buffer containing the data to compare
161 * @len: number of bytes to compare
162 *
163 * verify function for 8bit buswith
164 */
au_verify_buf(struct mtd_info * mtd,const u_char * buf,int len)165 static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
166 {
167 int i;
168 struct nand_chip *this = mtd->priv;
169
170 for (i = 0; i < len; i++) {
171 if (buf[i] != readb(this->IO_ADDR_R))
172 return -EFAULT;
173 au_sync();
174 }
175
176 return 0;
177 }
178
179 /**
180 * au_write_buf16 - write buffer to chip
181 * @mtd: MTD device structure
182 * @buf: data buffer
183 * @len: number of bytes to write
184 *
185 * write function for 16bit buswith
186 */
au_write_buf16(struct mtd_info * mtd,const u_char * buf,int len)187 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
188 {
189 int i;
190 struct nand_chip *this = mtd->priv;
191 u16 *p = (u16 *) buf;
192 len >>= 1;
193
194 for (i = 0; i < len; i++) {
195 writew(p[i], this->IO_ADDR_W);
196 au_sync();
197 }
198
199 }
200
201 /**
202 * au_read_buf16 - read chip data into buffer
203 * @mtd: MTD device structure
204 * @buf: buffer to store date
205 * @len: number of bytes to read
206 *
207 * read function for 16bit buswith
208 */
au_read_buf16(struct mtd_info * mtd,u_char * buf,int len)209 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
210 {
211 int i;
212 struct nand_chip *this = mtd->priv;
213 u16 *p = (u16 *) buf;
214 len >>= 1;
215
216 for (i = 0; i < len; i++) {
217 p[i] = readw(this->IO_ADDR_R);
218 au_sync();
219 }
220 }
221
222 /**
223 * au_verify_buf16 - Verify chip data against buffer
224 * @mtd: MTD device structure
225 * @buf: buffer containing the data to compare
226 * @len: number of bytes to compare
227 *
228 * verify function for 16bit buswith
229 */
au_verify_buf16(struct mtd_info * mtd,const u_char * buf,int len)230 static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
231 {
232 int i;
233 struct nand_chip *this = mtd->priv;
234 u16 *p = (u16 *) buf;
235 len >>= 1;
236
237 for (i = 0; i < len; i++) {
238 if (p[i] != readw(this->IO_ADDR_R))
239 return -EFAULT;
240 au_sync();
241 }
242 return 0;
243 }
244
245 /* Select the chip by setting nCE to low */
246 #define NAND_CTL_SETNCE 1
247 /* Deselect the chip by setting nCE to high */
248 #define NAND_CTL_CLRNCE 2
249 /* Select the command latch by setting CLE to high */
250 #define NAND_CTL_SETCLE 3
251 /* Deselect the command latch by setting CLE to low */
252 #define NAND_CTL_CLRCLE 4
253 /* Select the address latch by setting ALE to high */
254 #define NAND_CTL_SETALE 5
255 /* Deselect the address latch by setting ALE to low */
256 #define NAND_CTL_CLRALE 6
257
au1550_hwcontrol(struct mtd_info * mtd,int cmd)258 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
259 {
260 register struct nand_chip *this = mtd->priv;
261
262 switch (cmd) {
263
264 case NAND_CTL_SETCLE:
265 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
266 break;
267
268 case NAND_CTL_CLRCLE:
269 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
270 break;
271
272 case NAND_CTL_SETALE:
273 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
274 break;
275
276 case NAND_CTL_CLRALE:
277 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
278 /* FIXME: Nobody knows why this is necessary,
279 * but it works only that way */
280 udelay(1);
281 break;
282
283 case NAND_CTL_SETNCE:
284 /* assert (force assert) chip enable */
285 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
286 break;
287
288 case NAND_CTL_CLRNCE:
289 /* deassert chip enable */
290 au_writel(0, MEM_STNDCTL);
291 break;
292 }
293
294 this->IO_ADDR_R = this->IO_ADDR_W;
295
296 /* Drain the writebuffer */
297 au_sync();
298 }
299
au1550_device_ready(struct mtd_info * mtd)300 int au1550_device_ready(struct mtd_info *mtd)
301 {
302 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
303 au_sync();
304 return ret;
305 }
306
307 /**
308 * au1550_select_chip - control -CE line
309 * Forbid driving -CE manually permitting the NAND controller to do this.
310 * Keeping -CE asserted during the whole sector reads interferes with the
311 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
312 * We only have to hold -CE low for the NAND read commands since the flash
313 * chip needs it to be asserted during chip not ready time but the NAND
314 * controller keeps it released.
315 *
316 * @mtd: MTD device structure
317 * @chip: chipnumber to select, -1 for deselect
318 */
au1550_select_chip(struct mtd_info * mtd,int chip)319 static void au1550_select_chip(struct mtd_info *mtd, int chip)
320 {
321 }
322
323 /**
324 * au1550_command - Send command to NAND device
325 * @mtd: MTD device structure
326 * @command: the command to be sent
327 * @column: the column address for this command, -1 if none
328 * @page_addr: the page address for this command, -1 if none
329 */
au1550_command(struct mtd_info * mtd,unsigned command,int column,int page_addr)330 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
331 {
332 register struct nand_chip *this = mtd->priv;
333 int ce_override = 0, i;
334 ulong flags;
335
336 /* Begin command latch cycle */
337 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
338 /*
339 * Write out the command to the device.
340 */
341 if (command == NAND_CMD_SEQIN) {
342 int readcmd;
343
344 if (column >= mtd->writesize) {
345 /* OOB area */
346 column -= mtd->writesize;
347 readcmd = NAND_CMD_READOOB;
348 } else if (column < 256) {
349 /* First 256 bytes --> READ0 */
350 readcmd = NAND_CMD_READ0;
351 } else {
352 column -= 256;
353 readcmd = NAND_CMD_READ1;
354 }
355 au1550_write_byte(mtd, readcmd);
356 }
357 au1550_write_byte(mtd, command);
358
359 /* Set ALE and clear CLE to start address cycle */
360 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
361
362 if (column != -1 || page_addr != -1) {
363 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
364
365 /* Serially input address */
366 if (column != -1) {
367 /* Adjust columns for 16 bit buswidth */
368 if (this->options & NAND_BUSWIDTH_16)
369 column >>= 1;
370 au1550_write_byte(mtd, column);
371 }
372 if (page_addr != -1) {
373 au1550_write_byte(mtd, (u8)(page_addr & 0xff));
374
375 if (command == NAND_CMD_READ0 ||
376 command == NAND_CMD_READ1 ||
377 command == NAND_CMD_READOOB) {
378 /*
379 * NAND controller will release -CE after
380 * the last address byte is written, so we'll
381 * have to forcibly assert it. No interrupts
382 * are allowed while we do this as we don't
383 * want the NOR flash or PCMCIA drivers to
384 * steal our precious bytes of data...
385 */
386 ce_override = 1;
387 local_irq_save(flags);
388 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
389 }
390
391 au1550_write_byte(mtd, (u8)(page_addr >> 8));
392
393 /* One more address cycle for devices > 32MiB */
394 if (this->chipsize > (32 << 20))
395 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
396 }
397 /* Latch in address */
398 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
399 }
400
401 /*
402 * Program and erase have their own busy handlers.
403 * Status and sequential in need no delay.
404 */
405 switch (command) {
406
407 case NAND_CMD_PAGEPROG:
408 case NAND_CMD_ERASE1:
409 case NAND_CMD_ERASE2:
410 case NAND_CMD_SEQIN:
411 case NAND_CMD_STATUS:
412 return;
413
414 case NAND_CMD_RESET:
415 break;
416
417 case NAND_CMD_READ0:
418 case NAND_CMD_READ1:
419 case NAND_CMD_READOOB:
420 /* Check if we're really driving -CE low (just in case) */
421 if (unlikely(!ce_override))
422 break;
423
424 /* Apply a short delay always to ensure that we do wait tWB. */
425 ndelay(100);
426 /* Wait for a chip to become ready... */
427 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
428 udelay(1);
429
430 /* Release -CE and re-enable interrupts. */
431 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
432 local_irq_restore(flags);
433 return;
434 }
435 /* Apply this short delay always to ensure that we do wait tWB. */
436 ndelay(100);
437
438 while(!this->dev_ready(mtd));
439 }
440
441
442 /*
443 * Main initialization routine
444 */
au1xxx_nand_init(void)445 static int __init au1xxx_nand_init(void)
446 {
447 struct nand_chip *this;
448 u16 boot_swapboot = 0; /* default value */
449 int retval;
450 u32 mem_staddr;
451 u32 nand_phys;
452
453 /* Allocate memory for MTD device structure and private data */
454 au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
455 if (!au1550_mtd) {
456 printk("Unable to allocate NAND MTD dev structure.\n");
457 return -ENOMEM;
458 }
459
460 /* Get pointer to private data */
461 this = (struct nand_chip *)(&au1550_mtd[1]);
462
463 /* Link the private data with the MTD structure */
464 au1550_mtd->priv = this;
465 au1550_mtd->owner = THIS_MODULE;
466
467
468 /* MEM_STNDCTL: disable ints, disable nand boot */
469 au_writel(0, MEM_STNDCTL);
470
471 #ifdef CONFIG_MIPS_PB1550
472 /* set gpio206 high */
473 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
474
475 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
476
477 switch (boot_swapboot) {
478 case 0:
479 case 2:
480 case 8:
481 case 0xC:
482 case 0xD:
483 /* x16 NAND Flash */
484 nand_width = 0;
485 break;
486 case 1:
487 case 9:
488 case 3:
489 case 0xE:
490 case 0xF:
491 /* x8 NAND Flash */
492 nand_width = 1;
493 break;
494 default:
495 printk("Pb1550 NAND: bad boot:swap\n");
496 retval = -EINVAL;
497 goto outmem;
498 }
499 #endif
500
501 /* Configure chip-select; normally done by boot code, e.g. YAMON */
502 #ifdef NAND_STCFG
503 if (NAND_CS == 0) {
504 au_writel(NAND_STCFG, MEM_STCFG0);
505 au_writel(NAND_STTIME, MEM_STTIME0);
506 au_writel(NAND_STADDR, MEM_STADDR0);
507 }
508 if (NAND_CS == 1) {
509 au_writel(NAND_STCFG, MEM_STCFG1);
510 au_writel(NAND_STTIME, MEM_STTIME1);
511 au_writel(NAND_STADDR, MEM_STADDR1);
512 }
513 if (NAND_CS == 2) {
514 au_writel(NAND_STCFG, MEM_STCFG2);
515 au_writel(NAND_STTIME, MEM_STTIME2);
516 au_writel(NAND_STADDR, MEM_STADDR2);
517 }
518 if (NAND_CS == 3) {
519 au_writel(NAND_STCFG, MEM_STCFG3);
520 au_writel(NAND_STTIME, MEM_STTIME3);
521 au_writel(NAND_STADDR, MEM_STADDR3);
522 }
523 #endif
524
525 /* Locate NAND chip-select in order to determine NAND phys address */
526 mem_staddr = 0x00000000;
527 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
528 mem_staddr = au_readl(MEM_STADDR0);
529 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
530 mem_staddr = au_readl(MEM_STADDR1);
531 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
532 mem_staddr = au_readl(MEM_STADDR2);
533 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
534 mem_staddr = au_readl(MEM_STADDR3);
535
536 if (mem_staddr == 0x00000000) {
537 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
538 kfree(au1550_mtd);
539 return 1;
540 }
541 nand_phys = (mem_staddr << 4) & 0xFFFC0000;
542
543 p_nand = ioremap(nand_phys, 0x1000);
544
545 /* make controller and MTD agree */
546 if (NAND_CS == 0)
547 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
548 if (NAND_CS == 1)
549 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
550 if (NAND_CS == 2)
551 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
552 if (NAND_CS == 3)
553 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
554
555 /* Set address of hardware control function */
556 this->dev_ready = au1550_device_ready;
557 this->select_chip = au1550_select_chip;
558 this->cmdfunc = au1550_command;
559
560 /* 30 us command delay time */
561 this->chip_delay = 30;
562 this->ecc.mode = NAND_ECC_SOFT;
563
564 this->options = NAND_NO_AUTOINCR;
565
566 if (!nand_width)
567 this->options |= NAND_BUSWIDTH_16;
568
569 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
570 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
571 this->read_word = au_read_word;
572 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
573 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
574 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
575
576 /* Scan to find existence of the device */
577 if (nand_scan(au1550_mtd, 1)) {
578 retval = -ENXIO;
579 goto outio;
580 }
581
582 /* Register the partitions */
583 add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info));
584
585 return 0;
586
587 outio:
588 iounmap(p_nand);
589
590 outmem:
591 kfree(au1550_mtd);
592 return retval;
593 }
594
595 module_init(au1xxx_nand_init);
596
597 /*
598 * Clean up routine
599 */
au1550_cleanup(void)600 static void __exit au1550_cleanup(void)
601 {
602 /* Release resources, unregister device */
603 nand_release(au1550_mtd);
604
605 /* Free the MTD device structure */
606 kfree(au1550_mtd);
607
608 /* Unmap */
609 iounmap(p_nand);
610 }
611
612 module_exit(au1550_cleanup);
613
614 MODULE_LICENSE("GPL");
615 MODULE_AUTHOR("Embedded Edge, LLC");
616 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
617