1 /* 2 * Copyright (c) 2000-2010 LSI Corporation. 3 * 4 * 5 * Name: mpi2_cnfg.h 6 * Title: MPI Configuration messages and pages 7 * Creation Date: November 10, 2006 8 * 9 * mpi2_cnfg.h Version: 02.00.16 10 * 11 * Version History 12 * --------------- 13 * 14 * Date Version Description 15 * -------- -------- ------------------------------------------------------ 16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 18 * Added Manufacturing Page 11. 19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 20 * define. 21 * 06-26-07 02.00.02 Adding generic structure for product-specific 22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 23 * Rework of BIOS Page 2 configuration page. 24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 25 * forms. 26 * Added configuration pages IOC Page 8 and Driver 27 * Persistent Mapping Page 0. 28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 30 * RAID Physical Disk Pages 0 and 1, RAID Configuration 31 * Page 0). 32 * Added new value for AccessStatus field of SAS Device 33 * Page 0 (_SATA_NEEDS_INITIALIZATION). 34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 37 * NVDATA. 38 * Modified IOC Page 7 to use masks and added field for 39 * SASBroadcastPrimitiveMasks. 40 * Added MPI2_CONFIG_PAGE_BIOS_4. 41 * Added MPI2_CONFIG_PAGE_LOG_0. 42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 43 * Added SAS Device IDs. 44 * Updated Integrated RAID configuration pages including 45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 46 * Page 0. 47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 50 * Added missing MaxNumRoutedSasAddresses field to 51 * MPI2_CONFIG_PAGE_EXPANDER_0. 52 * Added SAS Port Page 0. 53 * Modified structure layout for 54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 58 * to 0x000000FF. 59 * Added two new values for the Physical Disk Coercion Size 60 * bits in the Flags field of Manufacturing Page 4. 61 * Added product-specific Manufacturing pages 16 to 31. 62 * Modified Flags bits for controlling write cache on SATA 63 * drives in IO Unit Page 1. 64 * Added new bit to AdditionalControlFlags of SAS IO Unit 65 * Page 1 to control Invalid Topology Correction. 66 * Added additional defines for RAID Volume Page 0 67 * VolumeStatusFlags field. 68 * Modified meaning of RAID Volume Page 0 VolumeSettings 69 * define for auto-configure of hot-swap drives. 70 * Added SupportedPhysDisks field to RAID Volume Page 1 and 71 * added related defines. 72 * Added PhysDiskAttributes field (and related defines) to 73 * RAID Physical Disk Page 0. 74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 75 * Added three new DiscoveryStatus bits for SAS IO Unit 76 * Page 0 and SAS Expander Page 0. 77 * Removed multiplexing information from SAS IO Unit pages. 78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 79 * Removed Zone Address Resolved bit from PhyInfo and from 80 * Expander Page 0 Flags field. 81 * Added two new AccessStatus values to SAS Device Page 0 82 * for indicating routing problems. Added 3 reserved words 83 * to this page. 84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 85 * Inserted missing reserved field into structure for IOC 86 * Page 6. 87 * Added more pending task bits to RAID Volume Page 0 88 * VolumeStatusFlags defines. 89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 91 * and SAS Expander Page 0 to flag a downstream initiator 92 * when in simplified routing mode. 93 * Removed SATA Init Failure defines for DiscoveryStatus 94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 96 * Added PortGroups, DmaGroup, and ControlGroup fields to 97 * SAS Device Page 0. 98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 99 * Unit Page 6. 100 * Added expander reduced functionality data to SAS 101 * Expander Page 0. 102 * Added SAS PHY Page 2 and SAS PHY Page 3. 103 * 07-30-09 02.00.12 Added IO Unit Page 7. 104 * Added new device ids. 105 * Added SAS IO Unit Page 5. 106 * Added partial and slumber power management capable flags 107 * to SAS Device Page 0 Flags field. 108 * Added PhyInfo defines for power condition. 109 * Added Ethernet configuration pages. 110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 111 * Added SAS PHY Page 4 structure and defines. 112 * 02-10-10 02.00.14 Modified the comments for the configuration page 113 * structures that contain an array of data. The host 114 * should use the "count" field in the page data (e.g. the 115 * NumPhys field) to determine the number of valid elements 116 * in the array. 117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 118 * Added PowerManagementCapabilities to IO Unit Page 7. 119 * Added PortWidthModGroup field to 120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 124 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 125 * define. 126 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 127 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 128 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 129 * defines. 130 * -------------------------------------------------------------------------- 131 */ 132 133 #ifndef MPI2_CNFG_H 134 #define MPI2_CNFG_H 135 136 /***************************************************************************** 137 * Configuration Page Header and defines 138 *****************************************************************************/ 139 140 /* Config Page Header */ 141 typedef struct _MPI2_CONFIG_PAGE_HEADER 142 { 143 U8 PageVersion; /* 0x00 */ 144 U8 PageLength; /* 0x01 */ 145 U8 PageNumber; /* 0x02 */ 146 U8 PageType; /* 0x03 */ 147 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 148 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 149 150 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 151 { 152 MPI2_CONFIG_PAGE_HEADER Struct; 153 U8 Bytes[4]; 154 U16 Word16[2]; 155 U32 Word32; 156 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 157 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 158 159 /* Extended Config Page Header */ 160 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 161 { 162 U8 PageVersion; /* 0x00 */ 163 U8 Reserved1; /* 0x01 */ 164 U8 PageNumber; /* 0x02 */ 165 U8 PageType; /* 0x03 */ 166 U16 ExtPageLength; /* 0x04 */ 167 U8 ExtPageType; /* 0x06 */ 168 U8 Reserved2; /* 0x07 */ 169 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 170 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 171 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 172 173 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 174 { 175 MPI2_CONFIG_PAGE_HEADER Struct; 176 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 177 U8 Bytes[8]; 178 U16 Word16[4]; 179 U32 Word32[2]; 180 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 181 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 182 183 184 /* PageType field values */ 185 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 186 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 187 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 188 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 189 190 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 191 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 192 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 193 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 194 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 195 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 196 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 197 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 198 199 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 200 201 202 /* ExtPageType field values */ 203 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 204 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 205 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 206 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 207 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 208 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 209 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 210 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 211 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 212 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 213 214 215 /***************************************************************************** 216 * PageAddress defines 217 *****************************************************************************/ 218 219 /* RAID Volume PageAddress format */ 220 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 221 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 222 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 223 224 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 225 226 227 /* RAID Physical Disk PageAddress format */ 228 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 229 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 230 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 231 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 232 233 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 234 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 235 236 237 /* SAS Expander PageAddress format */ 238 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 239 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 240 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 241 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 242 243 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 244 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 245 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 246 247 248 /* SAS Device PageAddress format */ 249 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 250 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 251 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 252 253 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 254 255 256 /* SAS PHY PageAddress format */ 257 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 258 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 259 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 260 261 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 262 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 263 264 265 /* SAS Port PageAddress format */ 266 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 267 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 268 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 269 270 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 271 272 273 /* SAS Enclosure PageAddress format */ 274 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 275 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 276 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 277 278 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 279 280 281 /* RAID Configuration PageAddress format */ 282 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 283 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 284 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 285 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 286 287 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 288 289 290 /* Driver Persistent Mapping PageAddress format */ 291 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 292 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 293 294 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 295 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 296 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 297 298 299 /* Ethernet PageAddress format */ 300 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 301 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 302 303 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 304 305 306 307 /**************************************************************************** 308 * Configuration messages 309 ****************************************************************************/ 310 311 /* Configuration Request Message */ 312 typedef struct _MPI2_CONFIG_REQUEST 313 { 314 U8 Action; /* 0x00 */ 315 U8 SGLFlags; /* 0x01 */ 316 U8 ChainOffset; /* 0x02 */ 317 U8 Function; /* 0x03 */ 318 U16 ExtPageLength; /* 0x04 */ 319 U8 ExtPageType; /* 0x06 */ 320 U8 MsgFlags; /* 0x07 */ 321 U8 VP_ID; /* 0x08 */ 322 U8 VF_ID; /* 0x09 */ 323 U16 Reserved1; /* 0x0A */ 324 U32 Reserved2; /* 0x0C */ 325 U32 Reserved3; /* 0x10 */ 326 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 327 U32 PageAddress; /* 0x18 */ 328 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 329 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 330 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 331 332 /* values for the Action field */ 333 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 334 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 335 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 336 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 337 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 338 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 339 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 340 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 341 342 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 343 344 345 /* Config Reply Message */ 346 typedef struct _MPI2_CONFIG_REPLY 347 { 348 U8 Action; /* 0x00 */ 349 U8 SGLFlags; /* 0x01 */ 350 U8 MsgLength; /* 0x02 */ 351 U8 Function; /* 0x03 */ 352 U16 ExtPageLength; /* 0x04 */ 353 U8 ExtPageType; /* 0x06 */ 354 U8 MsgFlags; /* 0x07 */ 355 U8 VP_ID; /* 0x08 */ 356 U8 VF_ID; /* 0x09 */ 357 U16 Reserved1; /* 0x0A */ 358 U16 Reserved2; /* 0x0C */ 359 U16 IOCStatus; /* 0x0E */ 360 U32 IOCLogInfo; /* 0x10 */ 361 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 362 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 363 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 364 365 366 367 /***************************************************************************** 368 * 369 * C o n f i g u r a t i o n P a g e s 370 * 371 *****************************************************************************/ 372 373 /**************************************************************************** 374 * Manufacturing Config pages 375 ****************************************************************************/ 376 377 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 378 379 /* SAS */ 380 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 381 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 382 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 383 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 384 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 385 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 386 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 387 388 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 389 390 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 391 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 392 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 393 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 394 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 395 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 396 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 397 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 398 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 399 400 401 402 403 /* Manufacturing Page 0 */ 404 405 typedef struct _MPI2_CONFIG_PAGE_MAN_0 406 { 407 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 408 U8 ChipName[16]; /* 0x04 */ 409 U8 ChipRevision[8]; /* 0x14 */ 410 U8 BoardName[16]; /* 0x1C */ 411 U8 BoardAssembly[16]; /* 0x2C */ 412 U8 BoardTracerNumber[16]; /* 0x3C */ 413 } MPI2_CONFIG_PAGE_MAN_0, 414 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 415 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 416 417 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 418 419 420 /* Manufacturing Page 1 */ 421 422 typedef struct _MPI2_CONFIG_PAGE_MAN_1 423 { 424 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 425 U8 VPD[256]; /* 0x04 */ 426 } MPI2_CONFIG_PAGE_MAN_1, 427 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 428 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 429 430 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 431 432 433 typedef struct _MPI2_CHIP_REVISION_ID 434 { 435 U16 DeviceID; /* 0x00 */ 436 U8 PCIRevisionID; /* 0x02 */ 437 U8 Reserved; /* 0x03 */ 438 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 439 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 440 441 442 /* Manufacturing Page 2 */ 443 444 /* 445 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 446 * one and check Header.PageLength at runtime. 447 */ 448 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 449 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 450 #endif 451 452 typedef struct _MPI2_CONFIG_PAGE_MAN_2 453 { 454 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 455 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 456 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 457 } MPI2_CONFIG_PAGE_MAN_2, 458 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 459 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 460 461 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 462 463 464 /* Manufacturing Page 3 */ 465 466 /* 467 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 468 * one and check Header.PageLength at runtime. 469 */ 470 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 471 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 472 #endif 473 474 typedef struct _MPI2_CONFIG_PAGE_MAN_3 475 { 476 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 477 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 478 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 479 } MPI2_CONFIG_PAGE_MAN_3, 480 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 481 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 482 483 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 484 485 486 /* Manufacturing Page 4 */ 487 488 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 489 { 490 U8 PowerSaveFlags; /* 0x00 */ 491 U8 InternalOperationsSleepTime; /* 0x01 */ 492 U8 InternalOperationsRunTime; /* 0x02 */ 493 U8 HostIdleTime; /* 0x03 */ 494 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 495 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 496 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 497 498 /* defines for the PowerSaveFlags field */ 499 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 500 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 501 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 502 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 503 504 typedef struct _MPI2_CONFIG_PAGE_MAN_4 505 { 506 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 507 U32 Reserved1; /* 0x04 */ 508 U32 Flags; /* 0x08 */ 509 U8 InquirySize; /* 0x0C */ 510 U8 Reserved2; /* 0x0D */ 511 U16 Reserved3; /* 0x0E */ 512 U8 InquiryData[56]; /* 0x10 */ 513 U32 RAID0VolumeSettings; /* 0x48 */ 514 U32 RAID1EVolumeSettings; /* 0x4C */ 515 U32 RAID1VolumeSettings; /* 0x50 */ 516 U32 RAID10VolumeSettings; /* 0x54 */ 517 U32 Reserved4; /* 0x58 */ 518 U32 Reserved5; /* 0x5C */ 519 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 520 U8 MaxOCEDisks; /* 0x64 */ 521 U8 ResyncRate; /* 0x65 */ 522 U16 DataScrubDuration; /* 0x66 */ 523 U8 MaxHotSpares; /* 0x68 */ 524 U8 MaxPhysDisksPerVol; /* 0x69 */ 525 U8 MaxPhysDisks; /* 0x6A */ 526 U8 MaxVolumes; /* 0x6B */ 527 } MPI2_CONFIG_PAGE_MAN_4, 528 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 529 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 530 531 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 532 533 /* Manufacturing Page 4 Flags field */ 534 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 535 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 536 537 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 538 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 539 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 540 541 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 542 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 543 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 544 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 545 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 546 547 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 548 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 549 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 550 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 551 552 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 553 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 554 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 555 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 556 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 557 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 558 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 559 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 560 561 562 /* Manufacturing Page 5 */ 563 564 /* 565 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 566 * one and check the value returned for NumPhys at runtime. 567 */ 568 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 569 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 570 #endif 571 572 typedef struct _MPI2_MANUFACTURING5_ENTRY 573 { 574 U64 WWID; /* 0x00 */ 575 U64 DeviceName; /* 0x08 */ 576 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 577 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 578 579 typedef struct _MPI2_CONFIG_PAGE_MAN_5 580 { 581 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 582 U8 NumPhys; /* 0x04 */ 583 U8 Reserved1; /* 0x05 */ 584 U16 Reserved2; /* 0x06 */ 585 U32 Reserved3; /* 0x08 */ 586 U32 Reserved4; /* 0x0C */ 587 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 588 } MPI2_CONFIG_PAGE_MAN_5, 589 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 590 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 591 592 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 593 594 595 /* Manufacturing Page 6 */ 596 597 typedef struct _MPI2_CONFIG_PAGE_MAN_6 598 { 599 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 600 U32 ProductSpecificInfo;/* 0x04 */ 601 } MPI2_CONFIG_PAGE_MAN_6, 602 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 603 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 604 605 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 606 607 608 /* Manufacturing Page 7 */ 609 610 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 611 { 612 U32 Pinout; /* 0x00 */ 613 U8 Connector[16]; /* 0x04 */ 614 U8 Location; /* 0x14 */ 615 U8 Reserved1; /* 0x15 */ 616 U16 Slot; /* 0x16 */ 617 U32 Reserved2; /* 0x18 */ 618 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 619 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 620 621 /* defines for the Pinout field */ 622 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 623 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 624 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 625 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 626 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 627 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 628 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 629 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 630 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 631 #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 632 633 /* defines for the Location field */ 634 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 635 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 636 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 637 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 638 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 639 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 640 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 641 642 /* 643 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 644 * one and check the value returned for NumPhys at runtime. 645 */ 646 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 647 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 648 #endif 649 650 typedef struct _MPI2_CONFIG_PAGE_MAN_7 651 { 652 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 653 U32 Reserved1; /* 0x04 */ 654 U32 Reserved2; /* 0x08 */ 655 U32 Flags; /* 0x0C */ 656 U8 EnclosureName[16]; /* 0x10 */ 657 U8 NumPhys; /* 0x20 */ 658 U8 Reserved3; /* 0x21 */ 659 U16 Reserved4; /* 0x22 */ 660 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 661 } MPI2_CONFIG_PAGE_MAN_7, 662 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 663 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 664 665 #define MPI2_MANUFACTURING7_PAGEVERSION (0x00) 666 667 /* defines for the Flags field */ 668 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 669 670 671 /* 672 * Generic structure to use for product-specific manufacturing pages 673 * (currently Manufacturing Page 8 through Manufacturing Page 31). 674 */ 675 676 typedef struct _MPI2_CONFIG_PAGE_MAN_PS 677 { 678 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 679 U32 ProductSpecificInfo;/* 0x04 */ 680 } MPI2_CONFIG_PAGE_MAN_PS, 681 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 682 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 683 684 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 685 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 686 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 687 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 688 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 689 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 690 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 691 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 692 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 693 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 694 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 695 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 696 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 697 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 698 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 699 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 700 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 701 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 702 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 703 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 704 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 705 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 706 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 707 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 708 709 710 /**************************************************************************** 711 * IO Unit Config Pages 712 ****************************************************************************/ 713 714 /* IO Unit Page 0 */ 715 716 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 717 { 718 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 719 U64 UniqueValue; /* 0x04 */ 720 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 721 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 722 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 723 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 724 725 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 726 727 728 /* IO Unit Page 1 */ 729 730 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 731 { 732 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 733 U32 Flags; /* 0x04 */ 734 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 735 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 736 737 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 738 739 /* IO Unit Page 1 Flags defines */ 740 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 741 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 742 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 743 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 744 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 745 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 746 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 747 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 748 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 749 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 750 751 752 /* IO Unit Page 3 */ 753 754 /* 755 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 756 * one and check the value returned for GPIOCount at runtime. 757 */ 758 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 759 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 760 #endif 761 762 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 763 { 764 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 765 U8 GPIOCount; /* 0x04 */ 766 U8 Reserved1; /* 0x05 */ 767 U16 Reserved2; /* 0x06 */ 768 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 769 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 770 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 771 772 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 773 774 /* defines for IO Unit Page 3 GPIOVal field */ 775 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 776 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 777 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 778 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 779 780 781 /* IO Unit Page 5 */ 782 783 /* 784 * Upper layer code (drivers, utilities, etc.) should leave this define set to 785 * one and check the value returned for NumDmaEngines at runtime. 786 */ 787 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 788 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 789 #endif 790 791 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 792 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 793 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 794 U64 RaidAcceleratorBufferSize; /* 0x0C */ 795 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 796 U8 RAControlSize; /* 0x1C */ 797 U8 NumDmaEngines; /* 0x1D */ 798 U8 RAMinControlSize; /* 0x1E */ 799 U8 RAMaxControlSize; /* 0x1F */ 800 U32 Reserved1; /* 0x20 */ 801 U32 Reserved2; /* 0x24 */ 802 U32 Reserved3; /* 0x28 */ 803 U32 DmaEngineCapabilities 804 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 805 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 806 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 807 808 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 809 810 /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 811 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00) 812 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 813 814 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 815 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 816 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 817 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 818 819 820 /* IO Unit Page 6 */ 821 822 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 823 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 824 U16 Flags; /* 0x04 */ 825 U8 RAHostControlSize; /* 0x06 */ 826 U8 Reserved0; /* 0x07 */ 827 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 828 U32 Reserved1; /* 0x10 */ 829 U32 Reserved2; /* 0x14 */ 830 U32 Reserved3; /* 0x18 */ 831 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 832 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 833 834 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 835 836 /* defines for IO Unit Page 6 Flags field */ 837 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 838 839 840 /* IO Unit Page 7 */ 841 842 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 843 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 844 U16 Reserved1; /* 0x04 */ 845 U8 PCIeWidth; /* 0x06 */ 846 U8 PCIeSpeed; /* 0x07 */ 847 U32 ProcessorState; /* 0x08 */ 848 U32 PowerManagementCapabilities; /* 0x0C */ 849 U16 IOCTemperature; /* 0x10 */ 850 U8 IOCTemperatureUnits; /* 0x12 */ 851 U8 IOCSpeed; /* 0x13 */ 852 U32 Reserved3; /* 0x14 */ 853 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 854 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 855 856 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x01) 857 858 /* defines for IO Unit Page 7 PCIeWidth field */ 859 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 860 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 861 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 862 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 863 864 /* defines for IO Unit Page 7 PCIeSpeed field */ 865 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 866 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 867 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 868 869 /* defines for IO Unit Page 7 ProcessorState field */ 870 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 871 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 872 873 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 874 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 875 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 876 877 /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 878 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 879 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 880 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 881 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) 882 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) 883 884 885 /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 886 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 887 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 888 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 889 890 /* defines for IO Unit Page 7 IOCSpeed field */ 891 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 892 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 893 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 894 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 895 896 897 898 /**************************************************************************** 899 * IOC Config Pages 900 ****************************************************************************/ 901 902 /* IOC Page 0 */ 903 904 typedef struct _MPI2_CONFIG_PAGE_IOC_0 905 { 906 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 907 U32 Reserved1; /* 0x04 */ 908 U32 Reserved2; /* 0x08 */ 909 U16 VendorID; /* 0x0C */ 910 U16 DeviceID; /* 0x0E */ 911 U8 RevisionID; /* 0x10 */ 912 U8 Reserved3; /* 0x11 */ 913 U16 Reserved4; /* 0x12 */ 914 U32 ClassCode; /* 0x14 */ 915 U16 SubsystemVendorID; /* 0x18 */ 916 U16 SubsystemID; /* 0x1A */ 917 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 918 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 919 920 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 921 922 923 /* IOC Page 1 */ 924 925 typedef struct _MPI2_CONFIG_PAGE_IOC_1 926 { 927 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 928 U32 Flags; /* 0x04 */ 929 U32 CoalescingTimeout; /* 0x08 */ 930 U8 CoalescingDepth; /* 0x0C */ 931 U8 PCISlotNum; /* 0x0D */ 932 U8 PCIBusNum; /* 0x0E */ 933 U8 PCIDomainSegment; /* 0x0F */ 934 U32 Reserved1; /* 0x10 */ 935 U32 Reserved2; /* 0x14 */ 936 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 937 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 938 939 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 940 941 /* defines for IOC Page 1 Flags field */ 942 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 943 944 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 945 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 946 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 947 948 /* IOC Page 6 */ 949 950 typedef struct _MPI2_CONFIG_PAGE_IOC_6 951 { 952 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 953 U32 CapabilitiesFlags; /* 0x04 */ 954 U8 MaxDrivesRAID0; /* 0x08 */ 955 U8 MaxDrivesRAID1; /* 0x09 */ 956 U8 MaxDrivesRAID1E; /* 0x0A */ 957 U8 MaxDrivesRAID10; /* 0x0B */ 958 U8 MinDrivesRAID0; /* 0x0C */ 959 U8 MinDrivesRAID1; /* 0x0D */ 960 U8 MinDrivesRAID1E; /* 0x0E */ 961 U8 MinDrivesRAID10; /* 0x0F */ 962 U32 Reserved1; /* 0x10 */ 963 U8 MaxGlobalHotSpares; /* 0x14 */ 964 U8 MaxPhysDisks; /* 0x15 */ 965 U8 MaxVolumes; /* 0x16 */ 966 U8 MaxConfigs; /* 0x17 */ 967 U8 MaxOCEDisks; /* 0x18 */ 968 U8 Reserved2; /* 0x19 */ 969 U16 Reserved3; /* 0x1A */ 970 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 971 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 972 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 973 U32 Reserved4; /* 0x28 */ 974 U32 Reserved5; /* 0x2C */ 975 U16 DefaultMetadataSize; /* 0x30 */ 976 U16 Reserved6; /* 0x32 */ 977 U16 MaxBadBlockTableEntries; /* 0x34 */ 978 U16 Reserved7; /* 0x36 */ 979 U32 IRNvsramVersion; /* 0x38 */ 980 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 981 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 982 983 #define MPI2_IOCPAGE6_PAGEVERSION (0x04) 984 985 /* defines for IOC Page 6 CapabilitiesFlags */ 986 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 987 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 988 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 989 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 990 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 991 992 993 /* IOC Page 7 */ 994 995 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 996 997 typedef struct _MPI2_CONFIG_PAGE_IOC_7 998 { 999 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1000 U32 Reserved1; /* 0x04 */ 1001 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1002 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1003 U16 Reserved2; /* 0x1A */ 1004 U32 Reserved3; /* 0x1C */ 1005 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1006 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1007 1008 #define MPI2_IOCPAGE7_PAGEVERSION (0x01) 1009 1010 1011 /* IOC Page 8 */ 1012 1013 typedef struct _MPI2_CONFIG_PAGE_IOC_8 1014 { 1015 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1016 U8 NumDevsPerEnclosure; /* 0x04 */ 1017 U8 Reserved1; /* 0x05 */ 1018 U16 Reserved2; /* 0x06 */ 1019 U16 MaxPersistentEntries; /* 0x08 */ 1020 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1021 U16 Flags; /* 0x0C */ 1022 U16 Reserved3; /* 0x0E */ 1023 U16 IRVolumeMappingFlags; /* 0x10 */ 1024 U16 Reserved4; /* 0x12 */ 1025 U32 Reserved5; /* 0x14 */ 1026 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1027 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1028 1029 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1030 1031 /* defines for IOC Page 8 Flags field */ 1032 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1033 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1034 1035 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1036 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1037 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1038 1039 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1040 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1041 1042 /* defines for IOC Page 8 IRVolumeMappingFlags */ 1043 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1044 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1045 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1046 1047 1048 /**************************************************************************** 1049 * BIOS Config Pages 1050 ****************************************************************************/ 1051 1052 /* BIOS Page 1 */ 1053 1054 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1055 { 1056 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1057 U32 BiosOptions; /* 0x04 */ 1058 U32 IOCSettings; /* 0x08 */ 1059 U32 Reserved1; /* 0x0C */ 1060 U32 DeviceSettings; /* 0x10 */ 1061 U16 NumberOfDevices; /* 0x14 */ 1062 U16 Reserved2; /* 0x16 */ 1063 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1064 U16 IOTimeoutSequential; /* 0x1A */ 1065 U16 IOTimeoutOther; /* 0x1C */ 1066 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1067 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1068 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1069 1070 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04) 1071 1072 /* values for BIOS Page 1 BiosOptions field */ 1073 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1074 1075 /* values for BIOS Page 1 IOCSettings field */ 1076 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1077 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1078 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1079 1080 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1081 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1082 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1083 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1084 1085 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1086 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1087 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1088 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1089 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1090 1091 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1092 1093 /* values for BIOS Page 1 DeviceSettings field */ 1094 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1095 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1096 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1097 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1098 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1099 1100 1101 /* BIOS Page 2 */ 1102 1103 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1104 { 1105 U32 Reserved1; /* 0x00 */ 1106 U32 Reserved2; /* 0x04 */ 1107 U32 Reserved3; /* 0x08 */ 1108 U32 Reserved4; /* 0x0C */ 1109 U32 Reserved5; /* 0x10 */ 1110 U32 Reserved6; /* 0x14 */ 1111 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1112 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1113 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1114 1115 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1116 { 1117 U64 SASAddress; /* 0x00 */ 1118 U8 LUN[8]; /* 0x08 */ 1119 U32 Reserved1; /* 0x10 */ 1120 U32 Reserved2; /* 0x14 */ 1121 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1122 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1123 1124 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1125 { 1126 U64 EnclosureLogicalID; /* 0x00 */ 1127 U32 Reserved1; /* 0x08 */ 1128 U32 Reserved2; /* 0x0C */ 1129 U16 SlotNumber; /* 0x10 */ 1130 U16 Reserved3; /* 0x12 */ 1131 U32 Reserved4; /* 0x14 */ 1132 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1133 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1134 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1135 1136 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1137 { 1138 U64 DeviceName; /* 0x00 */ 1139 U8 LUN[8]; /* 0x08 */ 1140 U32 Reserved1; /* 0x10 */ 1141 U32 Reserved2; /* 0x14 */ 1142 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1143 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1144 1145 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1146 { 1147 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1148 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1149 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1150 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1151 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1152 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1153 1154 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1155 { 1156 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1157 U32 Reserved1; /* 0x04 */ 1158 U32 Reserved2; /* 0x08 */ 1159 U32 Reserved3; /* 0x0C */ 1160 U32 Reserved4; /* 0x10 */ 1161 U32 Reserved5; /* 0x14 */ 1162 U32 Reserved6; /* 0x18 */ 1163 U8 ReqBootDeviceForm; /* 0x1C */ 1164 U8 Reserved7; /* 0x1D */ 1165 U16 Reserved8; /* 0x1E */ 1166 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1167 U8 ReqAltBootDeviceForm; /* 0x38 */ 1168 U8 Reserved9; /* 0x39 */ 1169 U16 Reserved10; /* 0x3A */ 1170 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1171 U8 CurrentBootDeviceForm; /* 0x58 */ 1172 U8 Reserved11; /* 0x59 */ 1173 U16 Reserved12; /* 0x5A */ 1174 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1175 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1176 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1177 1178 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1179 1180 /* values for BIOS Page 2 BootDeviceForm fields */ 1181 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1182 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1183 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1184 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1185 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1186 1187 1188 /* BIOS Page 3 */ 1189 1190 typedef struct _MPI2_ADAPTER_INFO 1191 { 1192 U8 PciBusNumber; /* 0x00 */ 1193 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1194 U16 AdapterFlags; /* 0x02 */ 1195 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1196 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1197 1198 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1199 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1200 1201 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1202 { 1203 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1204 U32 GlobalFlags; /* 0x04 */ 1205 U32 BiosVersion; /* 0x08 */ 1206 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1207 U32 Reserved1; /* 0x1C */ 1208 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1209 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1210 1211 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1212 1213 /* values for BIOS Page 3 GlobalFlags */ 1214 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1215 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1216 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1217 1218 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1219 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1220 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1221 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1222 1223 1224 /* BIOS Page 4 */ 1225 1226 /* 1227 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1228 * one and check the value returned for NumPhys at runtime. 1229 */ 1230 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1231 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1232 #endif 1233 1234 typedef struct _MPI2_BIOS4_ENTRY 1235 { 1236 U64 ReassignmentWWID; /* 0x00 */ 1237 U64 ReassignmentDeviceName; /* 0x08 */ 1238 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1239 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1240 1241 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1242 { 1243 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1244 U8 NumPhys; /* 0x04 */ 1245 U8 Reserved1; /* 0x05 */ 1246 U16 Reserved2; /* 0x06 */ 1247 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1248 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1249 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1250 1251 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1252 1253 1254 /**************************************************************************** 1255 * RAID Volume Config Pages 1256 ****************************************************************************/ 1257 1258 /* RAID Volume Page 0 */ 1259 1260 typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1261 { 1262 U8 RAIDSetNum; /* 0x00 */ 1263 U8 PhysDiskMap; /* 0x01 */ 1264 U8 PhysDiskNum; /* 0x02 */ 1265 U8 Reserved; /* 0x03 */ 1266 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1267 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1268 1269 /* defines for the PhysDiskMap field */ 1270 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1271 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1272 1273 typedef struct _MPI2_RAIDVOL0_SETTINGS 1274 { 1275 U16 Settings; /* 0x00 */ 1276 U8 HotSparePool; /* 0x01 */ 1277 U8 Reserved; /* 0x02 */ 1278 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1279 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1280 1281 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1282 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1283 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1284 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1285 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1286 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1287 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1288 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1289 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1290 1291 /* RAID Volume Page 0 VolumeSettings defines */ 1292 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1293 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1294 1295 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1296 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1297 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1298 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1299 1300 /* 1301 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1302 * one and check the value returned for NumPhysDisks at runtime. 1303 */ 1304 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1305 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1306 #endif 1307 1308 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1309 { 1310 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1311 U16 DevHandle; /* 0x04 */ 1312 U8 VolumeState; /* 0x06 */ 1313 U8 VolumeType; /* 0x07 */ 1314 U32 VolumeStatusFlags; /* 0x08 */ 1315 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1316 U64 MaxLBA; /* 0x10 */ 1317 U32 StripeSize; /* 0x18 */ 1318 U16 BlockSize; /* 0x1C */ 1319 U16 Reserved1; /* 0x1E */ 1320 U8 SupportedPhysDisks; /* 0x20 */ 1321 U8 ResyncRate; /* 0x21 */ 1322 U16 DataScrubDuration; /* 0x22 */ 1323 U8 NumPhysDisks; /* 0x24 */ 1324 U8 Reserved2; /* 0x25 */ 1325 U8 Reserved3; /* 0x26 */ 1326 U8 InactiveStatus; /* 0x27 */ 1327 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1328 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1329 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1330 1331 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1332 1333 /* values for RAID VolumeState */ 1334 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1335 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1336 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1337 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1338 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1339 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1340 1341 /* values for RAID VolumeType */ 1342 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1343 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1344 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1345 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1346 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1347 1348 /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1349 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1350 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1351 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1352 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1353 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1354 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1355 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1356 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1357 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1358 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1359 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1360 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1361 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1362 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1363 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1364 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1365 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1366 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1367 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1368 1369 /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1370 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1371 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1372 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1373 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1374 1375 /* values for RAID Volume Page 0 InactiveStatus field */ 1376 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1377 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1378 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1379 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1380 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1381 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1382 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1383 1384 1385 /* RAID Volume Page 1 */ 1386 1387 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1388 { 1389 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1390 U16 DevHandle; /* 0x04 */ 1391 U16 Reserved0; /* 0x06 */ 1392 U8 GUID[24]; /* 0x08 */ 1393 U8 Name[16]; /* 0x20 */ 1394 U64 WWID; /* 0x30 */ 1395 U32 Reserved1; /* 0x38 */ 1396 U32 Reserved2; /* 0x3C */ 1397 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1398 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1399 1400 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1401 1402 1403 /**************************************************************************** 1404 * RAID Physical Disk Config Pages 1405 ****************************************************************************/ 1406 1407 /* RAID Physical Disk Page 0 */ 1408 1409 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1410 { 1411 U16 Reserved1; /* 0x00 */ 1412 U8 HotSparePool; /* 0x02 */ 1413 U8 Reserved2; /* 0x03 */ 1414 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1415 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1416 1417 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1418 1419 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1420 { 1421 U8 VendorID[8]; /* 0x00 */ 1422 U8 ProductID[16]; /* 0x08 */ 1423 U8 ProductRevLevel[4]; /* 0x18 */ 1424 U8 SerialNum[32]; /* 0x1C */ 1425 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1426 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1427 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1428 1429 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1430 { 1431 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1432 U16 DevHandle; /* 0x04 */ 1433 U8 Reserved1; /* 0x06 */ 1434 U8 PhysDiskNum; /* 0x07 */ 1435 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1436 U32 Reserved2; /* 0x0C */ 1437 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1438 U32 Reserved3; /* 0x4C */ 1439 U8 PhysDiskState; /* 0x50 */ 1440 U8 OfflineReason; /* 0x51 */ 1441 U8 IncompatibleReason; /* 0x52 */ 1442 U8 PhysDiskAttributes; /* 0x53 */ 1443 U32 PhysDiskStatusFlags; /* 0x54 */ 1444 U64 DeviceMaxLBA; /* 0x58 */ 1445 U64 HostMaxLBA; /* 0x60 */ 1446 U64 CoercedMaxLBA; /* 0x68 */ 1447 U16 BlockSize; /* 0x70 */ 1448 U16 Reserved5; /* 0x72 */ 1449 U32 Reserved6; /* 0x74 */ 1450 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1451 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1452 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1453 1454 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1455 1456 /* PhysDiskState defines */ 1457 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1458 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1459 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1460 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1461 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1462 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1463 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1464 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1465 1466 /* OfflineReason defines */ 1467 #define MPI2_PHYSDISK0_ONLINE (0x00) 1468 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1469 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1470 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1471 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1472 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1473 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1474 1475 /* IncompatibleReason defines */ 1476 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1477 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1478 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1479 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1480 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1481 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1482 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1483 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1484 1485 /* PhysDiskAttributes defines */ 1486 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1487 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1488 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1489 1490 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1491 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1492 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1493 1494 /* PhysDiskStatusFlags defines */ 1495 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1496 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1497 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1498 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1499 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1500 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1501 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1502 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1503 1504 1505 /* RAID Physical Disk Page 1 */ 1506 1507 /* 1508 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1509 * one and check the value returned for NumPhysDiskPaths at runtime. 1510 */ 1511 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1512 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1513 #endif 1514 1515 typedef struct _MPI2_RAIDPHYSDISK1_PATH 1516 { 1517 U16 DevHandle; /* 0x00 */ 1518 U16 Reserved1; /* 0x02 */ 1519 U64 WWID; /* 0x04 */ 1520 U64 OwnerWWID; /* 0x0C */ 1521 U8 OwnerIdentifier; /* 0x14 */ 1522 U8 Reserved2; /* 0x15 */ 1523 U16 Flags; /* 0x16 */ 1524 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1525 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1526 1527 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1528 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1529 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1530 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1531 1532 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1533 { 1534 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1535 U8 NumPhysDiskPaths; /* 0x04 */ 1536 U8 PhysDiskNum; /* 0x05 */ 1537 U16 Reserved1; /* 0x06 */ 1538 U32 Reserved2; /* 0x08 */ 1539 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1540 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1541 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1542 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1543 1544 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1545 1546 1547 /**************************************************************************** 1548 * values for fields used by several types of SAS Config Pages 1549 ****************************************************************************/ 1550 1551 /* values for NegotiatedLinkRates fields */ 1552 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1553 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1554 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1555 /* link rates used for Negotiated Physical and Logical Link Rate */ 1556 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1557 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1558 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1559 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1560 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1561 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1562 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1563 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1564 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1565 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1566 1567 1568 /* values for AttachedPhyInfo fields */ 1569 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1570 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1571 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1572 1573 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1574 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1575 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1576 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1577 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1578 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1579 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1580 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1581 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1582 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1583 1584 1585 /* values for PhyInfo fields */ 1586 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1587 1588 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1589 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1590 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1591 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1592 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1593 1594 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1595 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1596 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1597 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1598 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1599 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1600 1601 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1602 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1603 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1604 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1605 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1606 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1607 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1608 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1609 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1610 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1611 1612 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1613 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1614 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1615 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1616 1617 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1618 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1619 1620 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1621 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1622 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1623 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1624 1625 1626 /* values for SAS ProgrammedLinkRate fields */ 1627 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1628 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1629 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1630 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1631 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1632 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1633 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1634 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1635 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1636 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1637 1638 1639 /* values for SAS HwLinkRate fields */ 1640 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1641 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1642 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1643 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1644 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1645 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1646 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1647 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1648 1649 1650 1651 /**************************************************************************** 1652 * SAS IO Unit Config Pages 1653 ****************************************************************************/ 1654 1655 /* SAS IO Unit Page 0 */ 1656 1657 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1658 { 1659 U8 Port; /* 0x00 */ 1660 U8 PortFlags; /* 0x01 */ 1661 U8 PhyFlags; /* 0x02 */ 1662 U8 NegotiatedLinkRate; /* 0x03 */ 1663 U32 ControllerPhyDeviceInfo;/* 0x04 */ 1664 U16 AttachedDevHandle; /* 0x08 */ 1665 U16 ControllerDevHandle; /* 0x0A */ 1666 U32 DiscoveryStatus; /* 0x0C */ 1667 U32 Reserved; /* 0x10 */ 1668 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1669 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1670 1671 /* 1672 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1673 * one and check the value returned for NumPhys at runtime. 1674 */ 1675 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1676 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1677 #endif 1678 1679 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1680 { 1681 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1682 U32 Reserved1; /* 0x08 */ 1683 U8 NumPhys; /* 0x0C */ 1684 U8 Reserved2; /* 0x0D */ 1685 U16 Reserved3; /* 0x0E */ 1686 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1687 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 1688 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1689 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1690 1691 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1692 1693 /* values for SAS IO Unit Page 0 PortFlags */ 1694 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1695 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1696 1697 /* values for SAS IO Unit Page 0 PhyFlags */ 1698 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1699 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1700 1701 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1702 1703 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1704 1705 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 1706 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1707 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1708 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1709 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1710 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1711 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1712 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1713 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1714 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1715 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1716 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1717 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1718 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1719 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1720 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1721 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1722 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1723 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1724 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1725 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1726 1727 1728 /* SAS IO Unit Page 1 */ 1729 1730 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1731 { 1732 U8 Port; /* 0x00 */ 1733 U8 PortFlags; /* 0x01 */ 1734 U8 PhyFlags; /* 0x02 */ 1735 U8 MaxMinLinkRate; /* 0x03 */ 1736 U32 ControllerPhyDeviceInfo; /* 0x04 */ 1737 U16 MaxTargetPortConnectTime; /* 0x08 */ 1738 U16 Reserved1; /* 0x0A */ 1739 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1740 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1741 1742 /* 1743 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1744 * one and check the value returned for NumPhys at runtime. 1745 */ 1746 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1747 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1748 #endif 1749 1750 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1751 { 1752 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1753 U16 ControlFlags; /* 0x08 */ 1754 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1755 U16 AdditionalControlFlags; /* 0x0C */ 1756 U16 SASWideMaxQueueDepth; /* 0x0E */ 1757 U8 NumPhys; /* 0x10 */ 1758 U8 SATAMaxQDepth; /* 0x11 */ 1759 U8 ReportDeviceMissingDelay; /* 0x12 */ 1760 U8 IODeviceMissingDelay; /* 0x13 */ 1761 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1762 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 1763 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1764 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1765 1766 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1767 1768 /* values for SAS IO Unit Page 1 ControlFlags */ 1769 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1770 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1771 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1772 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1773 1774 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1775 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1776 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1777 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1778 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1779 1780 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1781 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1782 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1783 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1784 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1785 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1786 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1787 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1788 1789 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1790 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1791 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1792 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1793 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1794 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1795 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1796 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1797 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1798 1799 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1800 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1801 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1802 1803 /* values for SAS IO Unit Page 1 PortFlags */ 1804 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1805 1806 /* values for SAS IO Unit Page 1 PhyFlags */ 1807 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1808 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1809 1810 /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 1811 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1812 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1813 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1814 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 1815 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 1816 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 1817 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 1818 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 1819 1820 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 1821 1822 1823 /* SAS IO Unit Page 4 */ 1824 1825 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 1826 { 1827 U8 MaxTargetSpinup; /* 0x00 */ 1828 U8 SpinupDelay; /* 0x01 */ 1829 U16 Reserved1; /* 0x02 */ 1830 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 1831 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 1832 1833 /* 1834 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1835 * one and check the value returned for NumPhys at runtime. 1836 */ 1837 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 1838 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 1839 #endif 1840 1841 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 1842 { 1843 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1844 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1845 U32 Reserved1; /* 0x18 */ 1846 U32 Reserved2; /* 0x1C */ 1847 U32 Reserved3; /* 0x20 */ 1848 U8 BootDeviceWaitTime; /* 0x24 */ 1849 U8 Reserved4; /* 0x25 */ 1850 U16 Reserved5; /* 0x26 */ 1851 U8 NumPhys; /* 0x28 */ 1852 U8 PEInitialSpinupDelay; /* 0x29 */ 1853 U8 PEReplyDelay; /* 0x2A */ 1854 U8 Flags; /* 0x2B */ 1855 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 1856 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 1857 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 1858 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 1859 1860 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 1861 1862 /* defines for Flags field */ 1863 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 1864 1865 /* defines for PHY field */ 1866 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1867 1868 1869 /* SAS IO Unit Page 5 */ 1870 1871 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 1872 U8 ControlFlags; /* 0x00 */ 1873 U8 PortWidthModGroup; /* 0x01 */ 1874 U16 InactivityTimerExponent; /* 0x02 */ 1875 U8 SATAPartialTimeout; /* 0x04 */ 1876 U8 Reserved2; /* 0x05 */ 1877 U8 SATASlumberTimeout; /* 0x06 */ 1878 U8 Reserved3; /* 0x07 */ 1879 U8 SASPartialTimeout; /* 0x08 */ 1880 U8 Reserved4; /* 0x09 */ 1881 U8 SASSlumberTimeout; /* 0x0A */ 1882 U8 Reserved5; /* 0x0B */ 1883 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1884 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1885 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 1886 1887 /* defines for ControlFlags field */ 1888 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1889 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1890 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1891 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1892 1893 /* defines for PortWidthModeGroup field */ 1894 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 1895 1896 /* defines for InactivityTimerExponent field */ 1897 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 1898 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 1899 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 1900 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 1901 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 1902 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 1903 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 1904 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 1905 1906 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 1907 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 1908 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 1909 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 1910 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 1911 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 1912 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 1913 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 1914 1915 /* 1916 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1917 * one and check the value returned for NumPhys at runtime. 1918 */ 1919 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 1920 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 1921 #endif 1922 1923 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 1924 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1925 U8 NumPhys; /* 0x08 */ 1926 U8 Reserved1; /* 0x09 */ 1927 U16 Reserved2; /* 0x0A */ 1928 U32 Reserved3; /* 0x0C */ 1929 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings 1930 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 1931 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 1932 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 1933 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 1934 1935 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 1936 1937 1938 /* SAS IO Unit Page 6 */ 1939 1940 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 1941 U8 CurrentStatus; /* 0x00 */ 1942 U8 CurrentModulation; /* 0x01 */ 1943 U8 CurrentUtilization; /* 0x02 */ 1944 U8 Reserved1; /* 0x03 */ 1945 U32 Reserved2; /* 0x04 */ 1946 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 1947 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 1948 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 1949 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 1950 1951 /* defines for CurrentStatus field */ 1952 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 1953 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 1954 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 1955 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 1956 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 1957 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 1958 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 1959 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 1960 1961 /* defines for CurrentModulation field */ 1962 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 1963 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 1964 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 1965 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 1966 1967 /* 1968 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1969 * one and check the value returned for NumGroups at runtime. 1970 */ 1971 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 1972 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 1973 #endif 1974 1975 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 1976 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1977 U32 Reserved1; /* 0x08 */ 1978 U32 Reserved2; /* 0x0C */ 1979 U8 NumGroups; /* 0x10 */ 1980 U8 Reserved3; /* 0x11 */ 1981 U16 Reserved4; /* 0x12 */ 1982 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 1983 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 1984 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 1985 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 1986 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 1987 1988 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 1989 1990 1991 /* SAS IO Unit Page 7 */ 1992 1993 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 1994 U8 Flags; /* 0x00 */ 1995 U8 Reserved1; /* 0x01 */ 1996 U16 Reserved2; /* 0x02 */ 1997 U8 Threshold75Pct; /* 0x04 */ 1998 U8 Threshold50Pct; /* 0x05 */ 1999 U8 Threshold25Pct; /* 0x06 */ 2000 U8 Reserved3; /* 0x07 */ 2001 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2002 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2003 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2004 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2005 2006 /* defines for Flags field */ 2007 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2008 2009 2010 /* 2011 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2012 * one and check the value returned for NumGroups at runtime. 2013 */ 2014 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2015 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2016 #endif 2017 2018 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2019 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2020 U8 SamplingInterval; /* 0x08 */ 2021 U8 WindowLength; /* 0x09 */ 2022 U16 Reserved1; /* 0x0A */ 2023 U32 Reserved2; /* 0x0C */ 2024 U32 Reserved3; /* 0x10 */ 2025 U8 NumGroups; /* 0x14 */ 2026 U8 Reserved4; /* 0x15 */ 2027 U16 Reserved5; /* 0x16 */ 2028 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2029 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2030 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2031 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2032 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2033 2034 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2035 2036 2037 /* SAS IO Unit Page 8 */ 2038 2039 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2040 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2041 U32 Reserved1; /* 0x08 */ 2042 U32 PowerManagementCapabilities;/* 0x0C */ 2043 U32 Reserved2; /* 0x10 */ 2044 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2045 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2046 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2047 2048 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2049 2050 /* defines for PowerManagementCapabilities field */ 2051 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000) 2052 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800) 2053 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400) 2054 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200) 2055 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100) 2056 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010) 2057 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008) 2058 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004) 2059 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002) 2060 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001) 2061 2062 2063 2064 2065 /**************************************************************************** 2066 * SAS Expander Config Pages 2067 ****************************************************************************/ 2068 2069 /* SAS Expander Page 0 */ 2070 2071 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2072 { 2073 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2074 U8 PhysicalPort; /* 0x08 */ 2075 U8 ReportGenLength; /* 0x09 */ 2076 U16 EnclosureHandle; /* 0x0A */ 2077 U64 SASAddress; /* 0x0C */ 2078 U32 DiscoveryStatus; /* 0x14 */ 2079 U16 DevHandle; /* 0x18 */ 2080 U16 ParentDevHandle; /* 0x1A */ 2081 U16 ExpanderChangeCount; /* 0x1C */ 2082 U16 ExpanderRouteIndexes; /* 0x1E */ 2083 U8 NumPhys; /* 0x20 */ 2084 U8 SASLevel; /* 0x21 */ 2085 U16 Flags; /* 0x22 */ 2086 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2087 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2088 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2089 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2090 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2091 U16 ZoneLockInactivityLimit; /* 0x34 */ 2092 U16 Reserved1; /* 0x36 */ 2093 U8 TimeToReducedFunc; /* 0x38 */ 2094 U8 InitialTimeToReducedFunc; /* 0x39 */ 2095 U8 MaxReducedFuncTime; /* 0x3A */ 2096 U8 Reserved2; /* 0x3B */ 2097 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2098 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2099 2100 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2101 2102 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2103 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2104 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2105 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2106 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2107 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2108 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2109 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2110 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2111 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2112 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2113 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2114 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2115 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2116 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2117 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2118 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2119 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2120 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2121 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2122 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2123 2124 /* values for SAS Expander Page 0 Flags field */ 2125 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2126 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2127 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2128 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2129 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2130 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2131 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2132 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2133 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2134 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2135 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2136 2137 2138 /* SAS Expander Page 1 */ 2139 2140 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2141 { 2142 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2143 U8 PhysicalPort; /* 0x08 */ 2144 U8 Reserved1; /* 0x09 */ 2145 U16 Reserved2; /* 0x0A */ 2146 U8 NumPhys; /* 0x0C */ 2147 U8 Phy; /* 0x0D */ 2148 U16 NumTableEntriesProgrammed; /* 0x0E */ 2149 U8 ProgrammedLinkRate; /* 0x10 */ 2150 U8 HwLinkRate; /* 0x11 */ 2151 U16 AttachedDevHandle; /* 0x12 */ 2152 U32 PhyInfo; /* 0x14 */ 2153 U32 AttachedDeviceInfo; /* 0x18 */ 2154 U16 ExpanderDevHandle; /* 0x1C */ 2155 U8 ChangeCount; /* 0x1E */ 2156 U8 NegotiatedLinkRate; /* 0x1F */ 2157 U8 PhyIdentifier; /* 0x20 */ 2158 U8 AttachedPhyIdentifier; /* 0x21 */ 2159 U8 Reserved3; /* 0x22 */ 2160 U8 DiscoveryInfo; /* 0x23 */ 2161 U32 AttachedPhyInfo; /* 0x24 */ 2162 U8 ZoneGroup; /* 0x28 */ 2163 U8 SelfConfigStatus; /* 0x29 */ 2164 U16 Reserved4; /* 0x2A */ 2165 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2166 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2167 2168 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2169 2170 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2171 2172 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2173 2174 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2175 2176 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2177 2178 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2179 2180 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2181 2182 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2183 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2184 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2185 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2186 2187 2188 /**************************************************************************** 2189 * SAS Device Config Pages 2190 ****************************************************************************/ 2191 2192 /* SAS Device Page 0 */ 2193 2194 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2195 { 2196 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2197 U16 Slot; /* 0x08 */ 2198 U16 EnclosureHandle; /* 0x0A */ 2199 U64 SASAddress; /* 0x0C */ 2200 U16 ParentDevHandle; /* 0x14 */ 2201 U8 PhyNum; /* 0x16 */ 2202 U8 AccessStatus; /* 0x17 */ 2203 U16 DevHandle; /* 0x18 */ 2204 U8 AttachedPhyIdentifier; /* 0x1A */ 2205 U8 ZoneGroup; /* 0x1B */ 2206 U32 DeviceInfo; /* 0x1C */ 2207 U16 Flags; /* 0x20 */ 2208 U8 PhysicalPort; /* 0x22 */ 2209 U8 MaxPortConnections; /* 0x23 */ 2210 U64 DeviceName; /* 0x24 */ 2211 U8 PortGroups; /* 0x2C */ 2212 U8 DmaGroup; /* 0x2D */ 2213 U8 ControlGroup; /* 0x2E */ 2214 U8 Reserved1; /* 0x2F */ 2215 U32 Reserved2; /* 0x30 */ 2216 U32 Reserved3; /* 0x34 */ 2217 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2218 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2219 2220 #define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2221 2222 /* values for SAS Device Page 0 AccessStatus field */ 2223 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2224 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2225 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2226 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2227 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2228 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2229 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2230 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2231 /* specific values for SATA Init failures */ 2232 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2233 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2234 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2235 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2236 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2237 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2238 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2239 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2240 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2241 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2242 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2243 2244 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2245 2246 /* values for SAS Device Page 0 Flags field */ 2247 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2248 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2249 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2250 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2251 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2252 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2253 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2254 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2255 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2256 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2257 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2258 2259 2260 /* SAS Device Page 1 */ 2261 2262 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2263 { 2264 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2265 U32 Reserved1; /* 0x08 */ 2266 U64 SASAddress; /* 0x0C */ 2267 U32 Reserved2; /* 0x14 */ 2268 U16 DevHandle; /* 0x18 */ 2269 U16 Reserved3; /* 0x1A */ 2270 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2271 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2272 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2273 2274 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2275 2276 2277 /**************************************************************************** 2278 * SAS PHY Config Pages 2279 ****************************************************************************/ 2280 2281 /* SAS PHY Page 0 */ 2282 2283 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2284 { 2285 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2286 U16 OwnerDevHandle; /* 0x08 */ 2287 U16 Reserved1; /* 0x0A */ 2288 U16 AttachedDevHandle; /* 0x0C */ 2289 U8 AttachedPhyIdentifier; /* 0x0E */ 2290 U8 Reserved2; /* 0x0F */ 2291 U32 AttachedPhyInfo; /* 0x10 */ 2292 U8 ProgrammedLinkRate; /* 0x14 */ 2293 U8 HwLinkRate; /* 0x15 */ 2294 U8 ChangeCount; /* 0x16 */ 2295 U8 Flags; /* 0x17 */ 2296 U32 PhyInfo; /* 0x18 */ 2297 U8 NegotiatedLinkRate; /* 0x1C */ 2298 U8 Reserved3; /* 0x1D */ 2299 U16 Reserved4; /* 0x1E */ 2300 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2301 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2302 2303 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2304 2305 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2306 2307 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2308 2309 /* values for SAS PHY Page 0 Flags field */ 2310 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2311 2312 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2313 2314 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2315 2316 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2317 2318 2319 /* SAS PHY Page 1 */ 2320 2321 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2322 { 2323 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2324 U32 Reserved1; /* 0x08 */ 2325 U32 InvalidDwordCount; /* 0x0C */ 2326 U32 RunningDisparityErrorCount; /* 0x10 */ 2327 U32 LossDwordSynchCount; /* 0x14 */ 2328 U32 PhyResetProblemCount; /* 0x18 */ 2329 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2330 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2331 2332 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2333 2334 2335 /* SAS PHY Page 2 */ 2336 2337 typedef struct _MPI2_SASPHY2_PHY_EVENT { 2338 U8 PhyEventCode; /* 0x00 */ 2339 U8 Reserved1; /* 0x01 */ 2340 U16 Reserved2; /* 0x02 */ 2341 U32 PhyEventInfo; /* 0x04 */ 2342 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2343 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2344 2345 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2346 2347 2348 /* 2349 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2350 * one and check the value returned for NumPhyEvents at runtime. 2351 */ 2352 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2353 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2354 #endif 2355 2356 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 2357 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2358 U32 Reserved1; /* 0x08 */ 2359 U8 NumPhyEvents; /* 0x0C */ 2360 U8 Reserved2; /* 0x0D */ 2361 U16 Reserved3; /* 0x0E */ 2362 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; 2363 /* 0x10 */ 2364 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2365 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2366 2367 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2368 2369 2370 /* SAS PHY Page 3 */ 2371 2372 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 2373 U8 PhyEventCode; /* 0x00 */ 2374 U8 Reserved1; /* 0x01 */ 2375 U16 Reserved2; /* 0x02 */ 2376 U8 CounterType; /* 0x04 */ 2377 U8 ThresholdWindow; /* 0x05 */ 2378 U8 TimeUnits; /* 0x06 */ 2379 U8 Reserved3; /* 0x07 */ 2380 U32 EventThreshold; /* 0x08 */ 2381 U16 ThresholdFlags; /* 0x0C */ 2382 U16 Reserved4; /* 0x0E */ 2383 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2384 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2385 2386 /* values for PhyEventCode field */ 2387 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2388 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2389 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2390 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2391 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2392 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2393 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2394 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2395 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2396 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2397 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2398 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2399 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2400 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2401 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2402 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2403 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2404 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2405 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2406 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2407 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2408 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2409 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2410 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2411 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2412 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2413 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2414 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2415 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2416 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2417 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2418 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2419 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2420 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2421 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2422 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2423 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2424 2425 /* values for the CounterType field */ 2426 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2427 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2428 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2429 2430 /* values for the TimeUnits field */ 2431 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2432 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2433 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2434 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2435 2436 /* values for the ThresholdFlags field */ 2437 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2438 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2439 2440 /* 2441 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2442 * one and check the value returned for NumPhyEvents at runtime. 2443 */ 2444 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2445 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2446 #endif 2447 2448 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 2449 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2450 U32 Reserved1; /* 0x08 */ 2451 U8 NumPhyEvents; /* 0x0C */ 2452 U8 Reserved2; /* 0x0D */ 2453 U16 Reserved3; /* 0x0E */ 2454 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig 2455 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2456 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2457 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2458 2459 #define MPI2_SASPHY3_PAGEVERSION (0x00) 2460 2461 2462 /* SAS PHY Page 4 */ 2463 2464 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 2465 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2466 U16 Reserved1; /* 0x08 */ 2467 U8 Reserved2; /* 0x0A */ 2468 U8 Flags; /* 0x0B */ 2469 U8 InitialFrame[28]; /* 0x0C */ 2470 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2471 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2472 2473 #define MPI2_SASPHY4_PAGEVERSION (0x00) 2474 2475 /* values for the Flags field */ 2476 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2477 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2478 2479 2480 2481 2482 /**************************************************************************** 2483 * SAS Port Config Pages 2484 ****************************************************************************/ 2485 2486 /* SAS Port Page 0 */ 2487 2488 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2489 { 2490 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2491 U8 PortNumber; /* 0x08 */ 2492 U8 PhysicalPort; /* 0x09 */ 2493 U8 PortWidth; /* 0x0A */ 2494 U8 PhysicalPortWidth; /* 0x0B */ 2495 U8 ZoneGroup; /* 0x0C */ 2496 U8 Reserved1; /* 0x0D */ 2497 U16 Reserved2; /* 0x0E */ 2498 U64 SASAddress; /* 0x10 */ 2499 U32 DeviceInfo; /* 0x18 */ 2500 U32 Reserved3; /* 0x1C */ 2501 U32 Reserved4; /* 0x20 */ 2502 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2503 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2504 2505 #define MPI2_SASPORT0_PAGEVERSION (0x00) 2506 2507 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2508 2509 2510 /**************************************************************************** 2511 * SAS Enclosure Config Pages 2512 ****************************************************************************/ 2513 2514 /* SAS Enclosure Page 0 */ 2515 2516 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2517 { 2518 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2519 U32 Reserved1; /* 0x08 */ 2520 U64 EnclosureLogicalID; /* 0x0C */ 2521 U16 Flags; /* 0x14 */ 2522 U16 EnclosureHandle; /* 0x16 */ 2523 U16 NumSlots; /* 0x18 */ 2524 U16 StartSlot; /* 0x1A */ 2525 U16 Reserved2; /* 0x1C */ 2526 U16 SEPDevHandle; /* 0x1E */ 2527 U32 Reserved3; /* 0x20 */ 2528 U32 Reserved4; /* 0x24 */ 2529 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2530 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2531 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2532 2533 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2534 2535 /* values for SAS Enclosure Page 0 Flags field */ 2536 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2537 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2538 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2539 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2540 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2541 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2542 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2543 2544 2545 /**************************************************************************** 2546 * Log Config Page 2547 ****************************************************************************/ 2548 2549 /* Log Page 0 */ 2550 2551 /* 2552 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2553 * one and check the value returned for NumLogEntries at runtime. 2554 */ 2555 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2556 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2557 #endif 2558 2559 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2560 2561 typedef struct _MPI2_LOG_0_ENTRY 2562 { 2563 U64 TimeStamp; /* 0x00 */ 2564 U32 Reserved1; /* 0x08 */ 2565 U16 LogSequence; /* 0x0C */ 2566 U16 LogEntryQualifier; /* 0x0E */ 2567 U8 VP_ID; /* 0x10 */ 2568 U8 VF_ID; /* 0x11 */ 2569 U16 Reserved2; /* 0x12 */ 2570 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2571 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2572 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2573 2574 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 2575 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2576 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2577 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2578 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2579 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2580 2581 typedef struct _MPI2_CONFIG_PAGE_LOG_0 2582 { 2583 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2584 U32 Reserved1; /* 0x08 */ 2585 U32 Reserved2; /* 0x0C */ 2586 U16 NumLogEntries; /* 0x10 */ 2587 U16 Reserved3; /* 0x12 */ 2588 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2589 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2590 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2591 2592 #define MPI2_LOG_0_PAGEVERSION (0x02) 2593 2594 2595 /**************************************************************************** 2596 * RAID Config Page 2597 ****************************************************************************/ 2598 2599 /* RAID Page 0 */ 2600 2601 /* 2602 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2603 * one and check the value returned for NumElements at runtime. 2604 */ 2605 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2606 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2607 #endif 2608 2609 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2610 { 2611 U16 ElementFlags; /* 0x00 */ 2612 U16 VolDevHandle; /* 0x02 */ 2613 U8 HotSparePool; /* 0x04 */ 2614 U8 PhysDiskNum; /* 0x05 */ 2615 U16 PhysDiskDevHandle; /* 0x06 */ 2616 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2617 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2618 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2619 2620 /* values for the ElementFlags field */ 2621 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2622 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2623 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2624 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2625 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2626 2627 2628 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2629 { 2630 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2631 U8 NumHotSpares; /* 0x08 */ 2632 U8 NumPhysDisks; /* 0x09 */ 2633 U8 NumVolumes; /* 0x0A */ 2634 U8 ConfigNum; /* 0x0B */ 2635 U32 Flags; /* 0x0C */ 2636 U8 ConfigGUID[24]; /* 0x10 */ 2637 U32 Reserved1; /* 0x28 */ 2638 U8 NumElements; /* 0x2C */ 2639 U8 Reserved2; /* 0x2D */ 2640 U16 Reserved3; /* 0x2E */ 2641 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2642 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2643 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2644 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2645 2646 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2647 2648 /* values for RAID Configuration Page 0 Flags field */ 2649 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2650 2651 2652 /**************************************************************************** 2653 * Driver Persistent Mapping Config Pages 2654 ****************************************************************************/ 2655 2656 /* Driver Persistent Mapping Page 0 */ 2657 2658 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2659 { 2660 U64 PhysicalIdentifier; /* 0x00 */ 2661 U16 MappingInformation; /* 0x08 */ 2662 U16 DeviceIndex; /* 0x0A */ 2663 U32 PhysicalBitsMapping; /* 0x0C */ 2664 U32 Reserved1; /* 0x10 */ 2665 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2666 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2667 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2668 2669 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2670 { 2671 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2672 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2673 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2674 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2675 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2676 2677 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2678 2679 /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2680 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2681 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2682 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2683 2684 2685 /**************************************************************************** 2686 * Ethernet Config Pages 2687 ****************************************************************************/ 2688 2689 /* Ethernet Page 0 */ 2690 2691 /* IP address (union of IPv4 and IPv6) */ 2692 typedef union _MPI2_ETHERNET_IP_ADDR { 2693 U32 IPv4Addr; 2694 U32 IPv6Addr[4]; 2695 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 2696 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 2697 2698 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 2699 2700 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 2701 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2702 U8 NumInterfaces; /* 0x08 */ 2703 U8 Reserved0; /* 0x09 */ 2704 U16 Reserved1; /* 0x0A */ 2705 U32 Status; /* 0x0C */ 2706 U8 MediaState; /* 0x10 */ 2707 U8 Reserved2; /* 0x11 */ 2708 U16 Reserved3; /* 0x12 */ 2709 U8 MacAddress[6]; /* 0x14 */ 2710 U8 Reserved4; /* 0x1A */ 2711 U8 Reserved5; /* 0x1B */ 2712 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 2713 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 2714 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 2715 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 2716 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 2717 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 2718 U8 HostName 2719 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2720 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 2721 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 2722 2723 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 2724 2725 /* values for Ethernet Page 0 Status field */ 2726 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 2727 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 2728 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 2729 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 2730 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 2731 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 2732 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 2733 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 2734 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 2735 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 2736 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 2737 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 2738 2739 /* values for Ethernet Page 0 MediaState field */ 2740 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 2741 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 2742 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 2743 2744 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 2745 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 2746 #define MPI2_ETHPG0_MS_10MBIT (0x01) 2747 #define MPI2_ETHPG0_MS_100MBIT (0x02) 2748 #define MPI2_ETHPG0_MS_1GBIT (0x03) 2749 2750 2751 /* Ethernet Page 1 */ 2752 2753 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 2754 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2755 U32 Reserved0; /* 0x08 */ 2756 U32 Flags; /* 0x0C */ 2757 U8 MediaState; /* 0x10 */ 2758 U8 Reserved1; /* 0x11 */ 2759 U16 Reserved2; /* 0x12 */ 2760 U8 MacAddress[6]; /* 0x14 */ 2761 U8 Reserved3; /* 0x1A */ 2762 U8 Reserved4; /* 0x1B */ 2763 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 2764 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 2765 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 2766 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 2767 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 2768 U32 Reserved5; /* 0x6C */ 2769 U32 Reserved6; /* 0x70 */ 2770 U32 Reserved7; /* 0x74 */ 2771 U32 Reserved8; /* 0x78 */ 2772 U8 HostName 2773 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2774 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 2775 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 2776 2777 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 2778 2779 /* values for Ethernet Page 1 Flags field */ 2780 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 2781 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 2782 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 2783 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 2784 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 2785 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 2786 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 2787 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 2788 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 2789 2790 /* values for Ethernet Page 1 MediaState field */ 2791 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 2792 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 2793 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 2794 2795 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 2796 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 2797 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 2798 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 2799 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 2800 2801 2802 #endif 2803 2804