1 /****************************************************************************** 2 * 3 * Name: skdrv2nd.h 4 * Project: GEnesis, PCI Gigabit Ethernet Adapter 5 * Purpose: Second header file for driver and all other modules 6 * 7 ******************************************************************************/ 8 9 /****************************************************************************** 10 * 11 * (C)Copyright 1998-2002 SysKonnect GmbH. 12 * (C)Copyright 2002-2003 Marvell. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * The information in this file is provided "AS IS" without warranty. 20 * 21 ******************************************************************************/ 22 23 /****************************************************************************** 24 * 25 * Description: 26 * 27 * This is the second include file of the driver, which includes all other 28 * neccessary files and defines all structures and constants used by the 29 * driver and the common modules. 30 * 31 * Include File Hierarchy: 32 * 33 * see skge.c 34 * 35 ******************************************************************************/ 36 37 #ifndef __INC_SKDRV2ND_H 38 #define __INC_SKDRV2ND_H 39 40 #include "h/skqueue.h" 41 #include "h/skgehwt.h" 42 #include "h/sktimer.h" 43 #include "h/ski2c.h" 44 #include "h/skgepnmi.h" 45 #include "h/skvpd.h" 46 #include "h/skgehw.h" 47 #include "h/skgeinit.h" 48 #include "h/skaddr.h" 49 #include "h/skgesirq.h" 50 #include "h/skcsum.h" 51 #include "h/skrlmt.h" 52 #include "h/skgedrv.h" 53 54 #define SK_PCI_ISCOMPLIANT(result, pdev) { \ 55 result = SK_FALSE; /* default */ \ 56 /* 3Com (0x10b7) */ \ 57 if (pdev->vendor == 0x10b7) { \ 58 /* Gigabit Ethernet Adapter (0x1700) */ \ 59 if ((pdev->device == 0x1700)) { \ 60 result = SK_TRUE; \ 61 } \ 62 /* SysKonnect (0x1148) */ \ 63 } else if (pdev->vendor == 0x1148) { \ 64 /* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */ \ 65 /* SK-98xx V2.0 Gigabit Ethernet Adapter (0x4320) */ \ 66 if ((pdev->device == 0x4300) || \ 67 (pdev->device == 0x4320)) { \ 68 result = SK_TRUE; \ 69 } \ 70 /* D-Link (0x1186) */ \ 71 } else if (pdev->vendor == 0x1186) { \ 72 /* Gigabit Ethernet Adapter (0x4c00) */ \ 73 if ((pdev->device == 0x4c00)) { \ 74 result = SK_TRUE; \ 75 } \ 76 /* Marvell (0x11ab) */ \ 77 } else if (pdev->vendor == 0x11ab) { \ 78 /* Gigabit Ethernet Adapter (0x4320) */ \ 79 if ((pdev->device == 0x4320)) { \ 80 result = SK_TRUE; \ 81 } \ 82 /* CNet (0x1371) */ \ 83 } else if (pdev->vendor == 0x1371) { \ 84 /* GigaCard Network Adapter (0x434e) */ \ 85 if ((pdev->device == 0x434e)) { \ 86 result = SK_TRUE; \ 87 } \ 88 /* Linksys (0x1737) */ \ 89 } else if (pdev->vendor == 0x1737) { \ 90 /* Gigabit Network Adapter (0x1032) */ \ 91 /* Gigabit Network Adapter (0x1064) */ \ 92 if ((pdev->device == 0x1032) || \ 93 (pdev->device == 0x1064)) { \ 94 result = SK_TRUE; \ 95 } \ 96 } else { \ 97 result = SK_FALSE; \ 98 } \ 99 } 100 101 102 extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned); 103 extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*); 104 extern SK_U64 SkOsGetTime(SK_AC*); 105 extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*); 106 extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*); 107 extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*); 108 extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32); 109 extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16); 110 extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8); 111 extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA); 112 113 #ifdef SK_DIAG_SUPPORT 114 extern int SkDrvEnterDiagMode(SK_AC *pAc); 115 extern int SkDrvLeaveDiagMode(SK_AC *pAc); 116 #endif 117 118 struct s_DrvRlmtMbuf { 119 SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */ 120 SK_U8 *pData; /* Data buffer (virtually contig.). */ 121 unsigned Size; /* Data buffer size. */ 122 unsigned Length; /* Length of packet (<= Size). */ 123 SK_U32 PortIdx; /* Receiving/transmitting port. */ 124 #ifdef SK_RLMT_MBUF_PRIVATE 125 SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */ 126 #endif /* SK_RLMT_MBUF_PRIVATE */ 127 struct sk_buff *pOs; /* Pointer to message block */ 128 }; 129 130 131 /* 132 * Time macros 133 */ 134 #if SK_TICKS_PER_SEC == 100 135 #define SK_PNMI_HUNDREDS_SEC(t) (t) 136 #else 137 #define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \ 138 (SK_TICKS_PER_SEC)) 139 #endif 140 141 /* 142 * New SkOsGetTime 143 */ 144 #define SkOsGetTimeCurrent(pAC, pUsec) {\ 145 struct timeval t;\ 146 do_gettimeofday(&t);\ 147 *pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\ 148 } 149 150 151 /* 152 * ioctl definitions 153 */ 154 #define SK_IOCTL_BASE (SIOCDEVPRIVATE) 155 #define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0) 156 #define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1) 157 #define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2) 158 #define SK_IOCTL_GEN (SK_IOCTL_BASE + 3) 159 #define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4) 160 161 typedef struct s_IOCTL SK_GE_IOCTL; 162 163 struct s_IOCTL { 164 char* pData; 165 unsigned int Len; 166 }; 167 168 169 /* 170 * define sizes of descriptor rings in bytes 171 */ 172 173 #define TX_RING_SIZE (8*1024) 174 #define RX_RING_SIZE (24*1024) 175 176 /* 177 * Buffer size for ethernet packets 178 */ 179 #define ETH_BUF_SIZE 1540 180 #define ETH_MAX_MTU 1514 181 #define ETH_MIN_MTU 60 182 #define ETH_MULTICAST_BIT 0x01 183 #define SK_JUMBO_MTU 9000 184 185 /* 186 * transmit priority selects the queue: LOW=asynchron, HIGH=synchron 187 */ 188 #define TX_PRIO_LOW 0 189 #define TX_PRIO_HIGH 1 190 191 /* 192 * alignment of rx/tx descriptors 193 */ 194 #define DESCR_ALIGN 64 195 196 /* 197 * definitions for pnmi. TODO 198 */ 199 #define SK_DRIVER_RESET(pAC, IoC) 0 200 #define SK_DRIVER_SENDEVENT(pAC, IoC) 0 201 #define SK_DRIVER_SELFTEST(pAC, IoC) 0 202 /* For get mtu you must add an own function */ 203 #define SK_DRIVER_GET_MTU(pAc,IoC,i) 0 204 #define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0 205 #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0 206 207 /* 208 ** Interim definition of SK_DRV_TIMER placed in this file until 209 ** common modules have boon finallized 210 */ 211 #define SK_DRV_TIMER 11 212 #define SK_DRV_MODERATION_TIMER 1 213 #define SK_DRV_MODERATION_TIMER_LENGTH 1000000 /* 1 second */ 214 #define SK_DRV_RX_CLEANUP_TIMER 2 215 #define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000 /* 100 millisecs */ 216 217 /* 218 ** Definitions regarding transmitting frames 219 ** any calculating any checksum. 220 */ 221 #define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6 222 #define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6 223 #define C_LEN_ETHERMAC_HEADER_LENTYPE 2 224 #define C_LEN_ETHERMAC_HEADER ( (C_LEN_ETHERMAC_HEADER_DEST_ADDR) + \ 225 (C_LEN_ETHERMAC_HEADER_SRC_ADDR) + \ 226 (C_LEN_ETHERMAC_HEADER_LENTYPE) ) 227 228 #define C_LEN_ETHERMTU_MINSIZE 46 229 #define C_LEN_ETHERMTU_MAXSIZE_STD 1500 230 #define C_LEN_ETHERMTU_MAXSIZE_JUMBO 9000 231 232 #define C_LEN_ETHERNET_MINSIZE ( (C_LEN_ETHERMAC_HEADER) + \ 233 (C_LEN_ETHERMTU_MINSIZE) ) 234 235 #define C_OFFSET_IPHEADER C_LEN_ETHERMAC_HEADER 236 #define C_OFFSET_IPHEADER_IPPROTO 9 237 #define C_OFFSET_TCPHEADER_TCPCS 16 238 #define C_OFFSET_UDPHEADER_UDPCS 6 239 240 #define C_OFFSET_IPPROTO ( (C_LEN_ETHERMAC_HEADER) + \ 241 (C_OFFSET_IPHEADER_IPPROTO) ) 242 243 #define C_PROTO_ID_UDP 17 /* refer to RFC 790 or Stevens' */ 244 #define C_PROTO_ID_TCP 6 /* TCP/IP illustrated for details */ 245 246 /* TX and RX descriptors *****************************************************/ 247 248 typedef struct s_RxD RXD; /* the receive descriptor */ 249 250 struct s_RxD { 251 volatile SK_U32 RBControl; /* Receive Buffer Control */ 252 SK_U32 VNextRxd; /* Next receive descriptor,low dword */ 253 SK_U32 VDataLow; /* Receive buffer Addr, low dword */ 254 SK_U32 VDataHigh; /* Receive buffer Addr, high dword */ 255 SK_U32 FrameStat; /* Receive Frame Status word */ 256 SK_U32 TimeStamp; /* Time stamp from XMAC */ 257 SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */ 258 SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */ 259 RXD *pNextRxd; /* Pointer to next Rxd */ 260 struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ 261 }; 262 263 typedef struct s_TxD TXD; /* the transmit descriptor */ 264 265 struct s_TxD { 266 volatile SK_U32 TBControl; /* Transmit Buffer Control */ 267 SK_U32 VNextTxd; /* Next transmit descriptor,low dword */ 268 SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */ 269 SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */ 270 SK_U32 FrameStat; /* Transmit Frame Status Word */ 271 SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */ 272 SK_U16 TcpSumSt; /* TCP Sum Start */ 273 SK_U16 TcpSumWr; /* TCP Sum Write */ 274 SK_U32 TcpReserved; /* not used */ 275 TXD *pNextTxd; /* Pointer to next Txd */ 276 struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ 277 }; 278 279 /* Used interrupt bits in the interrupts source register *********************/ 280 281 #define DRIVER_IRQS ((IS_IRQ_SW) | \ 282 (IS_R1_F) |(IS_R2_F) | \ 283 (IS_XS1_F) |(IS_XA1_F) | \ 284 (IS_XS2_F) |(IS_XA2_F)) 285 286 #define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \ 287 (IS_EXT_REG) |(IS_TIMINT) | \ 288 (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \ 289 (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \ 290 (IS_MAC1) |(IS_LNK_SYNC_M1)| \ 291 (IS_MAC2) |(IS_LNK_SYNC_M2)| \ 292 (IS_R1_C) |(IS_R2_C) | \ 293 (IS_XS1_C) |(IS_XA1_C) | \ 294 (IS_XS2_C) |(IS_XA2_C)) 295 296 #define IRQ_MASK ((IS_IRQ_SW) | \ 297 (IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \ 298 (IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \ 299 (IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \ 300 (IS_HW_ERR) |(IS_I2C_READY)| \ 301 (IS_EXT_REG) |(IS_TIMINT) | \ 302 (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \ 303 (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \ 304 (IS_MAC1) |(IS_MAC2) | \ 305 (IS_R1_C) |(IS_R2_C) | \ 306 (IS_XS1_C) |(IS_XA1_C) | \ 307 (IS_XS2_C) |(IS_XA2_C)) 308 309 #define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */ 310 311 typedef struct s_DevNet DEV_NET; 312 313 struct s_DevNet { 314 struct proc_dir_entry *proc; 315 int PortNr; 316 int NetNr; 317 int Mtu; 318 int Up; 319 SK_AC *pAC; 320 }; 321 322 typedef struct s_TxPort TX_PORT; 323 324 struct s_TxPort { 325 /* the transmit descriptor rings */ 326 caddr_t pTxDescrRing; /* descriptor area memory */ 327 SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */ 328 TXD *pTxdRingHead; /* Head of Tx rings */ 329 TXD *pTxdRingTail; /* Tail of Tx rings */ 330 TXD *pTxdRingPrev; /* descriptor sent previously */ 331 int TxdRingFree; /* # of free entrys */ 332 spinlock_t TxDesRingLock; /* serialize descriptor accesses */ 333 caddr_t HwAddr; /* bmu registers address */ 334 int PortIndex; /* index number of port (0 or 1) */ 335 }; 336 337 typedef struct s_RxPort RX_PORT; 338 339 struct s_RxPort { 340 /* the receive descriptor rings */ 341 caddr_t pRxDescrRing; /* descriptor area memory */ 342 SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */ 343 RXD *pRxdRingHead; /* Head of Rx rings */ 344 RXD *pRxdRingTail; /* Tail of Rx rings */ 345 RXD *pRxdRingPrev; /* descriptor given to BMU previously */ 346 int RxdRingFree; /* # of free entrys */ 347 spinlock_t RxDesRingLock; /* serialize descriptor accesses */ 348 int RxFillLimit; /* limit for buffers in ring */ 349 caddr_t HwAddr; /* bmu registers address */ 350 int PortIndex; /* index number of port (0 or 1) */ 351 }; 352 353 /* Definitions needed for interrupt moderation *******************************/ 354 355 #define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F)) 356 #define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F)) 357 #define IRQ_MASK_TX_ONLY ((IRQ_EOF_AS_TX)| (IRQ_EOF_SY_TX)) 358 #define IRQ_MASK_RX_ONLY ((IS_R1_F) | (IS_R2_F)) 359 #define IRQ_MASK_SP_ONLY (SPECIAL_IRQS) 360 #define IRQ_MASK_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY)) 361 #define IRQ_MASK_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY)) 362 #define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY)) 363 #define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX)) 364 365 #define C_INT_MOD_NONE 1 366 #define C_INT_MOD_STATIC 2 367 #define C_INT_MOD_DYNAMIC 4 368 369 #define C_CLK_FREQ_GENESIS 53215000 /* shorter: 53.125 MHz */ 370 #define C_CLK_FREQ_YUKON 78215000 /* shorter: 78.125 MHz */ 371 372 #define C_INTS_PER_SEC_DEFAULT 2000 373 #define C_INT_MOD_ENABLE_PERCENTAGE 50 /* if higher 50% enable */ 374 #define C_INT_MOD_DISABLE_PERCENTAGE 50 /* if lower 50% disable */ 375 #define C_INT_MOD_IPS_LOWER_RANGE 30 376 #define C_INT_MOD_IPS_UPPER_RANGE 40000 377 378 379 typedef struct s_DynIrqModInfo DIM_INFO; 380 struct s_DynIrqModInfo { 381 unsigned long PrevTimeVal; 382 unsigned int PrevSysLoad; 383 unsigned int PrevUsedTime; 384 unsigned int PrevTotalTime; 385 int PrevUsedDescrRatio; 386 int NbrProcessedDescr; 387 SK_U64 PrevPort0RxIntrCts; 388 SK_U64 PrevPort1RxIntrCts; 389 SK_U64 PrevPort0TxIntrCts; 390 SK_U64 PrevPort1TxIntrCts; 391 SK_BOOL ModJustEnabled; /* Moderation just enabled yes/no */ 392 393 int MaxModIntsPerSec; /* Moderation Threshold */ 394 int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */ 395 int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */ 396 397 long MaskIrqModeration; /* ModIrqType (eg. 'TxRx') */ 398 SK_BOOL DisplayStats; /* Stats yes/no */ 399 SK_BOOL AutoSizing; /* Resize DIM-timer on/off */ 400 int IntModTypeSelect; /* EnableIntMod (eg. 'dynamic') */ 401 402 SK_TIMER ModTimer; /* just some timer */ 403 }; 404 405 typedef struct s_PerStrm PER_STRM; 406 407 #define SK_ALLOC_IRQ 0x00000001 408 409 #ifdef SK_DIAG_SUPPORT 410 #define DIAG_ACTIVE 1 411 #define DIAG_NOTACTIVE 0 412 #endif 413 414 /**************************************************************************** 415 * Per board structure / Adapter Context structure: 416 * Allocated within attach(9e) and freed within detach(9e). 417 * Contains all 'per device' necessary handles, flags, locks etc.: 418 */ 419 struct s_AC { 420 SK_GEINIT GIni; /* GE init struct */ 421 SK_PNMI Pnmi; /* PNMI data struct */ 422 SK_VPD vpd; /* vpd data struct */ 423 SK_QUEUE Event; /* Event queue */ 424 SK_HWT Hwt; /* Hardware Timer control struct */ 425 SK_TIMCTRL Tim; /* Software Timer control struct */ 426 SK_I2C I2c; /* I2C relevant data structure */ 427 SK_ADDR Addr; /* for Address module */ 428 SK_CSUM Csum; /* for checksum module */ 429 SK_RLMT Rlmt; /* for rlmt module */ 430 spinlock_t SlowPathLock; /* Normal IRQ lock */ 431 SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */ 432 int RlmtMode; /* link check mode to set */ 433 int RlmtNets; /* Number of nets */ 434 435 SK_IOC IoBase; /* register set of adapter */ 436 int BoardLevel; /* level of active hw init (0-2) */ 437 char DeviceStr[80]; /* adapter string from vpd */ 438 SK_U32 AllocFlag; /* flag allocation of resources */ 439 struct pci_dev *PciDev; /* for access to pci config space */ 440 SK_U32 PciDevId; /* pci device id */ 441 struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */ 442 char Name[30]; /* driver name */ 443 struct SK_NET_DEVICE *Next; /* link all devices (for clearing) */ 444 int RxBufSize; /* length of receive buffers */ 445 struct net_device_stats stats; /* linux 'netstat -i' statistics */ 446 int Index; /* internal board index number */ 447 448 /* adapter RAM sizes for queues of active port */ 449 int RxQueueSize; /* memory used for receive queue */ 450 int TxSQueueSize; /* memory used for sync. tx queue */ 451 int TxAQueueSize; /* memory used for async. tx queue */ 452 453 int PromiscCount; /* promiscuous mode counter */ 454 int AllMultiCount; /* allmulticast mode counter */ 455 int MulticCount; /* number of different MC */ 456 /* addresses for this board */ 457 /* (may be more than HW can)*/ 458 459 int HWRevision; /* Hardware revision */ 460 int ActivePort; /* the active XMAC port */ 461 int MaxPorts; /* number of activated ports */ 462 int TxDescrPerRing; /* # of descriptors per tx ring */ 463 int RxDescrPerRing; /* # of descriptors per rx ring */ 464 465 caddr_t pDescrMem; /* Pointer to the descriptor area */ 466 dma_addr_t pDescrMemDMA; /* PCI DMA address of area */ 467 468 /* the port structures with descriptor rings */ 469 TX_PORT TxPort[SK_MAX_MACS][2]; 470 RX_PORT RxPort[SK_MAX_MACS]; 471 472 unsigned int CsOfs1; /* for checksum calculation */ 473 unsigned int CsOfs2; /* for checksum calculation */ 474 SK_U32 CsOfs; /* for checksum calculation */ 475 476 SK_BOOL CheckQueue; /* check event queue soon */ 477 SK_TIMER DrvCleanupTimer;/* to check for pending descriptors */ 478 DIM_INFO DynIrqModInfo; /* all data related to DIM */ 479 480 /* Only for tests */ 481 int PortUp; 482 int PortDown; 483 int ChipsetType; /* Chipset family type 484 * 0 == Genesis family support 485 * 1 == Yukon family support 486 */ 487 #ifdef SK_DIAG_SUPPORT 488 SK_U32 DiagModeActive; /* is diag active? */ 489 SK_BOOL DiagFlowCtrl; /* for control purposes */ 490 SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for all Pnmi-Data */ 491 SK_BOOL WasIfUp[SK_MAX_MACS]; /* for OpenClose while 492 * DIAG is busy with NIC 493 */ 494 #endif 495 496 }; 497 498 499 #endif /* __INC_SKDRV2ND_H */ 500 501