1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
4 *
5 * (c) 1998,1999,2000,2001 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 */
8 #ifndef __MATROXFB_H__
9 #define __MATROXFB_H__
10
11 /* general, but fairly heavy, debugging */
12 #undef MATROXFB_DEBUG
13
14 /* heavy debugging: */
15 /* -- logs putc[s], so everytime a char is displayed, it's logged */
16 #undef MATROXFB_DEBUG_HEAVY
17
18 /* This one _could_ cause infinite loops */
19 /* It _does_ cause lots and lots of messages during idle loops */
20 #undef MATROXFB_DEBUG_LOOP
21
22 /* Debug register calls, too? */
23 #undef MATROXFB_DEBUG_REG
24
25 /* Guard accelerator accesses with spin_lock_irqsave... */
26 #undef MATROXFB_USE_SPINLOCKS
27
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/errno.h>
32 #include <linux/string.h>
33 #include <linux/mm.h>
34 #include <linux/tty.h>
35 #include <linux/slab.h>
36 #include <linux/delay.h>
37 #include <linux/fb.h>
38 #include <linux/console.h>
39 #include <linux/selection.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/timer.h>
43 #include <linux/pci.h>
44 #include <linux/spinlock.h>
45
46 #include <asm/io.h>
47 #include <asm/unaligned.h>
48 #ifdef CONFIG_MTRR
49 #include <asm/mtrr.h>
50 #endif
51
52 #include <video/fbcon.h>
53 #include <video/fbcon-cfb4.h>
54 #include <video/fbcon-cfb8.h>
55 #include <video/fbcon-cfb16.h>
56 #include <video/fbcon-cfb24.h>
57 #include <video/fbcon-cfb32.h>
58
59 #if defined(CONFIG_FB_COMPAT_XPMAC)
60 #include <asm/vc_ioctl.h>
61 #endif
62 #if defined(CONFIG_PPC)
63 #include <asm/prom.h>
64 #include <asm/pci-bridge.h>
65 #include <video/macmodes.h>
66 #endif
67
68 /* always compile support for 32MB... It cost almost nothing */
69 #define CONFIG_FB_MATROX_32MB
70
71 #define FBCON_HAS_VGATEXT
72
73 #ifdef MATROXFB_DEBUG
74
75 #define DEBUG
76 #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
77
78 #ifdef MATROXFB_DEBUG_HEAVY
79 #define DBG_HEAVY(x) DBG(x)
80 #else /* MATROXFB_DEBUG_HEAVY */
81 #define DBG_HEAVY(x) /* DBG_HEAVY */
82 #endif /* MATROXFB_DEBUG_HEAVY */
83
84 #ifdef MATROXFB_DEBUG_LOOP
85 #define DBG_LOOP(x) DBG(x)
86 #else /* MATROXFB_DEBUG_LOOP */
87 #define DBG_LOOP(x) /* DBG_LOOP */
88 #endif /* MATROXFB_DEBUG_LOOP */
89
90 #ifdef MATROXFB_DEBUG_REG
91 #define DBG_REG(x) DBG(x)
92 #else /* MATROXFB_DEBUG_REG */
93 #define DBG_REG(x) /* DBG_REG */
94 #endif /* MATROXFB_DEBUG_REG */
95
96 #else /* MATROXFB_DEBUG */
97
98 #define DBG(x) /* DBG */
99 #define DBG_HEAVY(x) /* DBG_HEAVY */
100 #define DBG_REG(x) /* DBG_REG */
101 #define DBG_LOOP(x) /* DBG_LOOP */
102
103 #endif /* MATROXFB_DEBUG */
104
105 #if !defined(__i386__) && !defined(__x86_64__)
106 #ifndef ioremap_nocache
107 #define ioremap_nocache(X,Y) ioremap(X,Y)
108 #endif
109 #endif
110
111 #if defined(__alpha__) || defined(__mc68000__)
112 #define READx_WORKS
113 #define MEMCPYTOIO_WORKS
114 #elif defined(__powerpc64__)
115 #define RAW_READx_WORKS
116 #define MEMCPYTOIO_WORKS
117 #else
118 #define READx_FAILS
119 /* recheck __ppc__, maybe that __ppc__ needs MEMCPYTOIO_WRITEL */
120 /* I benchmarked PII/350MHz with G200... MEMCPY, MEMCPYTOIO and WRITEL are on same speed ( <2% diff) */
121 /* so that means that G200 speed (or AGP speed?) is our limit... I do not have benchmark to test, how */
122 /* much of PCI bandwidth is used during transfers... */
123 #if defined(__i386__) || defined(__x86_64__)
124 #define MEMCPYTOIO_MEMCPY
125 #else
126 #define MEMCPYTOIO_WRITEL
127 #endif
128 #endif
129
130 #if defined(__mc68000__)
131 #define MAP_BUSTOVIRT
132 #else
133 #define MAP_IOREMAP
134 #endif
135
136 #ifdef DEBUG
137 #define dprintk(X...) printk(X)
138 #else
139 #define dprintk(X...)
140 #endif
141
142 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
143 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
144 #endif
145 #ifndef PCI_SS_VENDOR_ID_MATROX
146 #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
147 #endif
148
149 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
150 #define PCI_SS_ID_MATROX_GENERIC 0xFF00
151 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
152 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
153 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
154 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
155 #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
156 #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
157 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
158 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
159 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
160 #endif
161
162 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
163 #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
164 #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
165
166 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
167
168 /* G-series and Mystique have (almost) same DAC */
169 #undef NEED_DAC1064
170 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G100)
171 #define NEED_DAC1064 1
172 #endif
173
174 typedef struct {
175 u_int8_t* vaddr;
176 } vaddr_t;
177
178 #ifdef READx_WORKS
mga_readb(vaddr_t va,unsigned int offs)179 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
180 return readb(va.vaddr + offs);
181 }
182
mga_readw(vaddr_t va,unsigned int offs)183 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
184 return readw(va.vaddr + offs);
185 }
186
mga_readl(vaddr_t va,unsigned int offs)187 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
188 return readl(va.vaddr + offs);
189 }
190
mga_writeb(vaddr_t va,unsigned int offs,u_int8_t value)191 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
192 writeb(value, va.vaddr + offs);
193 }
194
mga_writew(vaddr_t va,unsigned int offs,u_int16_t value)195 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
196 writew(value, va.vaddr + offs);
197 }
198
mga_writel(vaddr_t va,unsigned int offs,u_int32_t value)199 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
200 writel(value, va.vaddr + offs);
201 }
202 #elif defined(RAW_READx_WORKS)
mga_readb(vaddr_t va,unsigned int offs)203 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
204 return __raw_readb(va.vaddr + offs);
205 }
206
mga_readw(vaddr_t va,unsigned int offs)207 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
208 return __raw_readw(va.vaddr + offs);
209 }
210
mga_readl(vaddr_t va,unsigned int offs)211 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
212 return __raw_readl(va.vaddr + offs);
213 }
214
mga_writeb(vaddr_t va,unsigned int offs,u_int8_t value)215 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
216 __raw_writeb(value, va.vaddr + offs);
217 }
218
mga_writew(vaddr_t va,unsigned int offs,u_int16_t value)219 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
220 __raw_writew(value, va.vaddr + offs);
221 }
222
mga_writel(vaddr_t va,unsigned int offs,u_int32_t value)223 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
224 __raw_writel(value, va.vaddr + offs);
225 }
226 #else
mga_readb(vaddr_t va,unsigned int offs)227 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
228 return *(volatile u_int8_t*)(va.vaddr + offs);
229 }
230
mga_readw(vaddr_t va,unsigned int offs)231 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
232 return *(volatile u_int16_t*)(va.vaddr + offs);
233 }
234
mga_readl(vaddr_t va,unsigned int offs)235 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
236 return *(volatile u_int32_t*)(va.vaddr + offs);
237 }
238
mga_writeb(vaddr_t va,unsigned int offs,u_int8_t value)239 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
240 *(volatile u_int8_t*)(va.vaddr + offs) = value;
241 }
242
mga_writew(vaddr_t va,unsigned int offs,u_int16_t value)243 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
244 *(volatile u_int16_t*)(va.vaddr + offs) = value;
245 }
246
mga_writel(vaddr_t va,unsigned int offs,u_int32_t value)247 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
248 *(volatile u_int32_t*)(va.vaddr + offs) = value;
249 }
250 #endif
251
mga_memcpy_toio(vaddr_t va,unsigned int offs,const void * src,int len)252 static inline void mga_memcpy_toio(vaddr_t va, unsigned int offs, const void* src, int len) {
253 #ifdef MEMCPYTOIO_WORKS
254 memcpy_toio(va.vaddr + offs, src, len);
255 #elif defined(MEMCPYTOIO_WRITEL)
256 if (offs & 3) {
257 while (len >= 4) {
258 mga_writel(va, offs, get_unaligned((u32 *)src));
259 offs += 4;
260 len -= 4;
261 src += 4;
262 }
263 } else {
264 while (len >= 4) {
265 mga_writel(va, offs, *(u32 *)src);
266 offs += 4;
267 len -= 4;
268 src += 4;
269 }
270 }
271 if (len) {
272 u_int32_t tmp;
273
274 memcpy(&tmp, src, len);
275 mga_writel(va, offs, tmp);
276 }
277 #elif defined(MEMCPYTOIO_MEMCPY)
278 memcpy(va.vaddr + offs, src, len);
279 #else
280 #error "Sorry, do not know how to write block of data to device"
281 #endif
282 }
283
vaddr_add(vaddr_t * va,unsigned long offs)284 static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
285 va->vaddr += offs;
286 }
287
vaddr_va(vaddr_t va)288 static inline void* vaddr_va(vaddr_t va) {
289 return va.vaddr;
290 }
291
292 #define MGA_IOREMAP_NORMAL 0
293 #define MGA_IOREMAP_NOCACHE 1
294
295 #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
296 #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
mga_ioremap(unsigned long phys,unsigned long size,int flags,vaddr_t * virt)297 static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
298 #ifdef MAP_IOREMAP
299 if (flags & MGA_IOREMAP_NOCACHE)
300 virt->vaddr = ioremap_nocache(phys, size);
301 else
302 virt->vaddr = ioremap(phys, size);
303 #else
304 #ifdef MAP_BUSTOVIRT
305 virt->vaddr = bus_to_virt(phys);
306 #else
307 #error "Your architecture does not have neither ioremap nor bus_to_virt... Giving up"
308 #endif
309 #endif
310 return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */
311 }
312
mga_iounmap(vaddr_t va)313 static inline void mga_iounmap(vaddr_t va) {
314 #ifdef MAP_IOREMAP
315 iounmap(va.vaddr);
316 #endif
317 }
318
319 struct my_timming {
320 unsigned int pixclock;
321 int mnp;
322 unsigned int crtc;
323 unsigned int HDisplay;
324 unsigned int HSyncStart;
325 unsigned int HSyncEnd;
326 unsigned int HTotal;
327 unsigned int VDisplay;
328 unsigned int VSyncStart;
329 unsigned int VSyncEnd;
330 unsigned int VTotal;
331 unsigned int sync;
332 int dblscan;
333 int interlaced;
334 unsigned int delay; /* CRTC delay */
335 };
336
337 enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
338
339 struct matrox_pll_cache {
340 unsigned int valid;
341 struct {
342 unsigned int mnp_key;
343 unsigned int mnp_value;
344 } data[4];
345 };
346
347 struct matrox_pll_limits {
348 unsigned int vcomin;
349 unsigned int vcomax;
350 };
351
352 struct matrox_pll_features {
353 unsigned int vco_freq_min;
354 unsigned int ref_freq;
355 unsigned int feed_div_min;
356 unsigned int feed_div_max;
357 unsigned int in_div_min;
358 unsigned int in_div_max;
359 unsigned int post_shift_max;
360 };
361
362 struct matroxfb_par
363 {
364 unsigned int final_bppShift;
365 unsigned int cmap_len;
366 struct {
367 unsigned int bytes;
368 unsigned int pixels;
369 unsigned int chunks;
370 } ydstorg;
371 void (*putc)(u_int32_t, u_int32_t, struct display*, int, int, int);
372 void (*putcs)(u_int32_t, u_int32_t, struct display*, const unsigned short*, int, int, int);
373 };
374
375 struct matrox_fb_info;
376
377 struct matrox_DAC1064_features {
378 u_int8_t xvrefctrl;
379 u_int8_t xmiscctrl;
380 unsigned int cursorimage;
381 };
382
383 struct matrox_accel_features {
384 int has_cacheflush;
385 };
386
387 /* current hardware status */
388 struct mavenregs {
389 u_int8_t regs[256];
390 int mode;
391 int vlines;
392 int xtal;
393 int fv;
394
395 u_int16_t htotal;
396 u_int16_t hcorr;
397 };
398
399 struct matrox_crtc2 {
400 u_int32_t ctl, hparam, hsync, vparam, vsync, preload, datactl;
401 };
402
403 struct matrox_hw_state {
404 u_int32_t MXoptionReg;
405 unsigned char DACclk[6];
406 unsigned char DACreg[80];
407 unsigned char MiscOutReg;
408 unsigned char DACpal[768];
409 unsigned char CRTC[25];
410 unsigned char CRTCEXT[9];
411 unsigned char SEQ[5];
412 /* unused for MGA mode, but who knows... */
413 unsigned char GCTL[9];
414 /* unused for MGA mode, but who knows... */
415 unsigned char ATTR[21];
416
417 /* TVOut only */
418 struct mavenregs maven;
419
420 struct matrox_crtc2 crtc2;
421 };
422
423 struct matrox_accel_data {
424 #ifdef CONFIG_FB_MATROX_MILLENIUM
425 unsigned char ramdac_rev;
426 #endif
427 u_int32_t m_dwg_rect;
428 u_int32_t m_opmode;
429 };
430
431 struct matroxfb_queryctrl;
432 struct matroxfb_control;
433
434 struct matrox_altout {
435 struct module *owner;
436 const char *name;
437 int (*compute)(void* altout_dev, struct my_timming* input);
438 int (*program)(void* altout_dev);
439 int (*start)(void* altout_dev);
440 int (*verifymode)(void* altout_dev, u_int32_t mode);
441 int (*getqueryctrl)(void* altout_dev,
442 struct matroxfb_queryctrl* ctrl);
443 int (*getctrl)(void* altout_dev,
444 struct matroxfb_control* ctrl);
445 int (*setctrl)(void* altout_dev,
446 struct matroxfb_control* ctrl);
447 };
448
449 #define MATROXFB_SRC_NONE 0
450 #define MATROXFB_SRC_CRTC1 1
451 #define MATROXFB_SRC_CRTC2 2
452
453 enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
454
455 struct matrox_bios {
456 unsigned int bios_valid : 1;
457 unsigned int pins_len;
458 unsigned char pins[128];
459 struct {
460 unsigned char vMaj, vMin, vRev;
461 } version;
462 struct {
463 unsigned char state, tvout;
464 } output;
465 };
466
467 struct matrox_switch;
468 struct matroxfb_driver;
469 struct matroxfb_dh_fb_info;
470
471 struct matrox_vsync {
472 wait_queue_head_t wait;
473 unsigned int cnt;
474 };
475
476 struct matrox_fb_info {
477 struct fb_info fbcon;
478
479 struct list_head next_fb;
480
481 int dead;
482 unsigned int usecount;
483
484 unsigned int userusecount;
485 unsigned long irq_flags;
486
487 struct matroxfb_par curr;
488 struct matrox_hw_state hw;
489
490 struct matrox_accel_data accel;
491
492 struct pci_dev* pcidev;
493
494 struct {
495 struct rw_semaphore lock;
496 struct {
497 int brightness, contrast, saturation, hue, gamma;
498 int testout, deflicker;
499 } tvo_params;
500 } altout;
501 #define MATROXFB_MAX_OUTPUTS 3
502 struct {
503 unsigned int src;
504 struct matrox_altout* output;
505 void* data;
506 unsigned int mode;
507 } outputs[MATROXFB_MAX_OUTPUTS];
508 #define MATROXFB_MAX_FB_DRIVERS 5
509 struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
510 void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
511 unsigned int drivers_count;
512
513 struct {
514 unsigned long base; /* physical */
515 vaddr_t vbase; /* CPU view */
516 unsigned int len;
517 unsigned int len_usable;
518 unsigned int len_maximum;
519 } video;
520
521 struct {
522 unsigned long base; /* physical */
523 vaddr_t vbase; /* CPU view */
524 unsigned int len;
525 } mmio;
526
527 unsigned int max_pixel_clock;
528
529 struct matrox_switch* hw_switch;
530 int currcon;
531 struct display* currcon_display;
532
533 struct {
534 struct matrox_pll_features pll;
535 struct matrox_DAC1064_features DAC1064;
536 struct matrox_accel_features accel;
537 } features;
538 struct {
539 spinlock_t DAC;
540 spinlock_t accel;
541 } lock;
542
543 enum mga_chip chip;
544
545 int interleave;
546 int millenium;
547 int milleniumII;
548 struct {
549 int cfb4;
550 const int* vxres;
551 int cross4MB;
552 int text;
553 int plnwt;
554 int srcorg;
555 } capable;
556 struct {
557 unsigned int size;
558 unsigned int mgabase;
559 vaddr_t vbase;
560 } fastfont;
561 #ifdef CONFIG_MTRR
562 struct {
563 int vram;
564 int vram_valid;
565 } mtrr;
566 #endif
567 struct {
568 int precise_width;
569 int mga_24bpp_fix;
570 int novga;
571 int nobios;
572 int nopciretry;
573 int noinit;
574 int inverse;
575 int hwcursor;
576 int blink;
577 int sgram;
578 #ifdef CONFIG_FB_MATROX_32MB
579 int support32MB;
580 #endif
581
582 int accelerator;
583 int text_type_aux;
584 int video64bits;
585 int crtc2;
586 int maven_capable;
587 unsigned int vgastep;
588 unsigned int textmode;
589 unsigned int textstep;
590 unsigned int textvram; /* character cells */
591 unsigned int ydstorg; /* offset in bytes from video start to usable memory */
592 /* 0 except for 6MB Millenium */
593 int memtype;
594 int g450dac;
595 int dfp_type;
596 int panellink; /* G400 DFP possible (not G450/G550) */
597 int dualhead;
598 unsigned int fbResource;
599 } devflags;
600 struct display_switch dispsw;
601 struct {
602 int x;
603 int y;
604 unsigned int w;
605 unsigned int u;
606 unsigned int d;
607 unsigned int type;
608 int state;
609 int redraw;
610 struct timer_list timer;
611 } cursor;
612 struct matrox_bios bios;
613 struct {
614 struct matrox_vsync vsync;
615 int panpos;
616 unsigned int pixclock;
617 int mnp;
618 } crtc1;
619 struct {
620 struct matrox_vsync vsync;
621 unsigned int pixclock;
622 int mnp;
623 struct matroxfb_dh_fb_info* info;
624 struct rw_semaphore lock;
625 } crtc2;
626 struct {
627 struct matrox_pll_limits pixel;
628 struct matrox_pll_limits system;
629 struct matrox_pll_limits video;
630 } limits;
631 struct {
632 struct matrox_pll_cache pixel;
633 struct matrox_pll_cache system;
634 struct matrox_pll_cache video;
635 } cache;
636 struct {
637 struct {
638 unsigned int video;
639 unsigned int system;
640 } pll;
641 struct {
642 u_int32_t opt;
643 u_int32_t opt2;
644 u_int32_t opt3;
645 u_int32_t mctlwtst;
646 u_int32_t mctlwtst_core;
647 u_int32_t memmisc;
648 u_int32_t memrdbk;
649 u_int32_t maccess;
650 } reg;
651 struct {
652 unsigned int ddr:1,
653 emrswen:1,
654 dll:1;
655 } memory;
656 } values;
657 struct { unsigned red, green, blue, transp; } palette[256];
658 #if defined(CONFIG_FB_COMPAT_XPMAC)
659 char matrox_name[32];
660 #endif
661 /* These ifdefs must be last! They differ for module & non-module compiles */
662 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB24) || defined(FBCON_HAS_CFB32)
663 union {
664 #ifdef FBCON_HAS_CFB16
665 u_int16_t cfb16[16];
666 #endif
667 #ifdef FBCON_HAS_CFB24
668 u_int32_t cfb24[16];
669 #endif
670 #ifdef FBCON_HAS_CFB32
671 u_int32_t cfb32[16];
672 #endif
673 } cmap;
674 #endif
675 };
676
677 #define info2minfo(info) list_entry(info, struct matrox_fb_info, fbcon)
678
679 #ifdef CONFIG_FB_MATROX_MULTIHEAD
680 #define ACCESS_FBINFO2(info, x) (info->x)
681 #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
682
683 #define MINFO minfo
684
685 #define WPMINFO2 struct matrox_fb_info* minfo
686 #define WPMINFO WPMINFO2 ,
687 #define CPMINFO2 const struct matrox_fb_info* minfo
688 #define CPMINFO CPMINFO2 ,
689 #define PMINFO2 minfo
690 #define PMINFO PMINFO2 ,
691
mxinfo(const struct display * p)692 static inline struct matrox_fb_info* mxinfo(const struct display* p) {
693 return info2minfo(p->fb_info);
694 }
695
696 #define PMXINFO(p) mxinfo(p),
697 #define MINFO_FROM(x) struct matrox_fb_info* minfo = x
698
699 #else
700
701 extern struct matrox_fb_info matroxfb_global_mxinfo;
702
703 #define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x)
704 #define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x)
705
706 #define MINFO (&matroxfb_global_mxinfo)
707
708 #define WPMINFO2 void
709 #define WPMINFO
710 #define CPMINFO2 void
711 #define CPMINFO
712 #define PMINFO2
713 #define PMINFO
714
715 #define PMXINFO(p)
716 #define MINFO_FROM(x)
717
718 #endif
719
720 #define MINFO_FROM_DISP(x) MINFO_FROM(mxinfo(x))
721 #define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x))
722
723 struct matrox_switch {
724 int (*preinit)(WPMINFO2);
725 void (*reset)(WPMINFO2);
726 int (*init)(WPMINFO struct my_timming*, struct display*);
727 void (*restore)(WPMINFO struct display*);
728 int (*selhwcursor)(WPMINFO struct display*);
729 };
730
731 struct matroxfb_driver {
732 struct list_head node;
733 char* name;
734 void* (*probe)(struct matrox_fb_info* info);
735 void (*remove)(struct matrox_fb_info* info, void* data);
736 };
737
738 int matroxfb_register_driver(struct matroxfb_driver* drv);
739 void matroxfb_unregister_driver(struct matroxfb_driver* drv);
740
741 #define PCI_OPTION_REG 0x40
742 #define PCI_OPTION_ENABLE_ROM 0x40000000
743
744 #define PCI_MGA_INDEX 0x44
745 #define PCI_MGA_DATA 0x48
746 #define PCI_OPTION2_REG 0x50
747 #define PCI_OPTION3_REG 0x54
748 #define PCI_MEMMISC_REG 0x58
749
750 #define M_DWGCTL 0x1C00
751 #define M_MACCESS 0x1C04
752 #define M_CTLWTST 0x1C08
753
754 #define M_PLNWT 0x1C1C
755
756 #define M_BCOL 0x1C20
757 #define M_FCOL 0x1C24
758
759 #define M_SGN 0x1C58
760 #define M_LEN 0x1C5C
761 #define M_AR0 0x1C60
762 #define M_AR1 0x1C64
763 #define M_AR2 0x1C68
764 #define M_AR3 0x1C6C
765 #define M_AR4 0x1C70
766 #define M_AR5 0x1C74
767 #define M_AR6 0x1C78
768
769 #define M_CXBNDRY 0x1C80
770 #define M_FXBNDRY 0x1C84
771 #define M_YDSTLEN 0x1C88
772 #define M_PITCH 0x1C8C
773 #define M_YDST 0x1C90
774 #define M_YDSTORG 0x1C94
775 #define M_YTOP 0x1C98
776 #define M_YBOT 0x1C9C
777
778 /* mystique only */
779 #define M_CACHEFLUSH 0x1FFF
780
781 #define M_EXEC 0x0100
782
783 #define M_DWG_TRAP 0x04
784 #define M_DWG_BITBLT 0x08
785 #define M_DWG_ILOAD 0x09
786
787 #define M_DWG_LINEAR 0x0080
788 #define M_DWG_SOLID 0x0800
789 #define M_DWG_ARZERO 0x1000
790 #define M_DWG_SGNZERO 0x2000
791 #define M_DWG_SHIFTZERO 0x4000
792
793 #define M_DWG_REPLACE 0x000C0000
794 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
795 #define M_DWG_XOR 0x00060010
796
797 #define M_DWG_BFCOL 0x04000000
798 #define M_DWG_BMONOWF 0x08000000
799
800 #define M_DWG_TRANSC 0x40000000
801
802 #define M_FIFOSTATUS 0x1E10
803 #define M_STATUS 0x1E14
804 #define M_ICLEAR 0x1E18
805 #define M_IEN 0x1E1C
806
807 #define M_VCOUNT 0x1E20
808
809 #define M_RESET 0x1E40
810 #define M_MEMRDBK 0x1E44
811
812 #define M_AGP2PLL 0x1E4C
813
814 #define M_OPMODE 0x1E54
815 #define M_OPMODE_DMA_GEN_WRITE 0x00
816 #define M_OPMODE_DMA_BLIT 0x04
817 #define M_OPMODE_DMA_VECTOR_WRITE 0x08
818 #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
819 #define M_OPMODE_DMA_BE_8BPP 0x0000
820 #define M_OPMODE_DMA_BE_16BPP 0x0100
821 #define M_OPMODE_DMA_BE_32BPP 0x0200
822 #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
823 #define M_OPMODE_DIR_BE_8BPP 0x000000
824 #define M_OPMODE_DIR_BE_16BPP 0x010000
825 #define M_OPMODE_DIR_BE_32BPP 0x020000
826
827 #define M_ATTR_INDEX 0x1FC0
828 #define M_ATTR_DATA 0x1FC1
829
830 #define M_MISC_REG 0x1FC2
831 #define M_3C2_RD 0x1FC2
832
833 #define M_SEQ_INDEX 0x1FC4
834 #define M_SEQ_DATA 0x1FC5
835
836 #define M_MISC_REG_READ 0x1FCC
837
838 #define M_GRAPHICS_INDEX 0x1FCE
839 #define M_GRAPHICS_DATA 0x1FCF
840
841 #define M_CRTC_INDEX 0x1FD4
842
843 #define M_ATTR_RESET 0x1FDA
844 #define M_3DA_WR 0x1FDA
845 #define M_INSTS1 0x1FDA
846
847 #define M_EXTVGA_INDEX 0x1FDE
848 #define M_EXTVGA_DATA 0x1FDF
849
850 /* G200 only */
851 #define M_SRCORG 0x2CB4
852 #define M_DSTORG 0x2CB8
853
854 #define M_RAMDAC_BASE 0x3C00
855
856 /* fortunately, same on TVP3026 and MGA1064 */
857 #define M_DAC_REG (M_RAMDAC_BASE+0)
858 #define M_DAC_VAL (M_RAMDAC_BASE+1)
859 #define M_PALETTE_MASK (M_RAMDAC_BASE+2)
860
861 #define M_X_INDEX 0x00
862 #define M_X_DATAREG 0x0A
863
864 #define DAC_XGENIOCTRL 0x2A
865 #define DAC_XGENIODATA 0x2B
866
867 #define M_C2CTL 0x3E10
868
869 #ifdef __LITTLE_ENDIAN
870 #define MX_OPTION_BSWAP 0x00000000
871
872 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
873 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
874 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
875 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
876 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
877 #else
878 #ifdef __BIG_ENDIAN
879 #define MX_OPTION_BSWAP 0x80000000
880
881 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */
882 #define M_OPMODE_8BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
883 #define M_OPMODE_16BPP (M_OPMODE_DMA_BE_16BPP | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
884 #define M_OPMODE_24BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */
885 #define M_OPMODE_32BPP (M_OPMODE_DMA_BE_32BPP | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
886 #else
887 #error "Byte ordering have to be defined. Cannot continue."
888 #endif
889 #endif
890
891 #define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
892 #define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
893 #define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
894 #define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
895 #define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
896 #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
897 #ifdef __LITTLE_ENDIAN
898 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
899 #else
900 #define mga_setr(addr,port,val) do { mga_outb(addr, port); mga_outb((addr)+1, val); } while (0)
901 #endif
902
903 #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
904
905 #define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000)
906
907 /* code speedup */
908 #ifdef CONFIG_FB_MATROX_MILLENIUM
909 #define isInterleave(x) (x->interleave)
910 #define isMillenium(x) (x->millenium)
911 #define isMilleniumII(x) (x->milleniumII)
912 #else
913 #define isInterleave(x) (0)
914 #define isMillenium(x) (0)
915 #define isMilleniumII(x) (0)
916 #endif
917
918 #define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))
919 #define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))
920 #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
921 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
922 extern void matroxfb_DAC_out(CPMINFO int reg, int val);
923 extern int matroxfb_DAC_in(CPMINFO int reg);
924 extern struct list_head matroxfb_list;
925 extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
926 extern int matroxfb_switch(int con, struct fb_info *);
927 extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc);
928 extern int matroxfb_enable_irq(WPMINFO int reenable);
929
930 #ifdef MATROXFB_USE_SPINLOCKS
931 #define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
932 #define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
933 #define CRITFLAGS unsigned long critflags;
934 #else
935 #define CRITBEGIN
936 #define CRITEND
937 #define CRITFLAGS
938 #endif
939
940 #endif /* __MATROXFB_H__ */
941