1 /*
2  *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3  */
4 
5 /*
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #ifndef __ASM_ARCH_MXC_IRQS_H__
12 #define __ASM_ARCH_MXC_IRQS_H__
13 
14 #include <asm-generic/gpio.h>
15 
16 /*
17  * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
18  * have 128 IRQs, and those with AVIC have 64.
19  *
20  * To support single image, the biggest number should be defined on
21  * top of the list.
22  */
23 #if defined CONFIG_ARM_GIC
24 #define MXC_INTERNAL_IRQS	160
25 #elif defined CONFIG_MXC_TZIC
26 #define MXC_INTERNAL_IRQS	128
27 #else
28 #define MXC_INTERNAL_IRQS	64
29 #endif
30 
31 #define MXC_GPIO_IRQ_START	MXC_INTERNAL_IRQS
32 
33 /*
34  * The next 16 interrupts are for board specific purposes.  Since
35  * the kernel can only run on one machine at a time, we can re-use
36  * these.  If you need more, increase MXC_BOARD_IRQS, but keep it
37  * within sensible limits.
38  */
39 #define MXC_BOARD_IRQ_START	(MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
40 
41 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
42 #define MXC_BOARD_IRQS  80
43 #else
44 #define MXC_BOARD_IRQS	16
45 #endif
46 
47 #define MXC_IPU_IRQ_START	(MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
48 
49 #ifdef CONFIG_MX3_IPU_IRQS
50 #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
51 #else
52 #define MX3_IPU_IRQS 0
53 #endif
54 /* REVISIT: Add IPU irqs on IMX51 */
55 
56 #define NR_IRQS			(MXC_IPU_IRQ_START + MX3_IPU_IRQS)
57 
58 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
59 
60 /* all normal IRQs can be FIQs */
61 #define FIQ_START	0
62 /* switch between IRQ and FIQ */
63 extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
64 
65 #endif /* __ASM_ARCH_MXC_IRQS_H__ */
66