1 #ifndef __MACH_MX31_H__
2 #define __MACH_MX31_H__
3 
4 #ifndef __ASSEMBLER__
5 #include <linux/io.h>
6 #endif
7 
8 /*
9  * IRAM
10  */
11 #define MX31_IRAM_BASE_ADDR		0x1ffc0000	/* internal ram */
12 #define MX31_IRAM_SIZE			SZ_16K
13 
14 #define MX31_L2CC_BASE_ADDR		0x30000000
15 #define MX31_L2CC_SIZE			SZ_1M
16 
17 #define MX31_AIPS1_BASE_ADDR		0x43f00000
18 #define MX31_AIPS1_SIZE			SZ_1M
19 #define MX31_MAX_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x04000)
20 #define MX31_EVTMON_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x08000)
21 #define MX31_CLKCTL_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x0c000)
22 #define MX31_ETB_SLOT4_BASE_ADDR		(MX31_AIPS1_BASE_ADDR + 0x10000)
23 #define MX31_ETB_SLOT5_BASE_ADDR		(MX31_AIPS1_BASE_ADDR + 0x14000)
24 #define MX31_ECT_CTIO_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x18000)
25 #define MX31_I2C1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x80000)
26 #define MX31_I2C3_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x84000)
27 #define MX31_USB_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x88000)
28 #define MX31_USB_OTG_BASE_ADDR			(MX31_USB_BASE_ADDR + 0x0000)
29 #define MX31_USB_HS1_BASE_ADDR			(MX31_USB_BASE_ADDR + 0x0200)
30 #define MX31_USB_HS2_BASE_ADDR			(MX31_USB_BASE_ADDR + 0x0400)
31 #define MX31_ATA_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x8c000)
32 #define MX31_UART1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x90000)
33 #define MX31_UART2_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x94000)
34 #define MX31_I2C2_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x98000)
35 #define MX31_OWIRE_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x9c000)
36 #define MX31_SSI1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xa0000)
37 #define MX31_CSPI1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xa4000)
38 #define MX31_KPP_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xa8000)
39 #define MX31_IOMUXC_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xac000)
40 #define MX31_UART4_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xb0000)
41 #define MX31_UART5_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xb4000)
42 #define MX31_ECT_IP1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xb8000)
43 #define MX31_ECT_IP2_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xbc000)
44 
45 #define MX31_SPBA0_BASE_ADDR		0x50000000
46 #define MX31_SPBA0_SIZE			SZ_1M
47 #define MX31_SDHC1_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x04000)
48 #define MX31_SDHC2_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x08000)
49 #define MX31_UART3_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x0c000)
50 #define MX31_CSPI2_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x10000)
51 #define MX31_SSI2_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x14000)
52 #define MX31_SIM1_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x18000)
53 #define MX31_IIM_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x1c000)
54 #define MX31_ATA_DMA_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x20000)
55 #define MX31_MSHC1_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x24000)
56 #define MX31_SPBA_CTRL_BASE_ADDR		(MX31_SPBA0_BASE_ADDR + 0x3c000)
57 
58 #define MX31_AIPS2_BASE_ADDR		0x53f00000
59 #define MX31_AIPS2_SIZE			SZ_1M
60 #define MX31_CCM_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x80000)
61 #define MX31_CSPI3_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x84000)
62 #define MX31_FIRI_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x8c000)
63 #define MX31_GPT1_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x90000)
64 #define MX31_EPIT1_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x94000)
65 #define MX31_EPIT2_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x98000)
66 #define MX31_GPIO3_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xa4000)
67 #define MX31_SCC_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xac000)
68 #define MX31_SCM_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xae000)
69 #define MX31_SMN_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xaf000)
70 #define MX31_RNGA_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xb0000)
71 #define MX31_IPU_CTRL_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xc0000)
72 #define MX31_AUDMUX_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xc4000)
73 #define MX31_MPEG4_ENC_BASE_ADDR		(MX31_AIPS2_BASE_ADDR + 0xc8000)
74 #define MX31_GPIO1_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xcc000)
75 #define MX31_GPIO2_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xd0000)
76 #define MX31_SDMA_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xd4000)
77 #define MX31_RTC_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xd8000)
78 #define MX31_WDOG_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xdc000)
79 #define MX31_PWM_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xe0000)
80 #define MX31_RTIC_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xec000)
81 
82 #define MX31_ROMP_BASE_ADDR		0x60000000
83 #define MX31_ROMP_BASE_ADDR_VIRT	0xfc500000
84 #define MX31_ROMP_SIZE			SZ_1M
85 
86 #define MX31_AVIC_BASE_ADDR		0x68000000
87 #define MX31_AVIC_SIZE			SZ_1M
88 
89 #define MX31_IPU_MEM_BASE_ADDR		0x70000000
90 #define MX31_CSD0_BASE_ADDR		0x80000000
91 #define MX31_CSD1_BASE_ADDR		0x90000000
92 
93 #define MX31_CS0_BASE_ADDR		0xa0000000
94 #define MX31_CS1_BASE_ADDR		0xa8000000
95 #define MX31_CS2_BASE_ADDR		0xb0000000
96 #define MX31_CS3_BASE_ADDR		0xb2000000
97 
98 #define MX31_CS4_BASE_ADDR		0xb4000000
99 #define MX31_CS4_BASE_ADDR_VIRT		0xf6000000
100 #define MX31_CS4_SIZE			SZ_32M
101 
102 #define MX31_CS5_BASE_ADDR		0xb6000000
103 #define MX31_CS5_BASE_ADDR_VIRT		0xf8000000
104 #define MX31_CS5_SIZE			SZ_32M
105 
106 #define MX31_X_MEMC_BASE_ADDR		0xb8000000
107 #define MX31_X_MEMC_SIZE		SZ_64K
108 #define MX31_NFC_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x0000)
109 #define MX31_ESDCTL_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x1000)
110 #define MX31_WEIM_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x2000)
111 #define MX31_M3IF_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x3000)
112 #define MX31_EMI_CTL_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x4000)
113 #define MX31_PCMCIA_CTL_BASE_ADDR		MX31_EMI_CTL_BASE_ADDR
114 
115 #define MX31_WEIM_CSCRx_BASE_ADDR(cs)	(MX31_WEIM_BASE_ADDR + (cs) * 0x10)
116 #define MX31_WEIM_CSCRxU(cs)			(MX31_WEIM_CSCRx_BASE_ADDR(cs))
117 #define MX31_WEIM_CSCRxL(cs)			(MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
118 #define MX31_WEIM_CSCRxA(cs)			(MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
119 
120 #define MX31_PCMCIA_MEM_BASE_ADDR	0xbc000000
121 
122 #define MX31_IO_P2V(x)			IMX_IO_P2V(x)
123 #define MX31_IO_ADDRESS(x)		IOMEM(MX31_IO_P2V(x))
124 
125 #ifndef __ASSEMBLER__
mx31_setup_weimcs(size_t cs,unsigned upper,unsigned lower,unsigned addional)126 static inline void mx31_setup_weimcs(size_t cs,
127 		unsigned upper, unsigned lower, unsigned addional)
128 {
129 	__raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs)));
130 	__raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs)));
131 	__raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs)));
132 }
133 #endif
134 
135 #define MX31_INT_I2C3		3
136 #define MX31_INT_I2C2		4
137 #define MX31_INT_MPEG4_ENCODER	5
138 #define MX31_INT_RTIC		6
139 #define MX31_INT_FIRI		7
140 #define MX31_INT_SDHC2		8
141 #define MX31_INT_SDHC1		9
142 #define MX31_INT_I2C1		10
143 #define MX31_INT_SSI2		11
144 #define MX31_INT_SSI1		12
145 #define MX31_INT_CSPI2		13
146 #define MX31_INT_CSPI1		14
147 #define MX31_INT_ATA		15
148 #define MX31_INT_MBX		16
149 #define MX31_INT_CSPI3		17
150 #define MX31_INT_UART3		18
151 #define MX31_INT_IIM		19
152 #define MX31_INT_SIM2		20
153 #define MX31_INT_SIM1		21
154 #define MX31_INT_RNGA		22
155 #define MX31_INT_EVTMON		23
156 #define MX31_INT_KPP		24
157 #define MX31_INT_RTC		25
158 #define MX31_INT_PWM		26
159 #define MX31_INT_EPIT2		27
160 #define MX31_INT_EPIT1		28
161 #define MX31_INT_GPT		29
162 #define MX31_INT_POWER_FAIL	30
163 #define MX31_INT_CCM_DVFS	31
164 #define MX31_INT_UART2		32
165 #define MX31_INT_NFC		33
166 #define MX31_INT_SDMA		34
167 #define MX31_INT_USB_HS1	35
168 #define MX31_INT_USB_HS2	36
169 #define MX31_INT_USB_OTG	37
170 #define MX31_INT_MSHC1		39
171 #define MX31_INT_MSHC2		40
172 #define MX31_INT_IPU_ERR	41
173 #define MX31_INT_IPU_SYN	42
174 #define MX31_INT_UART1		45
175 #define MX31_INT_UART4		46
176 #define MX31_INT_UART5		47
177 #define MX31_INT_ECT		48
178 #define MX31_INT_SCC_SCM	49
179 #define MX31_INT_SCC_SMN	50
180 #define MX31_INT_GPIO2		51
181 #define MX31_INT_GPIO1		52
182 #define MX31_INT_CCM		53
183 #define MX31_INT_PCMCIA		54
184 #define MX31_INT_WDOG		55
185 #define MX31_INT_GPIO3		56
186 #define MX31_INT_EXT_POWER	58
187 #define MX31_INT_EXT_TEMPER	59
188 #define MX31_INT_EXT_SENSOR60	60
189 #define MX31_INT_EXT_SENSOR61	61
190 #define MX31_INT_EXT_WDOG	62
191 #define MX31_INT_EXT_TV		63
192 
193 #define MX31_DMA_REQ_SDHC1	20
194 #define MX31_DMA_REQ_SDHC2	21
195 #define MX31_DMA_REQ_SSI2_RX1	22
196 #define MX31_DMA_REQ_SSI2_TX1	23
197 #define MX31_DMA_REQ_SSI2_RX0	24
198 #define MX31_DMA_REQ_SSI2_TX0	25
199 #define MX31_DMA_REQ_SSI1_RX1	26
200 #define MX31_DMA_REQ_SSI1_TX1	27
201 #define MX31_DMA_REQ_SSI1_RX0	28
202 #define MX31_DMA_REQ_SSI1_TX0	29
203 
204 #define MX31_PROD_SIGNATURE		0x1	/* For MX31 */
205 
206 #endif /* ifndef __MACH_MX31_H__ */
207