1 /*
2  * MUSB OTG driver register defines
3  *
4  * Copyright 2005 Mentor Graphics Corporation
5  * Copyright (C) 2005-2006 by Texas Instruments
6  * Copyright (C) 2006-2007 Nokia Corporation
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  */
34 
35 #ifndef __MUSB_REGS_H__
36 #define __MUSB_REGS_H__
37 
38 #define MUSB_EP0_FIFOSIZE	64	/* This is non-configurable */
39 
40 /*
41  * MUSB Register bits
42  */
43 
44 /* POWER */
45 #define MUSB_POWER_ISOUPDATE	0x80
46 #define MUSB_POWER_SOFTCONN	0x40
47 #define MUSB_POWER_HSENAB	0x20
48 #define MUSB_POWER_HSMODE	0x10
49 #define MUSB_POWER_RESET	0x08
50 #define MUSB_POWER_RESUME	0x04
51 #define MUSB_POWER_SUSPENDM	0x02
52 #define MUSB_POWER_ENSUSPEND	0x01
53 
54 /* INTRUSB */
55 #define MUSB_INTR_SUSPEND	0x01
56 #define MUSB_INTR_RESUME	0x02
57 #define MUSB_INTR_RESET		0x04
58 #define MUSB_INTR_BABBLE	0x04
59 #define MUSB_INTR_SOF		0x08
60 #define MUSB_INTR_CONNECT	0x10
61 #define MUSB_INTR_DISCONNECT	0x20
62 #define MUSB_INTR_SESSREQ	0x40
63 #define MUSB_INTR_VBUSERROR	0x80	/* For SESSION end */
64 
65 /* DEVCTL */
66 #define MUSB_DEVCTL_BDEVICE	0x80
67 #define MUSB_DEVCTL_FSDEV	0x40
68 #define MUSB_DEVCTL_LSDEV	0x20
69 #define MUSB_DEVCTL_VBUS	0x18
70 #define MUSB_DEVCTL_VBUS_SHIFT	3
71 #define MUSB_DEVCTL_HM		0x04
72 #define MUSB_DEVCTL_HR		0x02
73 #define MUSB_DEVCTL_SESSION	0x01
74 
75 /* MUSB ULPI VBUSCONTROL */
76 #define MUSB_ULPI_USE_EXTVBUS	0x01
77 #define MUSB_ULPI_USE_EXTVBUSIND 0x02
78 /* ULPI_REG_CONTROL */
79 #define MUSB_ULPI_REG_REQ	(1 << 0)
80 #define MUSB_ULPI_REG_CMPLT	(1 << 1)
81 #define MUSB_ULPI_RDN_WR	(1 << 2)
82 
83 /* TESTMODE */
84 #define MUSB_TEST_FORCE_HOST	0x80
85 #define MUSB_TEST_FIFO_ACCESS	0x40
86 #define MUSB_TEST_FORCE_FS	0x20
87 #define MUSB_TEST_FORCE_HS	0x10
88 #define MUSB_TEST_PACKET	0x08
89 #define MUSB_TEST_K		0x04
90 #define MUSB_TEST_J		0x02
91 #define MUSB_TEST_SE0_NAK	0x01
92 
93 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
94 #define MUSB_FIFOSZ_DPB	0x10
95 /* Allocation size (8, 16, 32, ... 4096) */
96 #define MUSB_FIFOSZ_SIZE	0x0f
97 
98 /* CSR0 */
99 #define MUSB_CSR0_FLUSHFIFO	0x0100
100 #define MUSB_CSR0_TXPKTRDY	0x0002
101 #define MUSB_CSR0_RXPKTRDY	0x0001
102 
103 /* CSR0 in Peripheral mode */
104 #define MUSB_CSR0_P_SVDSETUPEND	0x0080
105 #define MUSB_CSR0_P_SVDRXPKTRDY	0x0040
106 #define MUSB_CSR0_P_SENDSTALL	0x0020
107 #define MUSB_CSR0_P_SETUPEND	0x0010
108 #define MUSB_CSR0_P_DATAEND	0x0008
109 #define MUSB_CSR0_P_SENTSTALL	0x0004
110 
111 /* CSR0 in Host mode */
112 #define MUSB_CSR0_H_DIS_PING		0x0800
113 #define MUSB_CSR0_H_WR_DATATOGGLE	0x0400	/* Set to allow setting: */
114 #define MUSB_CSR0_H_DATATOGGLE		0x0200	/* Data toggle control */
115 #define MUSB_CSR0_H_NAKTIMEOUT		0x0080
116 #define MUSB_CSR0_H_STATUSPKT		0x0040
117 #define MUSB_CSR0_H_REQPKT		0x0020
118 #define MUSB_CSR0_H_ERROR		0x0010
119 #define MUSB_CSR0_H_SETUPPKT		0x0008
120 #define MUSB_CSR0_H_RXSTALL		0x0004
121 
122 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
123 #define MUSB_CSR0_P_WZC_BITS	\
124 	(MUSB_CSR0_P_SENTSTALL)
125 #define MUSB_CSR0_H_WZC_BITS	\
126 	(MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
127 	| MUSB_CSR0_RXPKTRDY)
128 
129 /* TxType/RxType */
130 #define MUSB_TYPE_SPEED		0xc0
131 #define MUSB_TYPE_SPEED_SHIFT	6
132 #define MUSB_TYPE_PROTO		0x30	/* Implicitly zero for ep0 */
133 #define MUSB_TYPE_PROTO_SHIFT	4
134 #define MUSB_TYPE_REMOTE_END	0xf	/* Implicitly zero for ep0 */
135 
136 /* CONFIGDATA */
137 #define MUSB_CONFIGDATA_MPRXE		0x80	/* Auto bulk pkt combining */
138 #define MUSB_CONFIGDATA_MPTXE		0x40	/* Auto bulk pkt splitting */
139 #define MUSB_CONFIGDATA_BIGENDIAN	0x20
140 #define MUSB_CONFIGDATA_HBRXE		0x10	/* HB-ISO for RX */
141 #define MUSB_CONFIGDATA_HBTXE		0x08	/* HB-ISO for TX */
142 #define MUSB_CONFIGDATA_DYNFIFO		0x04	/* Dynamic FIFO sizing */
143 #define MUSB_CONFIGDATA_SOFTCONE	0x02	/* SoftConnect */
144 #define MUSB_CONFIGDATA_UTMIDW		0x01	/* Data width 0/1 => 8/16bits */
145 
146 /* TXCSR in Peripheral and Host mode */
147 #define MUSB_TXCSR_AUTOSET		0x8000
148 #define MUSB_TXCSR_DMAENAB		0x1000
149 #define MUSB_TXCSR_FRCDATATOG		0x0800
150 #define MUSB_TXCSR_DMAMODE		0x0400
151 #define MUSB_TXCSR_CLRDATATOG		0x0040
152 #define MUSB_TXCSR_FLUSHFIFO		0x0008
153 #define MUSB_TXCSR_FIFONOTEMPTY		0x0002
154 #define MUSB_TXCSR_TXPKTRDY		0x0001
155 
156 /* TXCSR in Peripheral mode */
157 #define MUSB_TXCSR_P_ISO		0x4000
158 #define MUSB_TXCSR_P_INCOMPTX		0x0080
159 #define MUSB_TXCSR_P_SENTSTALL		0x0020
160 #define MUSB_TXCSR_P_SENDSTALL		0x0010
161 #define MUSB_TXCSR_P_UNDERRUN		0x0004
162 
163 /* TXCSR in Host mode */
164 #define MUSB_TXCSR_H_WR_DATATOGGLE	0x0200
165 #define MUSB_TXCSR_H_DATATOGGLE		0x0100
166 #define MUSB_TXCSR_H_NAKTIMEOUT		0x0080
167 #define MUSB_TXCSR_H_RXSTALL		0x0020
168 #define MUSB_TXCSR_H_ERROR		0x0004
169 
170 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
171 #define MUSB_TXCSR_P_WZC_BITS	\
172 	(MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
173 	| MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
174 #define MUSB_TXCSR_H_WZC_BITS	\
175 	(MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
176 	| MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
177 
178 /* RXCSR in Peripheral and Host mode */
179 #define MUSB_RXCSR_AUTOCLEAR		0x8000
180 #define MUSB_RXCSR_DMAENAB		0x2000
181 #define MUSB_RXCSR_DISNYET		0x1000
182 #define MUSB_RXCSR_PID_ERR		0x1000
183 #define MUSB_RXCSR_DMAMODE		0x0800
184 #define MUSB_RXCSR_INCOMPRX		0x0100
185 #define MUSB_RXCSR_CLRDATATOG		0x0080
186 #define MUSB_RXCSR_FLUSHFIFO		0x0010
187 #define MUSB_RXCSR_DATAERROR		0x0008
188 #define MUSB_RXCSR_FIFOFULL		0x0002
189 #define MUSB_RXCSR_RXPKTRDY		0x0001
190 
191 /* RXCSR in Peripheral mode */
192 #define MUSB_RXCSR_P_ISO		0x4000
193 #define MUSB_RXCSR_P_SENTSTALL		0x0040
194 #define MUSB_RXCSR_P_SENDSTALL		0x0020
195 #define MUSB_RXCSR_P_OVERRUN		0x0004
196 
197 /* RXCSR in Host mode */
198 #define MUSB_RXCSR_H_AUTOREQ		0x4000
199 #define MUSB_RXCSR_H_WR_DATATOGGLE	0x0400
200 #define MUSB_RXCSR_H_DATATOGGLE		0x0200
201 #define MUSB_RXCSR_H_RXSTALL		0x0040
202 #define MUSB_RXCSR_H_REQPKT		0x0020
203 #define MUSB_RXCSR_H_ERROR		0x0004
204 
205 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
206 #define MUSB_RXCSR_P_WZC_BITS	\
207 	(MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
208 	| MUSB_RXCSR_RXPKTRDY)
209 #define MUSB_RXCSR_H_WZC_BITS	\
210 	(MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
211 	| MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
212 
213 /* HUBADDR */
214 #define MUSB_HUBADDR_MULTI_TT		0x80
215 
216 
217 #ifndef CONFIG_BLACKFIN
218 
219 /*
220  * Common USB registers
221  */
222 
223 #define MUSB_FADDR		0x00	/* 8-bit */
224 #define MUSB_POWER		0x01	/* 8-bit */
225 
226 #define MUSB_INTRTX		0x02	/* 16-bit */
227 #define MUSB_INTRRX		0x04
228 #define MUSB_INTRTXE		0x06
229 #define MUSB_INTRRXE		0x08
230 #define MUSB_INTRUSB		0x0A	/* 8 bit */
231 #define MUSB_INTRUSBE		0x0B	/* 8 bit */
232 #define MUSB_FRAME		0x0C
233 #define MUSB_INDEX		0x0E	/* 8 bit */
234 #define MUSB_TESTMODE		0x0F	/* 8 bit */
235 
236 /* Get offset for a given FIFO from musb->mregs */
237 #if defined(CONFIG_USB_MUSB_TUSB6010) ||	\
238 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
239 #define MUSB_FIFO_OFFSET(epnum)	(0x200 + ((epnum) * 0x20))
240 #else
241 #define MUSB_FIFO_OFFSET(epnum)	(0x20 + ((epnum) * 4))
242 #endif
243 
244 /*
245  * Additional Control Registers
246  */
247 
248 #define MUSB_DEVCTL		0x60	/* 8 bit */
249 
250 /* These are always controlled through the INDEX register */
251 #define MUSB_TXFIFOSZ		0x62	/* 8-bit (see masks) */
252 #define MUSB_RXFIFOSZ		0x63	/* 8-bit (see masks) */
253 #define MUSB_TXFIFOADD		0x64	/* 16-bit offset shifted right 3 */
254 #define MUSB_RXFIFOADD		0x66	/* 16-bit offset shifted right 3 */
255 
256 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
257 #define MUSB_HWVERS		0x6C	/* 8 bit */
258 #define MUSB_ULPI_BUSCONTROL	0x70	/* 8 bit */
259 #define MUSB_ULPI_INT_MASK	0x72	/* 8 bit */
260 #define MUSB_ULPI_INT_SRC	0x73	/* 8 bit */
261 #define MUSB_ULPI_REG_DATA	0x74	/* 8 bit */
262 #define MUSB_ULPI_REG_ADDR	0x75	/* 8 bit */
263 #define MUSB_ULPI_REG_CONTROL	0x76	/* 8 bit */
264 #define MUSB_ULPI_RAW_DATA	0x77	/* 8 bit */
265 
266 #define MUSB_EPINFO		0x78	/* 8 bit */
267 #define MUSB_RAMINFO		0x79	/* 8 bit */
268 #define MUSB_LINKINFO		0x7a	/* 8 bit */
269 #define MUSB_VPLEN		0x7b	/* 8 bit */
270 #define MUSB_HS_EOF1		0x7c	/* 8 bit */
271 #define MUSB_FS_EOF1		0x7d	/* 8 bit */
272 #define MUSB_LS_EOF1		0x7e	/* 8 bit */
273 
274 /* Offsets to endpoint registers */
275 #define MUSB_TXMAXP		0x00
276 #define MUSB_TXCSR		0x02
277 #define MUSB_CSR0		MUSB_TXCSR	/* Re-used for EP0 */
278 #define MUSB_RXMAXP		0x04
279 #define MUSB_RXCSR		0x06
280 #define MUSB_RXCOUNT		0x08
281 #define MUSB_COUNT0		MUSB_RXCOUNT	/* Re-used for EP0 */
282 #define MUSB_TXTYPE		0x0A
283 #define MUSB_TYPE0		MUSB_TXTYPE	/* Re-used for EP0 */
284 #define MUSB_TXINTERVAL		0x0B
285 #define MUSB_NAKLIMIT0		MUSB_TXINTERVAL	/* Re-used for EP0 */
286 #define MUSB_RXTYPE		0x0C
287 #define MUSB_RXINTERVAL		0x0D
288 #define MUSB_FIFOSIZE		0x0F
289 #define MUSB_CONFIGDATA		MUSB_FIFOSIZE	/* Re-used for EP0 */
290 
291 /* Offsets to endpoint registers in indexed model (using INDEX register) */
292 #define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
293 	(0x10 + (_offset))
294 
295 /* Offsets to endpoint registers in flat models */
296 #define MUSB_FLAT_OFFSET(_epnum, _offset)	\
297 	(0x100 + (0x10*(_epnum)) + (_offset))
298 
299 #if defined(CONFIG_USB_MUSB_TUSB6010) ||	\
300 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
301 /* TUSB6010 EP0 configuration register is special */
302 #define MUSB_TUSB_OFFSET(_epnum, _offset)	\
303 	(0x10 + _offset)
304 #include "tusb6010.h"		/* Needed "only" for TUSB_EP0_CONF */
305 #endif
306 
307 #define MUSB_TXCSR_MODE			0x2000
308 
309 /* "bus control"/target registers, for host side multipoint (external hubs) */
310 #define MUSB_TXFUNCADDR		0x00
311 #define MUSB_TXHUBADDR		0x02
312 #define MUSB_TXHUBPORT		0x03
313 
314 #define MUSB_RXFUNCADDR		0x04
315 #define MUSB_RXHUBADDR		0x06
316 #define MUSB_RXHUBPORT		0x07
317 
318 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
319 	(0x80 + (8*(_epnum)) + (_offset))
320 
musb_write_txfifosz(void __iomem * mbase,u8 c_size)321 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
322 {
323 	musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
324 }
325 
musb_write_txfifoadd(void __iomem * mbase,u16 c_off)326 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
327 {
328 	musb_writew(mbase, MUSB_TXFIFOADD, c_off);
329 }
330 
musb_write_rxfifosz(void __iomem * mbase,u8 c_size)331 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
332 {
333 	musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
334 }
335 
musb_write_rxfifoadd(void __iomem * mbase,u16 c_off)336 static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
337 {
338 	musb_writew(mbase, MUSB_RXFIFOADD, c_off);
339 }
340 
musb_write_ulpi_buscontrol(void __iomem * mbase,u8 val)341 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
342 {
343 	musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
344 }
345 
musb_read_txfifosz(void __iomem * mbase)346 static inline u8 musb_read_txfifosz(void __iomem *mbase)
347 {
348 	return musb_readb(mbase, MUSB_TXFIFOSZ);
349 }
350 
musb_read_txfifoadd(void __iomem * mbase)351 static inline u16 musb_read_txfifoadd(void __iomem *mbase)
352 {
353 	return musb_readw(mbase, MUSB_TXFIFOADD);
354 }
355 
musb_read_rxfifosz(void __iomem * mbase)356 static inline u8 musb_read_rxfifosz(void __iomem *mbase)
357 {
358 	return musb_readb(mbase, MUSB_RXFIFOSZ);
359 }
360 
musb_read_rxfifoadd(void __iomem * mbase)361 static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
362 {
363 	return musb_readw(mbase, MUSB_RXFIFOADD);
364 }
365 
musb_read_ulpi_buscontrol(void __iomem * mbase)366 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
367 {
368 	return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
369 }
370 
musb_read_configdata(void __iomem * mbase)371 static inline u8 musb_read_configdata(void __iomem *mbase)
372 {
373 	musb_writeb(mbase, MUSB_INDEX, 0);
374 	return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
375 }
376 
musb_read_hwvers(void __iomem * mbase)377 static inline u16 musb_read_hwvers(void __iomem *mbase)
378 {
379 	return musb_readw(mbase, MUSB_HWVERS);
380 }
381 
musb_read_target_reg_base(u8 i,void __iomem * mbase)382 static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
383 {
384 	return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
385 }
386 
musb_write_rxfunaddr(void __iomem * ep_target_regs,u8 qh_addr_reg)387 static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
388 		u8 qh_addr_reg)
389 {
390 	musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
391 }
392 
musb_write_rxhubaddr(void __iomem * ep_target_regs,u8 qh_h_addr_reg)393 static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
394 		u8 qh_h_addr_reg)
395 {
396 	musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
397 }
398 
musb_write_rxhubport(void __iomem * ep_target_regs,u8 qh_h_port_reg)399 static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
400 		u8 qh_h_port_reg)
401 {
402 	musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
403 }
404 
musb_write_txfunaddr(void __iomem * mbase,u8 epnum,u8 qh_addr_reg)405 static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
406 		u8 qh_addr_reg)
407 {
408 	musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
409 			qh_addr_reg);
410 }
411 
musb_write_txhubaddr(void __iomem * mbase,u8 epnum,u8 qh_addr_reg)412 static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
413 		u8 qh_addr_reg)
414 {
415 	musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
416 			qh_addr_reg);
417 }
418 
musb_write_txhubport(void __iomem * mbase,u8 epnum,u8 qh_h_port_reg)419 static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
420 		u8 qh_h_port_reg)
421 {
422 	musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
423 			qh_h_port_reg);
424 }
425 
musb_read_rxfunaddr(void __iomem * mbase,u8 epnum)426 static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
427 {
428 	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
429 }
430 
musb_read_rxhubaddr(void __iomem * mbase,u8 epnum)431 static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
432 {
433 	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
434 }
435 
musb_read_rxhubport(void __iomem * mbase,u8 epnum)436 static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
437 {
438 	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
439 }
440 
musb_read_txfunaddr(void __iomem * mbase,u8 epnum)441 static inline u8  musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
442 {
443 	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
444 }
445 
musb_read_txhubaddr(void __iomem * mbase,u8 epnum)446 static inline u8  musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
447 {
448 	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
449 }
450 
musb_read_txhubport(void __iomem * mbase,u8 epnum)451 static inline u8  musb_read_txhubport(void __iomem *mbase, u8 epnum)
452 {
453 	return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
454 }
455 
456 #else /* CONFIG_BLACKFIN */
457 
458 #define USB_BASE		USB_FADDR
459 #define USB_OFFSET(reg)		(reg - USB_BASE)
460 
461 /*
462  * Common USB registers
463  */
464 #define MUSB_FADDR		USB_OFFSET(USB_FADDR)	/* 8-bit */
465 #define MUSB_POWER		USB_OFFSET(USB_POWER)	/* 8-bit */
466 #define MUSB_INTRTX		USB_OFFSET(USB_INTRTX)	/* 16-bit */
467 #define MUSB_INTRRX		USB_OFFSET(USB_INTRRX)
468 #define MUSB_INTRTXE		USB_OFFSET(USB_INTRTXE)
469 #define MUSB_INTRRXE		USB_OFFSET(USB_INTRRXE)
470 #define MUSB_INTRUSB		USB_OFFSET(USB_INTRUSB)	/* 8 bit */
471 #define MUSB_INTRUSBE		USB_OFFSET(USB_INTRUSBE)/* 8 bit */
472 #define MUSB_FRAME		USB_OFFSET(USB_FRAME)
473 #define MUSB_INDEX		USB_OFFSET(USB_INDEX)	/* 8 bit */
474 #define MUSB_TESTMODE		USB_OFFSET(USB_TESTMODE)/* 8 bit */
475 
476 /* Get offset for a given FIFO from musb->mregs */
477 #define MUSB_FIFO_OFFSET(epnum)	\
478 	(USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
479 
480 /*
481  * Additional Control Registers
482  */
483 
484 #define MUSB_DEVCTL		USB_OFFSET(USB_OTG_DEV_CTL)	/* 8 bit */
485 
486 #define MUSB_LINKINFO		USB_OFFSET(USB_LINKINFO)/* 8 bit */
487 #define MUSB_VPLEN		USB_OFFSET(USB_VPLEN)	/* 8 bit */
488 #define MUSB_HS_EOF1		USB_OFFSET(USB_HS_EOF1)	/* 8 bit */
489 #define MUSB_FS_EOF1		USB_OFFSET(USB_FS_EOF1)	/* 8 bit */
490 #define MUSB_LS_EOF1		USB_OFFSET(USB_LS_EOF1)	/* 8 bit */
491 
492 /* Offsets to endpoint registers */
493 #define MUSB_TXMAXP		0x00
494 #define MUSB_TXCSR		0x04
495 #define MUSB_CSR0		MUSB_TXCSR	/* Re-used for EP0 */
496 #define MUSB_RXMAXP		0x08
497 #define MUSB_RXCSR		0x0C
498 #define MUSB_RXCOUNT		0x10
499 #define MUSB_COUNT0		MUSB_RXCOUNT	/* Re-used for EP0 */
500 #define MUSB_TXTYPE		0x14
501 #define MUSB_TYPE0		MUSB_TXTYPE	/* Re-used for EP0 */
502 #define MUSB_TXINTERVAL		0x18
503 #define MUSB_NAKLIMIT0		MUSB_TXINTERVAL	/* Re-used for EP0 */
504 #define MUSB_RXTYPE		0x1C
505 #define MUSB_RXINTERVAL		0x20
506 #define MUSB_TXCOUNT		0x28
507 
508 /* Offsets to endpoint registers in indexed model (using INDEX register) */
509 #define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
510 	(0x40 + (_offset))
511 
512 /* Offsets to endpoint registers in flat models */
513 #define MUSB_FLAT_OFFSET(_epnum, _offset)	\
514 	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
515 
516 /* Not implemented - HW has separate Tx/Rx FIFO */
517 #define MUSB_TXCSR_MODE			0x0000
518 
musb_write_txfifosz(void __iomem * mbase,u8 c_size)519 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
520 {
521 }
522 
musb_write_txfifoadd(void __iomem * mbase,u16 c_off)523 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
524 {
525 }
526 
musb_write_rxfifosz(void __iomem * mbase,u8 c_size)527 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
528 {
529 }
530 
musb_write_rxfifoadd(void __iomem * mbase,u16 c_off)531 static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
532 {
533 }
534 
musb_write_ulpi_buscontrol(void __iomem * mbase,u8 val)535 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
536 {
537 }
538 
musb_read_txfifosz(void __iomem * mbase)539 static inline u8 musb_read_txfifosz(void __iomem *mbase)
540 {
541 	return 0;
542 }
543 
musb_read_txfifoadd(void __iomem * mbase)544 static inline u16 musb_read_txfifoadd(void __iomem *mbase)
545 {
546 	return 0;
547 }
548 
musb_read_rxfifosz(void __iomem * mbase)549 static inline u8 musb_read_rxfifosz(void __iomem *mbase)
550 {
551 	return 0;
552 }
553 
musb_read_rxfifoadd(void __iomem * mbase)554 static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
555 {
556 	return 0;
557 }
558 
musb_read_ulpi_buscontrol(void __iomem * mbase)559 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
560 {
561 	return 0;
562 }
563 
musb_read_configdata(void __iomem * mbase)564 static inline u8 musb_read_configdata(void __iomem *mbase)
565 {
566 	return 0;
567 }
568 
musb_read_hwvers(void __iomem * mbase)569 static inline u16 musb_read_hwvers(void __iomem *mbase)
570 {
571 	/*
572 	 * This register is invisible on Blackfin, actually the MUSB
573 	 * RTL version of Blackfin is 1.9, so just harcode its value.
574 	 */
575 	return MUSB_HWVERS_1900;
576 }
577 
musb_read_target_reg_base(u8 i,void __iomem * mbase)578 static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
579 {
580 	return NULL;
581 }
582 
musb_write_rxfunaddr(void __iomem * ep_target_regs,u8 qh_addr_req)583 static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
584 		u8 qh_addr_req)
585 {
586 }
587 
musb_write_rxhubaddr(void __iomem * ep_target_regs,u8 qh_h_addr_reg)588 static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
589 		u8 qh_h_addr_reg)
590 {
591 }
592 
musb_write_rxhubport(void __iomem * ep_target_regs,u8 qh_h_port_reg)593 static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
594 		u8 qh_h_port_reg)
595 {
596 }
597 
musb_write_txfunaddr(void __iomem * mbase,u8 epnum,u8 qh_addr_reg)598 static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
599 		u8 qh_addr_reg)
600 {
601 }
602 
musb_write_txhubaddr(void __iomem * mbase,u8 epnum,u8 qh_addr_reg)603 static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
604 		u8 qh_addr_reg)
605 {
606 }
607 
musb_write_txhubport(void __iomem * mbase,u8 epnum,u8 qh_h_port_reg)608 static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
609 		u8 qh_h_port_reg)
610 {
611 }
612 
musb_read_rxfunaddr(void __iomem * mbase,u8 epnum)613 static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
614 {
615 	return 0;
616 }
617 
musb_read_rxhubaddr(void __iomem * mbase,u8 epnum)618 static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
619 {
620 	return 0;
621 }
622 
musb_read_rxhubport(void __iomem * mbase,u8 epnum)623 static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
624 {
625 	return 0;
626 }
627 
musb_read_txfunaddr(void __iomem * mbase,u8 epnum)628 static inline u8  musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
629 {
630 	return 0;
631 }
632 
musb_read_txhubaddr(void __iomem * mbase,u8 epnum)633 static inline u8  musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
634 {
635 	return 0;
636 }
637 
musb_read_txhubport(void __iomem * mbase,u8 epnum)638 static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
639 {
640 	return 0;
641 }
642 
643 #endif /* CONFIG_BLACKFIN */
644 
645 #endif	/* __MUSB_REGS_H__ */
646