1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT7921_MAC_H
5 #define __MT7921_MAC_H
6
7 #include "../mt76_connac2_mac.h"
8
9 #define MT_CT_PARSE_LEN 72
10 #define MT_CT_DMA_BUF_NUM 2
11
12 #define MT_RXD0_LENGTH GENMASK(15, 0)
13 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
15
16 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
17 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
18 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
19
20 enum rx_pkt_type {
21 PKT_TYPE_TXS,
22 PKT_TYPE_TXRXV,
23 PKT_TYPE_NORMAL,
24 PKT_TYPE_RX_DUP_RFB,
25 PKT_TYPE_RX_TMR,
26 PKT_TYPE_RETRIEVE,
27 PKT_TYPE_TXRX_NOTIFY,
28 PKT_TYPE_RX_EVENT,
29 PKT_TYPE_NORMAL_MCU,
30 };
31
32 /* RXD DW1 */
33 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
34 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
35 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
36 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
37 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
38 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
39 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
40 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
41 #define MT_RXD1_NORMAL_CM BIT(23)
42 #define MT_RXD1_NORMAL_CLM BIT(24)
43 #define MT_RXD1_NORMAL_ICV_ERR BIT(25)
44 #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
45 #define MT_RXD1_NORMAL_FCS_ERR BIT(27)
46 #define MT_RXD1_NORMAL_BAND_IDX BIT(28)
47 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
48 #define MT_RXD1_NORMAL_ADD_OM BIT(30)
49 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
50
51 /* RXD DW2 */
52 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
53 #define MT_RXD2_NORMAL_CO_ANT BIT(6)
54 #define MT_RXD2_NORMAL_BF_CQI BIT(7)
55 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
56 #define MT_RXD2_NORMAL_HDR_TRANS BIT(13)
57 #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)
58 #define MT_RXD2_NORMAL_TID GENMASK(19, 16)
59 #define MT_RXD2_NORMAL_MU_BAR BIT(21)
60 #define MT_RXD2_NORMAL_SW_BIT BIT(22)
61 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
62 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
63 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
64 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
65 #define MT_RXD2_NORMAL_FRAG BIT(27)
66 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
67 #define MT_RXD2_NORMAL_NDATA BIT(29)
68 #define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
69 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
70
71 /* RXD DW3 */
72 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
73 #define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
74 #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
75 #define MT_RXD3_NORMAL_U2M BIT(0)
76 #define MT_RXD3_NORMAL_HTC_VLD BIT(0)
77 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(19)
78 #define MT_RXD3_NORMAL_BEACON_MC BIT(20)
79 #define MT_RXD3_NORMAL_BEACON_UC BIT(21)
80 #define MT_RXD3_NORMAL_AMSDU BIT(22)
81 #define MT_RXD3_NORMAL_MESH BIT(23)
82 #define MT_RXD3_NORMAL_MHCP BIT(24)
83 #define MT_RXD3_NORMAL_NO_INFO_WB BIT(25)
84 #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS BIT(26)
85 #define MT_RXD3_NORMAL_POWER_SAVE_STAT BIT(27)
86 #define MT_RXD3_NORMAL_MORE BIT(28)
87 #define MT_RXD3_NORMAL_UNWANT BIT(29)
88 #define MT_RXD3_NORMAL_RX_DROP BIT(30)
89 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
90
91 /* RXD DW4 */
92 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
93 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
94 #define MT_RXD4_MID_AMSDU_FRAME BIT(1)
95 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
96 #define MT_RXD4_NORMAL_PATTERN_DROP BIT(9)
97 #define MT_RXD4_NORMAL_CLS BIT(10)
98 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
99 #define MT_RXD4_NORMAL_MAGIC_PKT BIT(13)
100 #define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
101 #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
102 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
103 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
104
105 /* RXD GROUP4 */
106 #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0)
107 #define MT_RXD6_TA_LO GENMASK(31, 16)
108
109 #define MT_RXD7_TA_HI GENMASK(31, 0)
110
111 #define MT_RXD8_SEQ_CTRL GENMASK(15, 0)
112 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
113
114 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
115
116 /* P-RXV DW0 */
117 #define MT_PRXV_TX_RATE GENMASK(6, 0)
118 #define MT_PRXV_TX_DCM BIT(4)
119 #define MT_PRXV_TX_ER_SU_106T BIT(5)
120 #define MT_PRXV_NSTS GENMASK(9, 7)
121 #define MT_PRXV_TXBF BIT(10)
122 #define MT_PRXV_HT_AD_CODE BIT(11)
123 #define MT_PRXV_FRAME_MODE GENMASK(14, 12)
124 #define MT_PRXV_SGI GENMASK(16, 15)
125 #define MT_PRXV_STBC GENMASK(23, 22)
126 #define MT_PRXV_TX_MODE GENMASK(27, 24)
127 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
128
129 /* P-RXV DW1 */
130 #define MT_PRXV_RCPI3 GENMASK(31, 24)
131 #define MT_PRXV_RCPI2 GENMASK(23, 16)
132 #define MT_PRXV_RCPI1 GENMASK(15, 8)
133 #define MT_PRXV_RCPI0 GENMASK(7, 0)
134 #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
135
136 /* C-RXV */
137 #define MT_CRXV_HT_STBC GENMASK(1, 0)
138 #define MT_CRXV_TX_MODE GENMASK(7, 4)
139 #define MT_CRXV_FRAME_MODE GENMASK(10, 8)
140 #define MT_CRXV_HT_SHORT_GI GENMASK(14, 13)
141 #define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17)
142 #define MT_CRXV_HE_LDPC_EXT_SYM BIT(20)
143 #define MT_CRXV_HE_PE_DISAMBIG BIT(23)
144 #define MT_CRXV_HE_NUM_USER GENMASK(30, 24)
145 #define MT_CRXV_HE_UPLINK BIT(31)
146
147 #define MT_CRXV_HE_RU0 GENMASK(7, 0)
148 #define MT_CRXV_HE_RU1 GENMASK(15, 8)
149 #define MT_CRXV_HE_RU2 GENMASK(23, 16)
150 #define MT_CRXV_HE_RU3 GENMASK(31, 24)
151 #define MT_CRXV_HE_MU_AID GENMASK(30, 20)
152
153 #define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
154 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
155 #define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
156 #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
157
158 #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
159 #define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)
160 #define MT_CRXV_HE_BEAM_CHNG BIT(13)
161 #define MT_CRXV_HE_DOPPLER BIT(16)
162
163 #define MT_CRXV_SNR GENMASK(18, 13)
164 #define MT_CRXV_FOE_LO GENMASK(31, 19)
165 #define MT_CRXV_FOE_HI GENMASK(6, 0)
166 #define MT_CRXV_FOE_SHIFT 13
167
168 enum tx_port_idx {
169 MT_TX_PORT_IDX_LMAC,
170 MT_TX_PORT_IDX_MCU
171 };
172
173 enum tx_mcu_port_q_idx {
174 MT_TX_MCU_PORT_RX_Q0 = 0x20,
175 MT_TX_MCU_PORT_RX_Q1,
176 MT_TX_MCU_PORT_RX_Q2,
177 MT_TX_MCU_PORT_RX_Q3,
178 MT_TX_MCU_PORT_RX_FWDL = 0x3e
179 };
180
181 #define MT_CT_INFO_APPLY_TXD BIT(0)
182 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
183 #define MT_CT_INFO_MGMT_FRAME BIT(2)
184 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
185 #define MT_CT_INFO_HSR2_TX BIT(4)
186 #define MT_CT_INFO_FROM_HOST BIT(7)
187
188 #define MT_TXP_MAX_BUF_NUM 6
189
190 struct mt7921_txp {
191 __le16 flags;
192 __le16 token;
193 u8 bss_idx;
194 __le16 rept_wds_wcid;
195 u8 nbuf;
196 __le32 buf[MT_TXP_MAX_BUF_NUM];
197 __le16 len[MT_TXP_MAX_BUF_NUM];
198 } __packed __aligned(4);
199
200 struct mt7921_tx_free {
201 __le16 rx_byte_cnt;
202 __le16 ctrl;
203 u8 txd_cnt;
204 u8 rsv[3];
205 __le32 info[];
206 } __packed __aligned(4);
207
208 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
209 #define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
210 #define MT_TX_FREE_LATENCY GENMASK(12, 0)
211 /* 0: success, others: dropped */
212 #define MT_TX_FREE_STATUS GENMASK(14, 13)
213 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
214 #define MT_TX_FREE_PAIR BIT(31)
215 /* will support this field in further revision */
216 #define MT_TX_FREE_RATE GENMASK(13, 0)
217
218 static inline struct mt7921_txp_common *
mt7921_txwi_to_txp(struct mt76_dev * dev,struct mt76_txwi_cache * t)219 mt7921_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
220 {
221 u8 *txwi;
222
223 if (!t)
224 return NULL;
225
226 txwi = mt76_get_txwi_ptr(dev, t);
227
228 return (struct mt7921_txp_common *)(txwi + MT_TXD_SIZE);
229 }
230
231 #define MT_HW_TXP_MAX_MSDU_NUM 4
232 #define MT_HW_TXP_MAX_BUF_NUM 4
233
234 #define MT_MSDU_ID_VALID BIT(15)
235
236 #define MT_TXD_LEN_MASK GENMASK(11, 0)
237 #define MT_TXD_LEN_MSDU_LAST BIT(14)
238 #define MT_TXD_LEN_AMSDU_LAST BIT(15)
239 #define MT_TXD_LEN_LAST BIT(15)
240
241 struct mt7921_txp_ptr {
242 __le32 buf0;
243 __le16 len0;
244 __le16 len1;
245 __le32 buf1;
246 } __packed __aligned(4);
247
248 struct mt7921_hw_txp {
249 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
250 struct mt7921_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
251 } __packed __aligned(4);
252
253 struct mt7921_txp_common {
254 union {
255 struct mt7921_hw_txp hw;
256 };
257 };
258
259 #define MT_WTBL_TXRX_CAP_RATE_OFFSET 7
260 #define MT_WTBL_TXRX_RATE_G2_HE 24
261 #define MT_WTBL_TXRX_RATE_G2 12
262
263 #define MT_WTBL_AC0_CTT_OFFSET 20
264
mt7921_mac_wtbl_lmac_addr(int idx,u8 offset)265 static inline u32 mt7921_mac_wtbl_lmac_addr(int idx, u8 offset)
266 {
267 return MT_WTBL_LMAC_OFFS(idx, 0) + offset * 4;
268 }
269
270 #endif
271