1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2022 MediaTek Inc. */
3 
4 #ifndef __MT76_CONNAC2_MAC_H
5 #define __MT76_CONNAC2_MAC_H
6 
7 enum tx_header_format {
8 	MT_HDR_FORMAT_802_3,
9 	MT_HDR_FORMAT_CMD,
10 	MT_HDR_FORMAT_802_11,
11 	MT_HDR_FORMAT_802_11_EXT,
12 };
13 
14 enum tx_pkt_type {
15 	MT_TX_TYPE_CT,
16 	MT_TX_TYPE_SF,
17 	MT_TX_TYPE_CMD,
18 	MT_TX_TYPE_FW,
19 };
20 
21 enum {
22 	MT_CTX0,
23 	MT_HIF0 = 0x0,
24 
25 	MT_LMAC_AC00 = 0x0,
26 	MT_LMAC_AC01,
27 	MT_LMAC_AC02,
28 	MT_LMAC_AC03,
29 	MT_LMAC_ALTX0 = 0x10,
30 	MT_LMAC_BMC0,
31 	MT_LMAC_BCN0,
32 	MT_LMAC_PSMP0,
33 };
34 
35 #define MT_TXD_SIZE			(8 * 4)
36 #define MT_SDIO_TXD_SIZE		(MT_TXD_SIZE + 8 * 4)
37 #define MT_SDIO_TAIL_SIZE		8
38 #define MT_SDIO_HDR_SIZE		4
39 #define MT_USB_TAIL_SIZE		4
40 
41 #define MT_TXD0_Q_IDX			GENMASK(31, 25)
42 #define MT_TXD0_PKT_FMT			GENMASK(24, 23)
43 #define MT_TXD0_ETH_TYPE_OFFSET		GENMASK(22, 16)
44 #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
45 
46 #define MT_TXD1_LONG_FORMAT		BIT(31)
47 #define MT_TXD1_TGID			BIT(30)
48 #define MT_TXD1_OWN_MAC			GENMASK(29, 24)
49 #define MT_TXD1_AMSDU			BIT(23)
50 #define MT_TXD1_TID			GENMASK(22, 20)
51 #define MT_TXD1_HDR_PAD			GENMASK(19, 18)
52 #define MT_TXD1_HDR_FORMAT		GENMASK(17, 16)
53 #define MT_TXD1_HDR_INFO		GENMASK(15, 11)
54 #define MT_TXD1_ETH_802_3		BIT(15)
55 #define MT_TXD1_VTA			BIT(10)
56 #define MT_TXD1_WLAN_IDX		GENMASK(9, 0)
57 
58 #define MT_TXD2_FIX_RATE		BIT(31)
59 #define MT_TXD2_FIXED_RATE		BIT(30)
60 #define MT_TXD2_POWER_OFFSET		GENMASK(29, 24)
61 #define MT_TXD2_MAX_TX_TIME		GENMASK(23, 16)
62 #define MT_TXD2_FRAG			GENMASK(15, 14)
63 #define MT_TXD2_HTC_VLD			BIT(13)
64 #define MT_TXD2_DURATION		BIT(12)
65 #define MT_TXD2_BIP			BIT(11)
66 #define MT_TXD2_MULTICAST		BIT(10)
67 #define MT_TXD2_RTS			BIT(9)
68 #define MT_TXD2_SOUNDING		BIT(8)
69 #define MT_TXD2_NDPA			BIT(7)
70 #define MT_TXD2_NDP			BIT(6)
71 #define MT_TXD2_FRAME_TYPE		GENMASK(5, 4)
72 #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
73 
74 #define MT_TXD3_SN_VALID		BIT(31)
75 #define MT_TXD3_PN_VALID		BIT(30)
76 #define MT_TXD3_SW_POWER_MGMT		BIT(29)
77 #define MT_TXD3_BA_DISABLE		BIT(28)
78 #define MT_TXD3_SEQ			GENMASK(27, 16)
79 #define MT_TXD3_REM_TX_COUNT		GENMASK(15, 11)
80 #define MT_TXD3_TX_COUNT		GENMASK(10, 6)
81 #define MT_TXD3_TIMING_MEASURE		BIT(5)
82 #define MT_TXD3_DAS			BIT(4)
83 #define MT_TXD3_EEOSP			BIT(3)
84 #define MT_TXD3_EMRD			BIT(2)
85 #define MT_TXD3_PROTECT_FRAME		BIT(1)
86 #define MT_TXD3_NO_ACK			BIT(0)
87 
88 #define MT_TXD4_PN_LOW			GENMASK(31, 0)
89 
90 #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
91 #define MT_TXD5_MD			BIT(15)
92 #define MT_TXD5_ADD_BA			BIT(14)
93 #define MT_TXD5_TX_STATUS_HOST		BIT(10)
94 #define MT_TXD5_TX_STATUS_MCU		BIT(9)
95 #define MT_TXD5_TX_STATUS_FMT		BIT(8)
96 #define MT_TXD5_PID			GENMASK(7, 0)
97 
98 #define MT_TXD6_TX_IBF			BIT(31)
99 #define MT_TXD6_TX_EBF			BIT(30)
100 #define MT_TXD6_TX_RATE			GENMASK(29, 16)
101 #define MT_TXD6_SGI			GENMASK(15, 14)
102 #define MT_TXD6_HELTF			GENMASK(13, 12)
103 #define MT_TXD6_LDPC			BIT(11)
104 #define MT_TXD6_SPE_ID_IDX		BIT(10)
105 #define MT_TXD6_ANT_ID			GENMASK(7, 4)
106 #define MT_TXD6_DYN_BW			BIT(3)
107 #define MT_TXD6_FIXED_BW		BIT(2)
108 #define MT_TXD6_BW			GENMASK(1, 0)
109 
110 #define MT_TXD7_TXD_LEN			GENMASK(31, 30)
111 #define MT_TXD7_UDP_TCP_SUM		BIT(29)
112 #define MT_TXD7_IP_SUM			BIT(28)
113 #define MT_TXD7_TYPE			GENMASK(21, 20)
114 #define MT_TXD7_SUB_TYPE		GENMASK(19, 16)
115 
116 #define MT_TXD7_PSE_FID			GENMASK(27, 16)
117 #define MT_TXD7_SPE_IDX			GENMASK(15, 11)
118 #define MT_TXD7_HW_AMSDU		BIT(10)
119 #define MT_TXD7_TX_TIME			GENMASK(9, 0)
120 
121 #define MT_TXD8_L_TYPE			GENMASK(5, 4)
122 #define MT_TXD8_L_SUB_TYPE		GENMASK(3, 0)
123 
124 #define MT_TX_RATE_STBC			BIT(13)
125 #define MT_TX_RATE_NSS			GENMASK(12, 10)
126 #define MT_TX_RATE_MODE			GENMASK(9, 6)
127 #define MT_TX_RATE_SU_EXT_TONE		BIT(5)
128 #define MT_TX_RATE_DCM			BIT(4)
129 /* VHT/HE only use bits 0-3 */
130 #define MT_TX_RATE_IDX			GENMASK(5, 0)
131 
132 #define MT_TXS0_FIXED_RATE		BIT(31)
133 #define MT_TXS0_BW			GENMASK(30, 29)
134 #define MT_TXS0_TID			GENMASK(28, 26)
135 #define MT_TXS0_AMPDU			BIT(25)
136 #define MT_TXS0_TXS_FORMAT		GENMASK(24, 23)
137 #define MT_TXS0_BA_ERROR		BIT(22)
138 #define MT_TXS0_PS_FLAG			BIT(21)
139 #define MT_TXS0_TXOP_TIMEOUT		BIT(20)
140 #define MT_TXS0_BIP_ERROR		BIT(19)
141 
142 #define MT_TXS0_QUEUE_TIMEOUT		BIT(18)
143 #define MT_TXS0_RTS_TIMEOUT		BIT(17)
144 #define MT_TXS0_ACK_TIMEOUT		BIT(16)
145 #define MT_TXS0_ACK_ERROR_MASK		GENMASK(18, 16)
146 
147 #define MT_TXS0_TX_STATUS_HOST		BIT(15)
148 #define MT_TXS0_TX_STATUS_MCU		BIT(14)
149 #define MT_TXS0_TX_RATE			GENMASK(13, 0)
150 
151 #define MT_TXS1_SEQNO			GENMASK(31, 20)
152 #define MT_TXS1_RESP_RATE		GENMASK(19, 16)
153 #define MT_TXS1_RXV_SEQNO		GENMASK(15, 8)
154 #define MT_TXS1_TX_POWER_DBM		GENMASK(7, 0)
155 
156 #define MT_TXS2_BF_STATUS		GENMASK(31, 30)
157 #define MT_TXS2_LAST_TX_RATE		GENMASK(29, 27)
158 #define MT_TXS2_SHARED_ANTENNA		BIT(26)
159 #define MT_TXS2_WCID			GENMASK(25, 16)
160 #define MT_TXS2_TX_DELAY		GENMASK(15, 0)
161 
162 #define MT_TXS3_PID			GENMASK(31, 24)
163 #define MT_TXS3_ANT_ID			GENMASK(23, 0)
164 
165 #define MT_TXS4_TIMESTAMP		GENMASK(31, 0)
166 
167 #endif /* __MT76_CONNAC2_MAC_H */
168