1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT7915_MAC_H
5 #define __MT7915_MAC_H
6
7 #include "../mt76_connac2_mac.h"
8
9 #define MT_CT_PARSE_LEN 72
10 #define MT_CT_DMA_BUF_NUM 2
11
12 #define MT_RXD0_LENGTH GENMASK(15, 0)
13 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
14
15 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
16 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
17 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
18
19 enum rx_pkt_type {
20 PKT_TYPE_TXS,
21 PKT_TYPE_TXRXV,
22 PKT_TYPE_NORMAL,
23 PKT_TYPE_RX_DUP_RFB,
24 PKT_TYPE_RX_TMR,
25 PKT_TYPE_RETRIEVE,
26 PKT_TYPE_TXRX_NOTIFY,
27 PKT_TYPE_RX_EVENT,
28 PKT_TYPE_RX_FW_MONITOR = 0x0c,
29 PKT_TYPE_TXRX_NOTIFY_V0 = 0x18,
30 };
31
32 /* RXD DW1 */
33 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
34 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
35 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
36 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
37 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
38 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
39 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
40 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
41 #define MT_RXD1_NORMAL_CM BIT(23)
42 #define MT_RXD1_NORMAL_CLM BIT(24)
43 #define MT_RXD1_NORMAL_ICV_ERR BIT(25)
44 #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
45 #define MT_RXD1_NORMAL_FCS_ERR BIT(27)
46 #define MT_RXD1_NORMAL_BAND_IDX BIT(28)
47 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
48 #define MT_RXD1_NORMAL_ADD_OM BIT(30)
49 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
50
51 /* RXD DW2 */
52 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
53 #define MT_RXD2_NORMAL_CO_ANT BIT(6)
54 #define MT_RXD2_NORMAL_BF_CQI BIT(7)
55 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
56 #define MT_RXD2_NORMAL_HDR_TRANS BIT(13)
57 #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)
58 #define MT_RXD2_NORMAL_TID GENMASK(19, 16)
59 #define MT_RXD2_NORMAL_MU_BAR BIT(21)
60 #define MT_RXD2_NORMAL_SW_BIT BIT(22)
61 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
62 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
63 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
64 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
65 #define MT_RXD2_NORMAL_FRAG BIT(27)
66 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
67 #define MT_RXD2_NORMAL_NDATA BIT(29)
68 #define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
69 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
70
71 /* RXD DW3 */
72 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
73 #define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
74 #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
75 #define MT_RXD3_NORMAL_U2M BIT(0)
76 #define MT_RXD3_NORMAL_HTC_VLD BIT(0)
77 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(19)
78 #define MT_RXD3_NORMAL_BEACON_MC BIT(20)
79 #define MT_RXD3_NORMAL_BEACON_UC BIT(21)
80 #define MT_RXD3_NORMAL_AMSDU BIT(22)
81 #define MT_RXD3_NORMAL_MESH BIT(23)
82 #define MT_RXD3_NORMAL_MHCP BIT(24)
83 #define MT_RXD3_NORMAL_NO_INFO_WB BIT(25)
84 #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS BIT(26)
85 #define MT_RXD3_NORMAL_POWER_SAVE_STAT BIT(27)
86 #define MT_RXD3_NORMAL_MORE BIT(28)
87 #define MT_RXD3_NORMAL_UNWANT BIT(29)
88 #define MT_RXD3_NORMAL_RX_DROP BIT(30)
89 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
90
91 /* RXD DW4 */
92 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
93 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
94 #define MT_RXD4_MID_AMSDU_FRAME BIT(1)
95 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
96
97 #define MT_RXD4_NORMAL_PATTERN_DROP BIT(9)
98 #define MT_RXD4_NORMAL_CLS BIT(10)
99 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
100 #define MT_RXD4_NORMAL_MAGIC_PKT BIT(13)
101 #define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
102 #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
103 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
104 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
105
106 #define MT_RXV_HDR_BAND_IDX BIT(24)
107
108 /* RXD GROUP4 */
109 #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0)
110 #define MT_RXD6_TA_LO GENMASK(31, 16)
111
112 #define MT_RXD7_TA_HI GENMASK(31, 0)
113
114 #define MT_RXD8_SEQ_CTRL GENMASK(15, 0)
115 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
116
117 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
118
119 /* P-RXV */
120 #define MT_PRXV_TX_RATE GENMASK(6, 0)
121 #define MT_PRXV_TX_DCM BIT(4)
122 #define MT_PRXV_TX_ER_SU_106T BIT(5)
123 #define MT_PRXV_NSTS GENMASK(9, 7)
124 #define MT_PRXV_TXBF BIT(10)
125 #define MT_PRXV_HT_AD_CODE BIT(11)
126 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
127 #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
128 #define MT_PRXV_RCPI3 GENMASK(31, 24)
129 #define MT_PRXV_RCPI2 GENMASK(23, 16)
130 #define MT_PRXV_RCPI1 GENMASK(15, 8)
131 #define MT_PRXV_RCPI0 GENMASK(7, 0)
132 #define MT_PRXV_HT_SHORT_GI GENMASK(16, 15)
133 #define MT_PRXV_HT_STBC GENMASK(23, 22)
134 #define MT_PRXV_TX_MODE GENMASK(27, 24)
135 #define MT_PRXV_FRAME_MODE GENMASK(14, 12)
136 #define MT_PRXV_DCM BIT(17)
137 #define MT_PRXV_NUM_RX BIT(20, 18)
138
139 /* C-RXV */
140 #define MT_CRXV_HT_STBC GENMASK(1, 0)
141 #define MT_CRXV_TX_MODE GENMASK(7, 4)
142 #define MT_CRXV_FRAME_MODE GENMASK(10, 8)
143 #define MT_CRXV_HT_SHORT_GI GENMASK(14, 13)
144 #define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17)
145 #define MT_CRXV_HE_LDPC_EXT_SYM BIT(20)
146 #define MT_CRXV_HE_PE_DISAMBIG BIT(23)
147 #define MT_CRXV_HE_NUM_USER GENMASK(30, 24)
148 #define MT_CRXV_HE_UPLINK BIT(31)
149 #define MT_CRXV_HE_RU0 GENMASK(7, 0)
150 #define MT_CRXV_HE_RU1 GENMASK(15, 8)
151 #define MT_CRXV_HE_RU2 GENMASK(23, 16)
152 #define MT_CRXV_HE_RU3 GENMASK(31, 24)
153
154 #define MT_CRXV_HE_MU_AID GENMASK(30, 20)
155
156 #define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
157 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
158 #define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
159 #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
160
161 #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
162 #define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)
163 #define MT_CRXV_HE_BEAM_CHNG BIT(13)
164 #define MT_CRXV_HE_DOPPLER BIT(16)
165
166 #define MT_CRXV_SNR GENMASK(18, 13)
167 #define MT_CRXV_FOE_LO GENMASK(31, 19)
168 #define MT_CRXV_FOE_HI GENMASK(6, 0)
169 #define MT_CRXV_FOE_SHIFT 13
170
171 enum tx_port_idx {
172 MT_TX_PORT_IDX_LMAC,
173 MT_TX_PORT_IDX_MCU
174 };
175
176 enum tx_mcu_port_q_idx {
177 MT_TX_MCU_PORT_RX_Q0 = 0x20,
178 MT_TX_MCU_PORT_RX_Q1,
179 MT_TX_MCU_PORT_RX_Q2,
180 MT_TX_MCU_PORT_RX_Q3,
181 MT_TX_MCU_PORT_RX_FWDL = 0x3e
182 };
183
184 #define MT_CT_INFO_APPLY_TXD BIT(0)
185 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
186 #define MT_CT_INFO_MGMT_FRAME BIT(2)
187 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
188 #define MT_CT_INFO_HSR2_TX BIT(4)
189 #define MT_CT_INFO_FROM_HOST BIT(7)
190
191 #define MT_TXP_MAX_BUF_NUM 6
192
193 struct mt7915_txp {
194 __le16 flags;
195 __le16 token;
196 u8 bss_idx;
197 __le16 rept_wds_wcid;
198 u8 nbuf;
199 __le32 buf[MT_TXP_MAX_BUF_NUM];
200 __le16 len[MT_TXP_MAX_BUF_NUM];
201 } __packed __aligned(4);
202
203 struct mt7915_tx_free {
204 __le16 rx_byte_cnt;
205 __le16 ctrl;
206 __le32 txd;
207 __le32 info[];
208 } __packed __aligned(4);
209
210 #define MT_TX_FREE_VER GENMASK(18, 16)
211 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
212 #define MT_TX_FREE_MSDU_CNT_V0 GENMASK(6, 0)
213 #define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
214 #define MT_TX_FREE_LATENCY GENMASK(12, 0)
215 /* 0: success, others: dropped */
216 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
217 #define MT_TX_FREE_PAIR BIT(31)
218 #define MT_TX_FREE_MPDU_HEADER BIT(30)
219 #define MT_TX_FREE_MSDU_ID_V3 GENMASK(14, 0)
220
221 /* will support this field in further revision */
222 #define MT_TX_FREE_RATE GENMASK(13, 0)
223
224 #define MT_TXS5_F0_FINAL_MPDU BIT(31)
225 #define MT_TXS5_F0_QOS BIT(30)
226 #define MT_TXS5_F0_TX_COUNT GENMASK(29, 25)
227 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
228 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
229 #define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0)
230
231 #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
232 #define MT_TXS6_F0_NOISE_2 GENMASK(23, 16)
233 #define MT_TXS6_F0_NOISE_1 GENMASK(15, 8)
234 #define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)
235 #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
236 #define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0)
237
238 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
239 #define MT_TXS7_F0_RCPI_2 GENMASK(23, 16)
240 #define MT_TXS7_F0_RCPI_1 GENMASK(15, 8)
241 #define MT_TXS7_F0_RCPI_0 GENMASK(7, 0)
242 #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)
243 #define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0)
244
245 struct mt7915_dfs_pulse {
246 u32 max_width; /* us */
247 int max_pwr; /* dbm */
248 int min_pwr; /* dbm */
249 u32 min_stgr_pri; /* us */
250 u32 max_stgr_pri; /* us */
251 u32 min_cr_pri; /* us */
252 u32 max_cr_pri; /* us */
253 };
254
255 struct mt7915_dfs_pattern {
256 u8 enb;
257 u8 stgr;
258 u8 min_crpn;
259 u8 max_crpn;
260 u8 min_crpr;
261 u8 min_pw;
262 u32 min_pri;
263 u32 max_pri;
264 u8 max_pw;
265 u8 min_crbn;
266 u8 max_crbn;
267 u8 min_stgpn;
268 u8 max_stgpn;
269 u8 min_stgpr;
270 u8 rsv[2];
271 u32 min_stgpr_diff;
272 } __packed;
273
274 struct mt7915_dfs_radar_spec {
275 struct mt7915_dfs_pulse pulse_th;
276 struct mt7915_dfs_pattern radar_pattern[16];
277 };
278
279 static inline struct mt7915_txp *
mt7915_txwi_to_txp(struct mt76_dev * dev,struct mt76_txwi_cache * t)280 mt7915_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
281 {
282 u8 *txwi;
283
284 if (!t)
285 return NULL;
286
287 txwi = mt76_get_txwi_ptr(dev, t);
288
289 return (struct mt7915_txp *)(txwi + MT_TXD_SIZE);
290 }
291
292 #endif
293