1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3 
4 #ifndef __MT7915_REGS_H
5 #define __MT7915_REGS_H
6 
7 struct __map {
8 	u32 phys;
9 	u32 maps;
10 	u32 size;
11 };
12 
13 /* used to differentiate between generations */
14 struct mt7915_reg_desc {
15 	const u32 *reg_rev;
16 	const u32 *offs_rev;
17 	const struct __map *map;
18 	u32 map_size;
19 };
20 
21 enum reg_rev {
22 	INT_SOURCE_CSR,
23 	INT_MASK_CSR,
24 	INT1_SOURCE_CSR,
25 	INT1_MASK_CSR,
26 	INT_MCU_CMD_SOURCE,
27 	INT_MCU_CMD_EVENT,
28 	WFDMA0_ADDR,
29 	WFDMA0_PCIE1_ADDR,
30 	WFDMA_EXT_CSR_ADDR,
31 	CBTOP1_PHY_END,
32 	INFRA_MCU_ADDR_END,
33 	FW_EXCEPTION_ADDR,
34 	SWDEF_BASE_ADDR,
35 	__MT_REG_MAX,
36 };
37 
38 enum offs_rev {
39 	TMAC_CDTR,
40 	TMAC_ODTR,
41 	TMAC_ATCR,
42 	TMAC_TRCR0,
43 	TMAC_ICR0,
44 	TMAC_ICR1,
45 	TMAC_CTCR0,
46 	TMAC_TFCR0,
47 	MDP_BNRCFR0,
48 	MDP_BNRCFR1,
49 	ARB_DRNGR0,
50 	ARB_SCR,
51 	RMAC_MIB_AIRTIME14,
52 	AGG_AWSCR0,
53 	AGG_PCR0,
54 	AGG_ACR0,
55 	AGG_MRCR,
56 	AGG_ATCR1,
57 	AGG_ATCR3,
58 	LPON_UTTR0,
59 	LPON_UTTR1,
60 	LPON_FRCR,
61 	MIB_SDR3,
62 	MIB_SDR4,
63 	MIB_SDR5,
64 	MIB_SDR7,
65 	MIB_SDR8,
66 	MIB_SDR9,
67 	MIB_SDR10,
68 	MIB_SDR11,
69 	MIB_SDR12,
70 	MIB_SDR13,
71 	MIB_SDR14,
72 	MIB_SDR15,
73 	MIB_SDR16,
74 	MIB_SDR17,
75 	MIB_SDR18,
76 	MIB_SDR19,
77 	MIB_SDR20,
78 	MIB_SDR21,
79 	MIB_SDR22,
80 	MIB_SDR23,
81 	MIB_SDR24,
82 	MIB_SDR25,
83 	MIB_SDR27,
84 	MIB_SDR28,
85 	MIB_SDR29,
86 	MIB_SDRVEC,
87 	MIB_SDR31,
88 	MIB_SDR32,
89 	MIB_SDRMUBF,
90 	MIB_DR8,
91 	MIB_DR9,
92 	MIB_DR11,
93 	MIB_MB_SDR0,
94 	MIB_MB_SDR1,
95 	TX_AGG_CNT,
96 	TX_AGG_CNT2,
97 	MIB_ARNG,
98 	WTBLON_TOP_WDUCR,
99 	WTBL_UPDATE,
100 	PLE_FL_Q_EMPTY,
101 	PLE_FL_Q_CTRL,
102 	PLE_AC_QEMPTY,
103 	PLE_FREEPG_CNT,
104 	PLE_FREEPG_HEAD_TAIL,
105 	PLE_PG_HIF_GROUP,
106 	PLE_HIF_PG_INFO,
107 	AC_OFFSET,
108 	ETBF_PAR_RPT0,
109 	__MT_OFFS_MAX,
110 };
111 
112 #define __REG(id)			(dev->reg.reg_rev[(id)])
113 #define __OFFS(id)			(dev->reg.offs_rev[(id)])
114 
115 /* MCU WFDMA0 */
116 #define MT_MCU_WFDMA0_BASE		0x2000
117 #define MT_MCU_WFDMA0(ofs)		(MT_MCU_WFDMA0_BASE + (ofs))
118 
119 #define MT_MCU_WFDMA0_DUMMY_CR		MT_MCU_WFDMA0(0x120)
120 
121 /* MCU WFDMA1 */
122 #define MT_MCU_WFDMA1_BASE		0x3000
123 #define MT_MCU_WFDMA1(ofs)		(MT_MCU_WFDMA1_BASE + (ofs))
124 
125 #define MT_MCU_INT_EVENT		__REG(INT_MCU_CMD_EVENT)
126 #define MT_MCU_INT_EVENT_DMA_STOPPED	BIT(0)
127 #define MT_MCU_INT_EVENT_DMA_INIT	BIT(1)
128 #define MT_MCU_INT_EVENT_SER_TRIGGER	BIT(2)
129 #define MT_MCU_INT_EVENT_RESET_DONE	BIT(3)
130 
131 /* PLE */
132 #define MT_PLE_BASE			0x820c0000
133 #define MT_PLE(ofs)			(MT_PLE_BASE + (ofs))
134 
135 #define MT_FL_Q_EMPTY			MT_PLE(__OFFS(PLE_FL_Q_EMPTY))
136 #define MT_FL_Q0_CTRL			MT_PLE(__OFFS(PLE_FL_Q_CTRL))
137 #define MT_FL_Q2_CTRL			MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
138 #define MT_FL_Q3_CTRL			MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
139 
140 #define MT_PLE_FREEPG_CNT		MT_PLE(__OFFS(PLE_FREEPG_CNT))
141 #define MT_PLE_FREEPG_HEAD_TAIL		MT_PLE(__OFFS(PLE_FREEPG_HEAD_TAIL))
142 #define MT_PLE_PG_HIF_GROUP		MT_PLE(__OFFS(PLE_PG_HIF_GROUP))
143 #define MT_PLE_HIF_PG_INFO		MT_PLE(__OFFS(PLE_HIF_PG_INFO))
144 
145 #define MT_PLE_AC_QEMPTY(ac, n)		MT_PLE(__OFFS(PLE_AC_QEMPTY) +	\
146 					       __OFFS(AC_OFFSET) *	\
147 					       (ac) + ((n) << 2))
148 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n)	MT_PLE(0x10e0 + ((n) << 2))
149 
150 #define MT_PSE_BASE			0x820c8000
151 #define MT_PSE(ofs)			(MT_PSE_BASE + (ofs))
152 
153 /* WF MDP TOP */
154 #define MT_MDP_BASE			0x820cd000
155 #define MT_MDP(ofs)			(MT_MDP_BASE + (ofs))
156 
157 #define MT_MDP_DCR0			MT_MDP(0x000)
158 #define MT_MDP_DCR0_DAMSDU_EN		BIT(15)
159 
160 #define MT_MDP_DCR1			MT_MDP(0x004)
161 #define MT_MDP_DCR1_MAX_RX_LEN		GENMASK(15, 3)
162 
163 #define MT_MDP_DCR2			MT_MDP(0x0e8)
164 #define MT_MDP_DCR2_RX_TRANS_SHORT	BIT(2)
165 
166 #define MT_MDP_BNRCFR0(_band)		MT_MDP(__OFFS(MDP_BNRCFR0) + \
167 					       ((_band) << 8))
168 #define MT_MDP_RCFR0_MCU_RX_MGMT	GENMASK(5, 4)
169 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR	GENMASK(7, 6)
170 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR	GENMASK(9, 8)
171 
172 #define MT_MDP_BNRCFR1(_band)		MT_MDP(__OFFS(MDP_BNRCFR1) + \
173 					       ((_band) << 8))
174 #define MT_MDP_RCFR1_MCU_RX_BYPASS	GENMASK(23, 22)
175 #define MT_MDP_RCFR1_RX_DROPPED_UCAST	GENMASK(28, 27)
176 #define MT_MDP_RCFR1_RX_DROPPED_MCAST	GENMASK(30, 29)
177 #define MT_MDP_TO_HIF			0
178 #define MT_MDP_TO_WM			1
179 
180 /* TRB: band 0(0x820e1000), band 1(0x820f1000) */
181 #define MT_WF_TRB_BASE(_band)		((_band) ? 0x820f1000 : 0x820e1000)
182 #define MT_WF_TRB(_band, ofs)		(MT_WF_TRB_BASE(_band) + (ofs))
183 
184 #define MT_TRB_RXPSR0(_band)		MT_WF_TRB(_band, 0x03c)
185 #define MT_TRB_RXPSR0_RX_WTBL_PTR	GENMASK(25, 16)
186 #define MT_TRB_RXPSR0_RX_RMAC_PTR	GENMASK(9, 0)
187 
188 /* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
189 #define MT_WF_TMAC_BASE(_band)		((_band) ? 0x820f4000 : 0x820e4000)
190 #define MT_WF_TMAC(_band, ofs)		(MT_WF_TMAC_BASE(_band) + (ofs))
191 
192 #define MT_TMAC_TCR0(_band)		MT_WF_TMAC(_band, 0)
193 #define MT_TMAC_TCR0_TX_BLINK		GENMASK(7, 6)
194 #define MT_TMAC_TCR0_TBTT_STOP_CTRL	BIT(25)
195 
196 #define MT_TMAC_CDTR(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_CDTR))
197  #define MT_TMAC_ODTR(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_ODTR))
198 #define MT_TIMEOUT_VAL_PLCP		GENMASK(15, 0)
199 #define MT_TIMEOUT_VAL_CCA		GENMASK(31, 16)
200 
201 #define MT_TMAC_ATCR(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_ATCR))
202 #define MT_TMAC_ATCR_TXV_TOUT		GENMASK(7, 0)
203 
204 #define MT_TMAC_TRCR0(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_TRCR0))
205 #define MT_TMAC_TRCR0_TR2T_CHK		GENMASK(8, 0)
206 #define MT_TMAC_TRCR0_I2T_CHK		GENMASK(24, 16)
207 
208 #define MT_TMAC_ICR0(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_ICR0))
209 #define MT_IFS_EIFS_OFDM		GENMASK(8, 0)
210 #define MT_IFS_RIFS			GENMASK(14, 10)
211 #define MT_IFS_SIFS			GENMASK(22, 16)
212 #define MT_IFS_SLOT			GENMASK(30, 24)
213 
214 #define MT_TMAC_ICR1(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_ICR1))
215 #define MT_IFS_EIFS_CCK			GENMASK(8, 0)
216 
217 #define MT_TMAC_CTCR0(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_CTCR0))
218 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME		GENMASK(5, 0)
219 #define MT_TMAC_CTCR0_INS_DDLMT_EN		BIT(17)
220 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN	BIT(18)
221 
222 #define MT_TMAC_TFCR0(_band)		MT_WF_TMAC(_band, __OFFS(TMAC_TFCR0))
223 
224 /* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */
225 #define MT_WF_DMA_BASE(_band)		((_band) ? 0x820f7000 : 0x820e7000)
226 #define MT_WF_DMA(_band, ofs)		(MT_WF_DMA_BASE(_band) + (ofs))
227 
228 #define MT_DMA_DCR0(_band)		MT_WF_DMA(_band, 0x000)
229 #define MT_DMA_DCR0_MAX_RX_LEN		GENMASK(15, 3)
230 #define MT_DMA_DCR0_RXD_G5_EN		BIT(23)
231 
232 /* ETBF: band 0(0x820ea000), band 1(0x820fa000) */
233 #define MT_WF_ETBF_BASE(_band)		((_band) ? 0x820fa000 : 0x820ea000)
234 #define MT_WF_ETBF(_band, ofs)		(MT_WF_ETBF_BASE(_band) + (ofs))
235 
236 #define MT_ETBF_TX_NDP_BFRP(_band)	MT_WF_ETBF(_band, 0x040)
237 #define MT_ETBF_TX_FB_CPL		GENMASK(31, 16)
238 #define MT_ETBF_TX_FB_TRI		GENMASK(15, 0)
239 
240 #define MT_ETBF_PAR_RPT0(_band)		MT_WF_ETBF(_band, __OFFS(ETBF_PAR_RPT0))
241 #define MT_ETBF_PAR_RPT0_FB_BW		GENMASK(7, 6)
242 #define MT_ETBF_PAR_RPT0_FB_NC		GENMASK(5, 3)
243 #define MT_ETBF_PAR_RPT0_FB_NR		GENMASK(2, 0)
244 
245 #define MT_ETBF_TX_APP_CNT(_band)	MT_WF_ETBF(_band, 0x0f0)
246 #define MT_ETBF_TX_IBF_CNT		GENMASK(31, 16)
247 #define MT_ETBF_TX_EBF_CNT		GENMASK(15, 0)
248 
249 #define MT_ETBF_RX_FB_CNT(_band)	MT_WF_ETBF(_band, 0x0f8)
250 #define MT_ETBF_RX_FB_ALL		GENMASK(31, 24)
251 #define MT_ETBF_RX_FB_HE		GENMASK(23, 16)
252 #define MT_ETBF_RX_FB_VHT		GENMASK(15, 8)
253 #define MT_ETBF_RX_FB_HT		GENMASK(7, 0)
254 
255 /* LPON: band 0(0x820eb000), band 1(0x820fb000) */
256 #define MT_WF_LPON_BASE(_band)		((_band) ? 0x820fb000 : 0x820eb000)
257 #define MT_WF_LPON(_band, ofs)		(MT_WF_LPON_BASE(_band) + (ofs))
258 
259 #define MT_LPON_UTTR0(_band)		MT_WF_LPON(_band, __OFFS(LPON_UTTR0))
260 #define MT_LPON_UTTR1(_band)		MT_WF_LPON(_band, __OFFS(LPON_UTTR1))
261 #define MT_LPON_FRCR(_band)		MT_WF_LPON(_band, __OFFS(LPON_FRCR))
262 
263 #define MT_LPON_TCR(_band, n)		MT_WF_LPON(_band, 0x0a8 +	\
264 						   (((n) * 4) << 1))
265 #define MT_LPON_TCR_MT7916(_band, n)	MT_WF_LPON(_band, 0x0a8 +	\
266 						   (((n) * 4) << 4))
267 #define MT_LPON_TCR_SW_MODE		GENMASK(1, 0)
268 #define MT_LPON_TCR_SW_WRITE		BIT(0)
269 #define MT_LPON_TCR_SW_ADJUST		BIT(1)
270 #define MT_LPON_TCR_SW_READ		GENMASK(1, 0)
271 
272 /* MIB: band 0(0x820ed000), band 1(0x820fd000) */
273 /* These counters are (mostly?) clear-on-read.  So, some should not
274  * be read at all in case firmware is already reading them.  These
275  * are commented with 'DNR' below.  The DNR stats will be read by querying
276  * the firmware API for the appropriate message.  For counters the driver
277  * does read, the driver should accumulate the counters.
278  */
279 #define MT_WF_MIB_BASE(_band)		((_band) ? 0x820fd000 : 0x820ed000)
280 #define MT_WF_MIB(_band, ofs)		(MT_WF_MIB_BASE(_band) + (ofs))
281 
282 #define MT_MIB_SDR0(_band)		MT_WF_MIB(_band, 0x010)
283 #define MT_MIB_SDR0_BERACON_TX_CNT_MASK	GENMASK(15, 0)
284 
285 #define MT_MIB_SDR3(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR3))
286 #define MT_MIB_SDR3_FCS_ERR_MASK	GENMASK(15, 0)
287 #define MT_MIB_SDR3_FCS_ERR_MASK_MT7916	GENMASK(31, 16)
288 
289 #define MT_MIB_SDR4(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR4))
290 #define MT_MIB_SDR4_RX_FIFO_FULL_MASK	GENMASK(15, 0)
291 
292 /* rx mpdu counter, full 32 bits */
293 #define MT_MIB_SDR5(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR5))
294 
295 #define MT_MIB_SDR6(_band)		MT_WF_MIB(_band, 0x020)
296 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK	GENMASK(15, 0)
297 
298 #define MT_MIB_SDR7(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR7))
299 #define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK	GENMASK(15, 0)
300 
301 #define MT_MIB_SDR8(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR8))
302 #define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK	GENMASK(15, 0)
303 
304 /* aka CCA_NAV_TX_TIME */
305 #define MT_MIB_SDR9_DNR(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR9))
306 #define MT_MIB_SDR9_CCA_BUSY_TIME_MASK		GENMASK(23, 0)
307 
308 #define MT_MIB_SDR10_DNR(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR10))
309 #define MT_MIB_SDR10_MRDY_COUNT_MASK		GENMASK(25, 0)
310 #define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916	GENMASK(31, 0)
311 
312 #define MT_MIB_SDR11(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR11))
313 #define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK	GENMASK(15, 0)
314 
315 /* tx ampdu cnt, full 32 bits */
316 #define MT_MIB_SDR12(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR12))
317 
318 #define MT_MIB_SDR13(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR13))
319 #define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK	GENMASK(15, 0)
320 
321 /* counts all mpdus in ampdu, regardless of success */
322 #define MT_MIB_SDR14(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR14))
323 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK	GENMASK(23, 0)
324 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916	GENMASK(31, 0)
325 
326 /* counts all successfully tx'd mpdus in ampdu */
327 #define MT_MIB_SDR15(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR15))
328 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK	GENMASK(23, 0)
329 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916	GENMASK(31, 0)
330 
331 /* in units of 'us' */
332 #define MT_MIB_SDR16_DNR(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR16))
333 #define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK	GENMASK(23, 0)
334 
335 #define MT_MIB_SDR17_DNR(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR17))
336 #define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK	GENMASK(23, 0)
337 
338 #define MT_MIB_SDR18(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR18))
339 #define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK	GENMASK(23, 0)
340 
341 /* units are us */
342 #define MT_MIB_SDR19_DNR(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR19))
343 #define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK	GENMASK(23, 0)
344 
345 #define MT_MIB_SDR20_DNR(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR20))
346 #define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK	GENMASK(23, 0)
347 
348 #define MT_MIB_SDR21_DNR(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR21))
349 #define MT_MIB_SDR20_GREEN_MDRDY_TIME_MASK	GENMASK(23, 0)
350 
351 /* rx ampdu count, 32-bit */
352 #define MT_MIB_SDR22(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR22))
353 
354 /* rx ampdu bytes count, 32-bit */
355 #define MT_MIB_SDR23(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR23))
356 
357 /* rx ampdu valid subframe count */
358 #define MT_MIB_SDR24(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR24))
359 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK	GENMASK(23, 0)
360 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916	GENMASK(31, 0)
361 
362 /* rx ampdu valid subframe bytes count, 32bits */
363 #define MT_MIB_SDR25(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR25))
364 
365 /* remaining windows protected stats */
366 #define MT_MIB_SDR27(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR27))
367 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK	GENMASK(15, 0)
368 
369 #define MT_MIB_SDR28(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR28))
370 #define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK	GENMASK(15, 0)
371 
372 #define MT_MIB_SDR29(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR29))
373 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK		GENMASK(7, 0)
374 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916	GENMASK(15, 0)
375 
376 #define MT_MIB_SDRVEC(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDRVEC))
377 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK	GENMASK(15, 0)
378 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916	GENMASK(31, 16)
379 
380 /* rx blockack count, 32 bits */
381 #define MT_MIB_SDR31(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR31))
382 
383 #define MT_MIB_SDR32(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDR32))
384 #define MT_MIB_SDR32_TX_PKT_EBF_CNT	GENMASK(15, 0)
385 #define MT_MIB_SDR32_TX_PKT_IBF_CNT	GENMASK(31, 16)
386 
387 #define MT_MIB_SDR33(_band)		MT_WF_MIB(_band, 0x088)
388 #define MT_MIB_SDR33_TX_PKT_IBF_CNT	GENMASK(15, 0)
389 
390 #define MT_MIB_SDRMUBF(_band)		MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF))
391 #define MT_MIB_MU_BF_TX_CNT		GENMASK(15, 0)
392 
393 /* 36, 37 both DNR */
394 
395 #define MT_MIB_DR8(_band)		MT_WF_MIB(_band, __OFFS(MIB_DR8))
396 #define MT_MIB_DR9(_band)		MT_WF_MIB(_band, __OFFS(MIB_DR9))
397 #define MT_MIB_DR11(_band)		MT_WF_MIB(_band, __OFFS(MIB_DR11))
398 
399 #define MT_MIB_MB_SDR0(_band, n)	MT_WF_MIB(_band, __OFFS(MIB_MB_SDR0) + (n))
400 #define MT_MIB_RTS_RETRIES_COUNT_MASK	GENMASK(31, 16)
401 #define MT_MIB_RTS_COUNT_MASK		GENMASK(15, 0)
402 
403 #define MT_MIB_MB_SDR1(_band, n)	MT_WF_MIB(_band, __OFFS(MIB_MB_SDR1) + (n))
404 #define MT_MIB_BA_MISS_COUNT_MASK	GENMASK(15, 0)
405 #define MT_MIB_ACK_FAIL_COUNT_MASK	GENMASK(31, 16)
406 
407 #define MT_MIB_MB_SDR2(_band, n)	MT_WF_MIB(_band, 0x518 + (n))
408 #define MT_MIB_MB_BFTF(_band, n)	MT_WF_MIB(_band, 0x510 + (n))
409 
410 #define MT_TX_AGG_CNT(_band, n)		MT_WF_MIB(_band, __OFFS(TX_AGG_CNT) +	\
411 						  ((n) << 2))
412 #define MT_TX_AGG_CNT2(_band, n)	MT_WF_MIB(_band, __OFFS(TX_AGG_CNT2) +	\
413 						  ((n) << 2))
414 #define MT_MIB_ARNG(_band, n)		MT_WF_MIB(_band, __OFFS(MIB_ARNG) +	\
415 						  ((n) << 2))
416 #define MT_MIB_ARNCR_RANGE(val, n)	(((val) >> ((n) << 3)) & GENMASK(7, 0))
417 
418 #define MT_MIB_BFCR0(_band)		MT_WF_MIB(_band, 0x7b0)
419 #define MT_MIB_BFCR0_RX_FB_HT		GENMASK(15, 0)
420 #define MT_MIB_BFCR0_RX_FB_VHT		GENMASK(31, 16)
421 
422 #define MT_MIB_BFCR1(_band)		MT_WF_MIB(_band, 0x7b4)
423 #define MT_MIB_BFCR1_RX_FB_HE		GENMASK(15, 0)
424 
425 #define MT_MIB_BFCR2(_band)		MT_WF_MIB(_band, 0x7b8)
426 #define MT_MIB_BFCR2_BFEE_TX_FB_TRIG	GENMASK(15, 0)
427 
428 #define MT_MIB_BFCR7(_band)		MT_WF_MIB(_band, 0x7cc)
429 #define MT_MIB_BFCR7_BFEE_TX_FB_CPL	GENMASK(15, 0)
430 
431 /* WTBLON TOP */
432 #define MT_WTBLON_TOP_BASE		0x820d4000
433 #define MT_WTBLON_TOP(ofs)		(MT_WTBLON_TOP_BASE + (ofs))
434 #define MT_WTBLON_TOP_WDUCR		MT_WTBLON_TOP(__OFFS(WTBLON_TOP_WDUCR))
435 #define MT_WTBLON_TOP_WDUCR_GROUP	GENMASK(2, 0)
436 
437 #define MT_WTBL_UPDATE			MT_WTBLON_TOP(__OFFS(WTBL_UPDATE))
438 #define MT_WTBL_UPDATE_WLAN_IDX		GENMASK(9, 0)
439 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR	BIT(12)
440 #define MT_WTBL_UPDATE_BUSY		BIT(31)
441 
442 /* WTBL */
443 #define MT_WTBL_BASE			0x820d8000
444 #define MT_WTBL_LMAC_ID			GENMASK(14, 8)
445 #define MT_WTBL_LMAC_DW			GENMASK(7, 2)
446 #define MT_WTBL_LMAC_OFFS(_id, _dw)	(MT_WTBL_BASE | \
447 					 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
448 					 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
449 
450 /* AGG: band 0(0x820e2000), band 1(0x820f2000) */
451 #define MT_WF_AGG_BASE(_band)		((_band) ? 0x820f2000 : 0x820e2000)
452 #define MT_WF_AGG(_band, ofs)		(MT_WF_AGG_BASE(_band) + (ofs))
453 
454 #define MT_AGG_AWSCR0(_band, _n)	MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) +	\
455 							  (_n) * 4))
456 #define MT_AGG_PCR0(_band, _n)		MT_WF_AGG(_band, (__OFFS(AGG_PCR0) +	\
457 							  (_n) * 4))
458 #define MT_AGG_PCR0_MM_PROT		BIT(0)
459 #define MT_AGG_PCR0_GF_PROT		BIT(1)
460 #define MT_AGG_PCR0_BW20_PROT		BIT(2)
461 #define MT_AGG_PCR0_BW40_PROT		BIT(4)
462 #define MT_AGG_PCR0_BW80_PROT		BIT(6)
463 #define MT_AGG_PCR0_ERP_PROT		GENMASK(12, 8)
464 #define MT_AGG_PCR0_VHT_PROT		BIT(13)
465 #define MT_AGG_PCR0_PTA_WIN_DIS		BIT(15)
466 
467 #define MT_AGG_PCR1_RTS0_NUM_THRES	GENMASK(31, 23)
468 #define MT_AGG_PCR1_RTS0_LEN_THRES	GENMASK(19, 0)
469 
470 #define MT_AGG_ACR0(_band)		MT_WF_AGG(_band, __OFFS(AGG_ACR0))
471 #define MT_AGG_ACR_CFEND_RATE		GENMASK(13, 0)
472 #define MT_AGG_ACR_BAR_RATE		GENMASK(29, 16)
473 
474 #define MT_AGG_MRCR(_band)		MT_WF_AGG(_band, __OFFS(AGG_MRCR))
475 #define MT_AGG_MRCR_BAR_CNT_LIMIT		GENMASK(15, 12)
476 #define MT_AGG_MRCR_LAST_RTS_CTS_RN		BIT(6)
477 #define MT_AGG_MRCR_RTS_FAIL_LIMIT		GENMASK(11, 7)
478 #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT	GENMASK(28, 24)
479 
480 #define MT_AGG_ATCR1(_band)		MT_WF_AGG(_band, __OFFS(AGG_ATCR1))
481 #define MT_AGG_ATCR3(_band)		MT_WF_AGG(_band, __OFFS(AGG_ATCR3))
482 
483 /* ARB: band 0(0x820e3000), band 1(0x820f3000) */
484 #define MT_WF_ARB_BASE(_band)		((_band) ? 0x820f3000 : 0x820e3000)
485 #define MT_WF_ARB(_band, ofs)		(MT_WF_ARB_BASE(_band) + (ofs))
486 
487 #define MT_ARB_SCR(_band)		MT_WF_ARB(_band, __OFFS(ARB_SCR))
488 #define MT_ARB_SCR_TX_DISABLE		BIT(8)
489 #define MT_ARB_SCR_RX_DISABLE		BIT(9)
490 
491 #define MT_ARB_DRNGR0(_band, _n)	MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) +	\
492 							  (_n) * 4))
493 
494 /* RMAC: band 0(0x820e5000), band 1(0x820f5000) */
495 #define MT_WF_RMAC_BASE(_band)		((_band) ? 0x820f5000 : 0x820e5000)
496 #define MT_WF_RMAC(_band, ofs)		(MT_WF_RMAC_BASE(_band) + (ofs))
497 
498 #define MT_WF_RFCR(_band)		MT_WF_RMAC(_band, 0x000)
499 #define MT_WF_RFCR_DROP_STBC_MULTI	BIT(0)
500 #define MT_WF_RFCR_DROP_FCSFAIL		BIT(1)
501 #define MT_WF_RFCR_DROP_VERSION		BIT(3)
502 #define MT_WF_RFCR_DROP_PROBEREQ	BIT(4)
503 #define MT_WF_RFCR_DROP_MCAST		BIT(5)
504 #define MT_WF_RFCR_DROP_BCAST		BIT(6)
505 #define MT_WF_RFCR_DROP_MCAST_FILTERED	BIT(7)
506 #define MT_WF_RFCR_DROP_A3_MAC		BIT(8)
507 #define MT_WF_RFCR_DROP_A3_BSSID	BIT(9)
508 #define MT_WF_RFCR_DROP_A2_BSSID	BIT(10)
509 #define MT_WF_RFCR_DROP_OTHER_BEACON	BIT(11)
510 #define MT_WF_RFCR_DROP_FRAME_REPORT	BIT(12)
511 #define MT_WF_RFCR_DROP_CTL_RSV		BIT(13)
512 #define MT_WF_RFCR_DROP_CTS		BIT(14)
513 #define MT_WF_RFCR_DROP_RTS		BIT(15)
514 #define MT_WF_RFCR_DROP_DUPLICATE	BIT(16)
515 #define MT_WF_RFCR_DROP_OTHER_BSS	BIT(17)
516 #define MT_WF_RFCR_DROP_OTHER_UC	BIT(18)
517 #define MT_WF_RFCR_DROP_OTHER_TIM	BIT(19)
518 #define MT_WF_RFCR_DROP_NDPA		BIT(20)
519 #define MT_WF_RFCR_DROP_UNWANTED_CTL	BIT(21)
520 
521 #define MT_WF_RFCR1(_band)		MT_WF_RMAC(_band, 0x004)
522 #define MT_WF_RFCR1_DROP_ACK		BIT(4)
523 #define MT_WF_RFCR1_DROP_BF_POLL	BIT(5)
524 #define MT_WF_RFCR1_DROP_BA		BIT(6)
525 #define MT_WF_RFCR1_DROP_CFEND		BIT(7)
526 #define MT_WF_RFCR1_DROP_CFACK		BIT(8)
527 
528 #define MT_WF_RMAC_MIB_AIRTIME0(_band)	MT_WF_RMAC(_band, 0x0380)
529 #define MT_WF_RMAC_MIB_RXTIME_CLR	BIT(31)
530 
531 /* WFDMA0 */
532 #define MT_WFDMA0_BASE			__REG(WFDMA0_ADDR)
533 #define MT_WFDMA0(ofs)			(MT_WFDMA0_BASE + (ofs))
534 
535 #define MT_WFDMA0_RST			MT_WFDMA0(0x100)
536 #define MT_WFDMA0_RST_LOGIC_RST		BIT(4)
537 #define MT_WFDMA0_RST_DMASHDL_ALL_RST	BIT(5)
538 
539 #define MT_WFDMA0_BUSY_ENA		MT_WFDMA0(0x13c)
540 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0	BIT(0)
541 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1	BIT(1)
542 #define MT_WFDMA0_BUSY_ENA_RX_FIFO	BIT(2)
543 
544 #define MT_WFDMA0_GLO_CFG		MT_WFDMA0(0x208)
545 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN	BIT(0)
546 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN	BIT(2)
547 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO	BIT(28)
548 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO	BIT(27)
549 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2	BIT(21)
550 
551 #define MT_WFDMA0_RST_DTX_PTR		MT_WFDMA0(0x20c)
552 #define MT_WFDMA0_PRI_DLY_INT_CFG0	MT_WFDMA0(0x2f0)
553 #define MT_WFDMA0_PRI_DLY_INT_CFG1	MT_WFDMA0(0x2f4)
554 #define MT_WFDMA0_PRI_DLY_INT_CFG2	MT_WFDMA0(0x2f8)
555 
556 /* WFDMA1 */
557 #define MT_WFDMA1_BASE			0xd5000
558 #define MT_WFDMA1(ofs)			(MT_WFDMA1_BASE + (ofs))
559 
560 #define MT_WFDMA1_RST			MT_WFDMA1(0x100)
561 #define MT_WFDMA1_RST_LOGIC_RST		BIT(4)
562 #define MT_WFDMA1_RST_DMASHDL_ALL_RST	BIT(5)
563 
564 #define MT_WFDMA1_BUSY_ENA		MT_WFDMA1(0x13c)
565 #define MT_WFDMA1_BUSY_ENA_TX_FIFO0	BIT(0)
566 #define MT_WFDMA1_BUSY_ENA_TX_FIFO1	BIT(1)
567 #define MT_WFDMA1_BUSY_ENA_RX_FIFO	BIT(2)
568 
569 #define MT_WFDMA1_GLO_CFG		MT_WFDMA1(0x208)
570 #define MT_WFDMA1_GLO_CFG_TX_DMA_EN	BIT(0)
571 #define MT_WFDMA1_GLO_CFG_RX_DMA_EN	BIT(2)
572 #define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO	BIT(28)
573 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO	BIT(27)
574 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2	BIT(21)
575 
576 #define MT_WFDMA1_RST_DTX_PTR		MT_WFDMA1(0x20c)
577 #define MT_WFDMA1_PRI_DLY_INT_CFG0	MT_WFDMA1(0x2f0)
578 
579 /* WFDMA CSR */
580 #define MT_WFDMA_EXT_CSR_BASE		__REG(WFDMA_EXT_CSR_ADDR)
581 #define MT_WFDMA_EXT_CSR_PHYS_BASE	0x18027000
582 #define MT_WFDMA_EXT_CSR(ofs)		(MT_WFDMA_EXT_CSR_BASE + (ofs))
583 #define MT_WFDMA_EXT_CSR_PHYS(ofs)	(MT_WFDMA_EXT_CSR_PHYS_BASE + (ofs))
584 
585 #define MT_WFDMA_HOST_CONFIG		MT_WFDMA_EXT_CSR_PHYS(0x30)
586 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND	BIT(0)
587 #define MT_WFDMA_HOST_CONFIG_WED	BIT(1)
588 
589 #define MT_WFDMA_WED_RING_CONTROL	MT_WFDMA_EXT_CSR_PHYS(0x34)
590 #define MT_WFDMA_WED_RING_CONTROL_TX0	GENMASK(4, 0)
591 #define MT_WFDMA_WED_RING_CONTROL_TX1	GENMASK(12, 8)
592 #define MT_WFDMA_WED_RING_CONTROL_RX1	GENMASK(20, 16)
593 
594 #define MT_WFDMA_EXT_CSR_HIF_MISC	MT_WFDMA_EXT_CSR_PHYS(0x44)
595 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY	BIT(0)
596 
597 #define MT_PCIE_RECOG_ID		0xd7090
598 #define MT_PCIE_RECOG_ID_MASK		GENMASK(30, 0)
599 #define MT_PCIE_RECOG_ID_SEM		BIT(31)
600 
601 #define MT_INT_WED_MASK_CSR		MT_WFDMA_EXT_CSR(0x204)
602 
603 #define MT_WED_TX_RING_BASE		MT_WFDMA_EXT_CSR(0x300)
604 #define MT_WED_RX_RING_BASE		MT_WFDMA_EXT_CSR(0x400)
605 
606 /* WFDMA0 PCIE1 */
607 #define MT_WFDMA0_PCIE1_BASE		__REG(WFDMA0_PCIE1_ADDR)
608 #define MT_WFDMA0_PCIE1(ofs)		(MT_WFDMA0_PCIE1_BASE + (ofs))
609 
610 #define MT_WFDMA0_PCIE1_BUSY_ENA	MT_WFDMA0_PCIE1(0x13c)
611 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0	BIT(0)
612 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1	BIT(1)
613 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO	BIT(2)
614 
615 /* WFDMA1 PCIE1 */
616 #define MT_WFDMA1_PCIE1_BASE		0xd9000
617 #define MT_WFDMA1_PCIE1(ofs)		(MT_WFDMA1_PCIE1_BASE + (ofs))
618 
619 #define MT_WFDMA1_PCIE1_BUSY_ENA	MT_WFDMA1_PCIE1(0x13c)
620 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0	BIT(0)
621 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1	BIT(1)
622 #define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO	BIT(2)
623 
624 /* WFDMA COMMON */
625 #define __RXQ(q)			((q) + __MT_MCUQ_MAX)
626 #define __TXQ(q)			(__RXQ(q) + __MT_RXQ_MAX)
627 
628 #define MT_Q_ID(q)			(dev->q_id[(q)])
629 #define MT_Q_BASE(q)			((dev->wfdma_mask >> (q)) & 0x1 ?	\
630 					 MT_WFDMA1_BASE : MT_WFDMA0_BASE)
631 
632 #define MT_MCUQ_ID(q)			MT_Q_ID(q)
633 #define MT_TXQ_ID(q)			MT_Q_ID(__TXQ(q))
634 #define MT_RXQ_ID(q)			MT_Q_ID(__RXQ(q))
635 
636 #define MT_MCUQ_RING_BASE(q)		(MT_Q_BASE(q) + 0x300)
637 #define MT_TXQ_RING_BASE(q)		(MT_Q_BASE(__TXQ(q)) + 0x300)
638 #define MT_RXQ_RING_BASE(q)		(MT_Q_BASE(__RXQ(q)) + 0x500)
639 
640 #define MT_MCUQ_EXT_CTRL(q)		(MT_Q_BASE(q) +	0x600 +	\
641 					 MT_MCUQ_ID(q)* 0x4)
642 #define MT_RXQ_EXT_CTRL(q)		(MT_Q_BASE(__RXQ(q)) + 0x680 +	\
643 					 MT_RXQ_ID(q)* 0x4)
644 #define MT_TXQ_EXT_CTRL(q)		(MT_Q_BASE(__TXQ(q)) + 0x600 +	\
645 					 MT_TXQ_ID(q)* 0x4)
646 
647 #define MT_INT_SOURCE_CSR		__REG(INT_SOURCE_CSR)
648 #define MT_INT_MASK_CSR			__REG(INT_MASK_CSR)
649 
650 #define MT_INT1_SOURCE_CSR		__REG(INT1_SOURCE_CSR)
651 #define MT_INT1_MASK_CSR		__REG(INT1_MASK_CSR)
652 
653 #define MT_INT_RX_DONE_BAND0		BIT(16)
654 #define MT_INT_RX_DONE_BAND1		BIT(17)
655 #define MT_INT_RX_DONE_WM		BIT(0)
656 #define MT_INT_RX_DONE_WA		BIT(1)
657 #define MT_INT_RX_DONE_WA_MAIN		BIT(1)
658 #define MT_INT_RX_DONE_WA_EXT		BIT(2)
659 #define MT_INT_MCU_CMD			BIT(29)
660 #define MT_INT_RX_DONE_BAND0_MT7916	BIT(22)
661 #define MT_INT_RX_DONE_BAND1_MT7916	BIT(23)
662 #define MT_INT_RX_DONE_WA_MAIN_MT7916	BIT(2)
663 #define MT_INT_RX_DONE_WA_EXT_MT7916	BIT(3)
664 
665 #define MT_INT_RX(q)			(dev->q_int_mask[__RXQ(q)])
666 #define MT_INT_TX_MCU(q)		(dev->q_int_mask[(q)])
667 
668 #define MT_INT_RX_DONE_MCU		(MT_INT_RX(MT_RXQ_MCU) |	\
669 					 MT_INT_RX(MT_RXQ_MCU_WA))
670 
671 #define MT_INT_BAND0_RX_DONE		(MT_INT_RX(MT_RXQ_MAIN) |	\
672 					 MT_INT_RX(MT_RXQ_MAIN_WA))
673 
674 #define MT_INT_BAND1_RX_DONE		(MT_INT_RX(MT_RXQ_EXT) |	\
675 					 MT_INT_RX(MT_RXQ_EXT_WA) |	\
676 					 MT_INT_RX(MT_RXQ_MAIN_WA))
677 
678 #define MT_INT_RX_DONE_ALL		(MT_INT_RX_DONE_MCU |		\
679 					 MT_INT_BAND0_RX_DONE |		\
680 					 MT_INT_BAND1_RX_DONE)
681 
682 #define MT_INT_TX_DONE_FWDL		BIT(26)
683 #define MT_INT_TX_DONE_MCU_WM		BIT(27)
684 #define MT_INT_TX_DONE_MCU_WA		BIT(15)
685 #define MT_INT_TX_DONE_BAND0		BIT(30)
686 #define MT_INT_TX_DONE_BAND1		BIT(31)
687 #define MT_INT_TX_DONE_MCU_WA_MT7916	BIT(25)
688 
689 #define MT_INT_TX_DONE_MCU		(MT_INT_TX_MCU(MT_MCUQ_WA) |	\
690 					 MT_INT_TX_MCU(MT_MCUQ_WM) |	\
691 					 MT_INT_TX_MCU(MT_MCUQ_FWDL))
692 
693 #define MT_MCU_CMD			__REG(INT_MCU_CMD_SOURCE)
694 #define MT_MCU_CMD_STOP_DMA_FW_RELOAD	BIT(1)
695 #define MT_MCU_CMD_STOP_DMA		BIT(2)
696 #define MT_MCU_CMD_RESET_DONE		BIT(3)
697 #define MT_MCU_CMD_RECOVERY_DONE	BIT(4)
698 #define MT_MCU_CMD_NORMAL_STATE		BIT(5)
699 #define MT_MCU_CMD_ERROR_MASK		GENMASK(5, 1)
700 
701 /* TOP RGU */
702 #define MT_TOP_RGU_BASE			0x18000000
703 #define MT_TOP_PWR_CTRL			(MT_TOP_RGU_BASE + (0x0))
704 #define MT_TOP_PWR_KEY			(0x5746 << 16)
705 #define MT_TOP_PWR_SW_RST		BIT(0)
706 #define MT_TOP_PWR_SW_PWR_ON		GENMASK(3, 2)
707 #define MT_TOP_PWR_HW_CTRL		BIT(4)
708 #define MT_TOP_PWR_PWR_ON		BIT(7)
709 
710 #define MT_TOP_RGU_SYSRAM_PDN		(MT_TOP_RGU_BASE + 0x050)
711 #define MT_TOP_RGU_SYSRAM_SLP		(MT_TOP_RGU_BASE + 0x054)
712 #define MT_TOP_WFSYS_PWR		(MT_TOP_RGU_BASE + 0x010)
713 #define MT_TOP_PWR_EN_MASK		BIT(7)
714 #define MT_TOP_PWR_ACK_MASK		BIT(6)
715 #define MT_TOP_PWR_KEY_MASK		GENMASK(31, 16)
716 
717 #define MT7986_TOP_WM_RESET		(MT_TOP_RGU_BASE + 0x120)
718 #define MT7986_TOP_WM_RESET_MASK	BIT(0)
719 
720 /* l1/l2 remap */
721 #define MT_HIF_REMAP_L1			0xf11ac
722 #define MT_HIF_REMAP_L1_MT7916		0xfe260
723 #define MT_HIF_REMAP_L1_MASK		GENMASK(15, 0)
724 #define MT_HIF_REMAP_L1_OFFSET		GENMASK(15, 0)
725 #define MT_HIF_REMAP_L1_BASE		GENMASK(31, 16)
726 #define MT_HIF_REMAP_BASE_L1		0xe0000
727 
728 #define MT_HIF_REMAP_L2			0xf11b0
729 #define MT_HIF_REMAP_L2_MASK		GENMASK(19, 0)
730 #define MT_HIF_REMAP_L2_OFFSET		GENMASK(11, 0)
731 #define MT_HIF_REMAP_L2_BASE		GENMASK(31, 12)
732 #define MT_HIF_REMAP_L2_MT7916		0x1b8
733 #define MT_HIF_REMAP_L2_MASK_MT7916	GENMASK(31, 16)
734 #define MT_HIF_REMAP_L2_OFFSET_MT7916	GENMASK(15, 0)
735 #define MT_HIF_REMAP_L2_BASE_MT7916	GENMASK(31, 16)
736 #define MT_HIF_REMAP_BASE_L2_MT7916	0x40000
737 
738 #define MT_INFRA_BASE			0x18000000
739 #define MT_WFSYS0_PHY_START		0x18400000
740 #define MT_WFSYS1_PHY_START		0x18800000
741 #define MT_WFSYS1_PHY_END		0x18bfffff
742 #define MT_CBTOP1_PHY_START		0x70000000
743 #define MT_CBTOP1_PHY_END		__REG(CBTOP1_PHY_END)
744 #define MT_CBTOP2_PHY_START		0xf0000000
745 #define MT_CBTOP2_PHY_END		0xffffffff
746 #define MT_INFRA_MCU_START		0x7c000000
747 #define MT_INFRA_MCU_END		__REG(INFRA_MCU_ADDR_END)
748 #define MT_CONN_INFRA_OFFSET(p)		((p) - MT_INFRA_BASE)
749 
750 /* CONN INFRA CFG */
751 #define MT_CONN_INFRA_BASE		0x18001000
752 #define MT_CONN_INFRA(ofs)		(MT_CONN_INFRA_BASE + (ofs))
753 
754 #define MT_CONN_INFRA_EFUSE		MT_CONN_INFRA(0x020)
755 
756 #define MT_CONN_INFRA_ADIE_RESET	MT_CONN_INFRA(0x030)
757 #define MT_CONN_INFRA_ADIE1_RESET_MASK	BIT(0)
758 #define MT_CONN_INFRA_ADIE2_RESET_MASK	BIT(2)
759 
760 #define MT_CONN_INFRA_OSC_RC_EN		MT_CONN_INFRA(0x380)
761 
762 #define MT_CONN_INFRA_OSC_CTRL		MT_CONN_INFRA(0x300)
763 #define MT_CONN_INFRA_OSC_RC_EN_MASK	BIT(7)
764 #define MT_CONN_INFRA_OSC_STB_TIME_MASK	GENMASK(23, 0)
765 
766 #define MT_CONN_INFRA_HW_CTRL		MT_CONN_INFRA(0x200)
767 #define MT_CONN_INFRA_HW_CTRL_MASK	BIT(0)
768 
769 #define MT_CONN_INFRA_WF_SLP_PROT	MT_CONN_INFRA(0x540)
770 #define MT_CONN_INFRA_WF_SLP_PROT_MASK	BIT(0)
771 
772 #define MT_CONN_INFRA_WF_SLP_PROT_RDY	MT_CONN_INFRA(0x544)
773 #define MT_CONN_INFRA_CONN_WF_MASK	(BIT(29) | BIT(31))
774 #define MT_CONN_INFRA_CONN		(BIT(25) | BIT(29) | BIT(31))
775 
776 #define MT_CONN_INFRA_EMI_REQ		MT_CONN_INFRA(0x414)
777 #define MT_CONN_INFRA_EMI_REQ_MASK	BIT(0)
778 #define MT_CONN_INFRA_INFRA_REQ_MASK	BIT(5)
779 
780 /* AFE */
781 #define MT_AFE_CTRL_BASE(_band)		(0x18003000 + ((_band) << 19))
782 #define MT_AFE_CTRL(_band, ofs)		(MT_AFE_CTRL_BASE(_band) + (ofs))
783 
784 #define MT_AFE_DIG_EN_01(_band)		MT_AFE_CTRL(_band, 0x00)
785 #define MT_AFE_DIG_EN_02(_band)		MT_AFE_CTRL(_band, 0x04)
786 #define MT_AFE_DIG_EN_03(_band)		MT_AFE_CTRL(_band, 0x08)
787 #define MT_AFE_DIG_TOP_01(_band)	MT_AFE_CTRL(_band, 0x0c)
788 
789 #define MT_AFE_PLL_STB_TIME(_band)	MT_AFE_CTRL(_band, 0xf4)
790 #define MT_AFE_PLL_STB_TIME_MASK	(GENMASK(30, 16) | GENMASK(14, 0))
791 #define MT_AFE_PLL_STB_TIME_VAL		(FIELD_PREP(GENMASK(30, 16), 0x4bc) | \
792 					 FIELD_PREP(GENMASK(14, 0), 0x7e4))
793 #define MT_AFE_BPLL_CFG_MASK		GENMASK(7, 6)
794 #define MT_AFE_WPLL_CFG_MASK		GENMASK(1, 0)
795 #define MT_AFE_MCU_WPLL_CFG_MASK	GENMASK(3, 2)
796 #define MT_AFE_MCU_BPLL_CFG_MASK	GENMASK(17, 16)
797 #define MT_AFE_PLL_CFG_MASK		(MT_AFE_BPLL_CFG_MASK | \
798 					 MT_AFE_WPLL_CFG_MASK | \
799 					 MT_AFE_MCU_WPLL_CFG_MASK | \
800 					 MT_AFE_MCU_BPLL_CFG_MASK)
801 #define MT_AFE_PLL_CFG_VAL		(FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \
802 					 FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \
803 					 FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \
804 					 FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2))
805 
806 #define MT_AFE_DIG_TOP_01_MASK		GENMASK(18, 15)
807 #define MT_AFE_DIG_TOP_01_VAL		FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9)
808 
809 #define MT_AFE_RG_WBG_EN_RCK_MASK	BIT(0)
810 #define MT_AFE_RG_WBG_EN_BPLL_UP_MASK	BIT(21)
811 #define MT_AFE_RG_WBG_EN_WPLL_UP_MASK	BIT(20)
812 #define MT_AFE_RG_WBG_EN_PLL_UP_MASK	(MT_AFE_RG_WBG_EN_BPLL_UP_MASK | \
813 					 MT_AFE_RG_WBG_EN_WPLL_UP_MASK)
814 #define MT_AFE_RG_WBG_EN_TXCAL_MASK	GENMASK(21, 17)
815 
816 #define MT_ADIE_SLP_CTRL_BASE(_band)	(0x18005000 + ((_band) << 19))
817 #define MT_ADIE_SLP_CTRL(_band, ofs)	(MT_ADIE_SLP_CTRL_BASE(_band) + (ofs))
818 
819 #define MT_ADIE_SLP_CTRL_CK0(_band)	MT_ADIE_SLP_CTRL(_band, 0x120)
820 
821 /* ADIE */
822 #define MT_ADIE_CHIP_ID			0x02c
823 #define MT_ADIE_VERSION_MASK		GENMASK(15, 0)
824 #define MT_ADIE_CHIP_ID_MASK		GENMASK(31, 16)
825 #define MT_ADIE_IDX0			GENMASK(15, 0)
826 #define MT_ADIE_IDX1			GENMASK(31, 16)
827 
828 #define MT_ADIE_RG_TOP_THADC_BG		0x034
829 #define MT_ADIE_VRPI_SEL_CR_MASK	GENMASK(15, 12)
830 #define MT_ADIE_VRPI_SEL_EFUSE_MASK	GENMASK(6, 3)
831 
832 #define MT_ADIE_RG_TOP_THADC		0x038
833 #define MT_ADIE_PGA_GAIN_MASK		GENMASK(25, 23)
834 #define MT_ADIE_PGA_GAIN_EFUSE_MASK	GENMASK(2, 0)
835 #define MT_ADIE_LDO_CTRL_MASK		GENMASK(27, 26)
836 #define MT_ADIE_LDO_CTRL_EFUSE_MASK	GENMASK(6, 5)
837 
838 #define MT_AFE_RG_ENCAL_WBTAC_IF_SW	0x070
839 #define MT_ADIE_EFUSE_RDATA0		0x130
840 
841 #define MT_ADIE_EFUSE2_CTRL		0x148
842 #define MT_ADIE_EFUSE_CTRL_MASK		BIT(1)
843 
844 #define MT_ADIE_EFUSE_CFG		0x144
845 #define MT_ADIE_EFUSE_MODE_MASK		GENMASK(7, 6)
846 #define MT_ADIE_EFUSE_ADDR_MASK		GENMASK(25, 16)
847 #define MT_ADIE_EFUSE_VALID_MASK	BIT(29)
848 #define MT_ADIE_EFUSE_KICK_MASK		BIT(30)
849 
850 #define MT_ADIE_THADC_ANALOG		0x3a6
851 
852 #define MT_ADIE_THADC_SLOP		0x3a7
853 #define MT_ADIE_ANA_EN_MASK		BIT(7)
854 
855 #define MT_ADIE_7975_XTAL_CAL		0x3a1
856 #define MT_ADIE_TRIM_MASK		GENMASK(6, 0)
857 #define MT_ADIE_EFUSE_TRIM_MASK		GENMASK(5, 0)
858 #define MT_ADIE_XO_TRIM_EN_MASK		BIT(7)
859 #define MT_ADIE_XTAL_DECREASE_MASK	BIT(6)
860 
861 #define MT_ADIE_7975_XO_TRIM2		0x3a2
862 #define MT_ADIE_7975_XO_TRIM3		0x3a3
863 #define MT_ADIE_7975_XO_TRIM4		0x3a4
864 #define MT_ADIE_7975_XTAL_EN		0x3a5
865 
866 #define MT_ADIE_XO_TRIM_FLOW		0x3ac
867 #define MT_ADIE_XTAL_AXM_80M_OSC	0x390
868 #define MT_ADIE_XTAL_AXM_40M_OSC	0x391
869 #define MT_ADIE_XTAL_TRIM1_80M_OSC	0x398
870 #define MT_ADIE_XTAL_TRIM1_40M_OSC	0x399
871 #define MT_ADIE_WRI_CK_SEL		0x4ac
872 #define MT_ADIE_RG_STRAP_PIN_IN		0x4fc
873 #define MT_ADIE_XTAL_C1			0x654
874 #define MT_ADIE_XTAL_C2			0x658
875 #define MT_ADIE_RG_XO_01		0x65c
876 #define MT_ADIE_RG_XO_03		0x664
877 
878 #define MT_ADIE_CLK_EN			0xa00
879 
880 #define MT_ADIE_7975_XTAL		0xa18
881 #define MT_ADIE_7975_XTAL_EN_MASK	BIT(29)
882 
883 #define MT_ADIE_7975_COCLK		0xa1c
884 #define MT_ADIE_7975_XO_2		0xa84
885 #define MT_ADIE_7975_XO_2_FIX_EN	BIT(31)
886 
887 #define MT_ADIE_7975_XO_CTRL2		0xa94
888 #define MT_ADIE_7975_XO_CTRL2_C1_MASK	GENMASK(26, 20)
889 #define MT_ADIE_7975_XO_CTRL2_C2_MASK	GENMASK(18, 12)
890 #define MT_ADIE_7975_XO_CTRL2_MASK	(MT_ADIE_7975_XO_CTRL2_C1_MASK | \
891 					 MT_ADIE_7975_XO_CTRL2_C2_MASK)
892 
893 #define MT_ADIE_7975_XO_CTRL6		0xaa4
894 #define MT_ADIE_7975_XO_CTRL6_MASK	BIT(16)
895 
896 /* TOP SPI */
897 #define MT_TOP_SPI_ADIE_BASE(_band)	(0x18004000 + ((_band) << 19))
898 #define MT_TOP_SPI_ADIE(_band, ofs)	(MT_TOP_SPI_ADIE_BASE(_band) + (ofs))
899 
900 #define MT_TOP_SPI_BUSY_CR(_band)	MT_TOP_SPI_ADIE(_band, 0)
901 #define MT_TOP_SPI_POLLING_BIT		BIT(5)
902 
903 #define MT_TOP_SPI_ADDR_CR(_band)	MT_TOP_SPI_ADIE(_band, 0x50)
904 #define MT_TOP_SPI_READ_ADDR_FORMAT	(BIT(12) | BIT(13) | BIT(15))
905 #define MT_TOP_SPI_WRITE_ADDR_FORMAT	(BIT(13) | BIT(15))
906 
907 #define MT_TOP_SPI_WRITE_DATA_CR(_band)	MT_TOP_SPI_ADIE(_band, 0x54)
908 #define MT_TOP_SPI_READ_DATA_CR(_band)	MT_TOP_SPI_ADIE(_band, 0x58)
909 
910 /* CONN INFRA CKGEN */
911 #define MT_INFRA_CKGEN_BASE		0x18009000
912 #define MT_INFRA_CKGEN(ofs)		(MT_INFRA_CKGEN_BASE + (ofs))
913 
914 #define MT_INFRA_CKGEN_BUS		MT_INFRA_CKGEN(0xa00)
915 #define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK	BIT(23)
916 #define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK	BIT(29)
917 
918 #define MT_INFRA_CKGEN_BUS_WPLL_DIV_1	MT_INFRA_CKGEN(0x008)
919 #define MT_INFRA_CKGEN_BUS_WPLL_DIV_2	MT_INFRA_CKGEN(0x00c)
920 
921 #define MT_INFRA_CKGEN_RFSPI_WPLL_DIV	MT_INFRA_CKGEN(0x040)
922 #define MT_INFRA_CKGEN_DIV_SEL_MASK	GENMASK(7, 2)
923 #define MT_INFRA_CKGEN_DIV_EN_MASK	BIT(0)
924 
925 /* CONN INFRA BUS */
926 #define MT_INFRA_BUS_BASE		0x1800e000
927 #define MT_INFRA_BUS(ofs)		(MT_INFRA_BUS_BASE + (ofs))
928 
929 #define MT_INFRA_BUS_OFF_TIMEOUT	MT_INFRA_BUS(0x300)
930 #define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK	GENMASK(14, 7)
931 #define MT_INFRA_BUS_TIMEOUT_EN_MASK	GENMASK(3, 0)
932 
933 #define MT_INFRA_BUS_ON_TIMEOUT		MT_INFRA_BUS(0x31c)
934 #define MT_INFRA_BUS_EMI_START		MT_INFRA_BUS(0x360)
935 #define MT_INFRA_BUS_EMI_END		MT_INFRA_BUS(0x364)
936 
937 /* CONN_INFRA_SKU */
938 #define MT_CONNINFRA_SKU_DEC_ADDR	0x18050000
939 #define MT_CONNINFRA_SKU_MASK		GENMASK(15, 0)
940 #define MT_ADIE_TYPE_MASK		BIT(1)
941 
942 /* FW MODE SYNC */
943 #define MT_FW_EXCEPTION		__REG(FW_EXCEPTION_ADDR)
944 
945 #define MT_SWDEF_BASE			__REG(SWDEF_BASE_ADDR)
946 
947 #define MT_SWDEF(ofs)			(MT_SWDEF_BASE + (ofs))
948 #define MT_SWDEF_MODE			MT_SWDEF(0x3c)
949 #define MT_SWDEF_NORMAL_MODE		0
950 #define MT_SWDEF_ICAP_MODE		1
951 #define MT_SWDEF_SPECTRUM_MODE		2
952 
953 #define MT_SWDEF_SER_STATS		MT_SWDEF(0x040)
954 #define MT_SWDEF_PLE_STATS		MT_SWDEF(0x044)
955 #define MT_SWDEF_PLE1_STATS		MT_SWDEF(0x048)
956 #define MT_SWDEF_PLE_AMSDU_STATS	MT_SWDEF(0x04C)
957 #define MT_SWDEF_PSE_STATS		MT_SWDEF(0x050)
958 #define MT_SWDEF_PSE1_STATS		MT_SWDEF(0x054)
959 #define MT_SWDEF_LAMC_WISR6_BN0_STATS	MT_SWDEF(0x058)
960 #define MT_SWDEF_LAMC_WISR6_BN1_STATS	MT_SWDEF(0x05C)
961 #define MT_SWDEF_LAMC_WISR7_BN0_STATS	MT_SWDEF(0x060)
962 #define MT_SWDEF_LAMC_WISR7_BN1_STATS	MT_SWDEF(0x064)
963 
964 #define MT_DIC_CMD_REG_BASE		0x41f000
965 #define MT_DIC_CMD_REG(ofs)		(MT_DIC_CMD_REG_BASE + (ofs))
966 #define MT_DIC_CMD_REG_CMD		MT_DIC_CMD_REG(0x10)
967 
968 #define MT_CPU_UTIL_BASE		0x41f030
969 #define MT_CPU_UTIL(ofs)		(MT_CPU_UTIL_BASE + (ofs))
970 #define MT_CPU_UTIL_BUSY_PCT		MT_CPU_UTIL(0x00)
971 #define MT_CPU_UTIL_PEAK_BUSY_PCT	MT_CPU_UTIL(0x04)
972 #define MT_CPU_UTIL_IDLE_CNT		MT_CPU_UTIL(0x08)
973 #define MT_CPU_UTIL_PEAK_IDLE_CNT	MT_CPU_UTIL(0x0c)
974 #define MT_CPU_UTIL_CTRL		MT_CPU_UTIL(0x1c)
975 
976 /* LED */
977 #define MT_LED_TOP_BASE			0x18013000
978 #define MT_LED_PHYS(_n)			(MT_LED_TOP_BASE + (_n))
979 
980 #define MT_LED_CTRL(_n)			MT_LED_PHYS(0x00 + ((_n) * 4))
981 #define MT_LED_CTRL_KICK		BIT(7)
982 #define MT_LED_CTRL_BLINK_MODE		BIT(2)
983 #define MT_LED_CTRL_POLARITY		BIT(1)
984 
985 #define MT_LED_TX_BLINK(_n)		MT_LED_PHYS(0x10 + ((_n) * 4))
986 #define MT_LED_TX_BLINK_ON_MASK		GENMASK(7, 0)
987 #define MT_LED_TX_BLINK_OFF_MASK        GENMASK(15, 8)
988 
989 #define MT_LED_EN(_n)			MT_LED_PHYS(0x40 + ((_n) * 4))
990 
991 #define MT_LED_GPIO_MUX2                0x70005058 /* GPIO 18 */
992 #define MT_LED_GPIO_MUX3                0x7000505C /* GPIO 26 */
993 #define MT_LED_GPIO_SEL_MASK            GENMASK(11, 8)
994 
995 /* MT TOP */
996 #define MT_TOP_BASE			0x18060000
997 #define MT_TOP(ofs)			(MT_TOP_BASE + (ofs))
998 
999 #define MT_TOP_LPCR_HOST_BAND(_band)	MT_TOP(0x10 + ((_band) * 0x10))
1000 #define MT_TOP_LPCR_HOST_FW_OWN		BIT(0)
1001 #define MT_TOP_LPCR_HOST_DRV_OWN	BIT(1)
1002 #define MT_TOP_LPCR_HOST_FW_OWN_STAT	BIT(2)
1003 
1004 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band)	MT_TOP(0x14 + ((_band) * 0x10))
1005 #define MT_TOP_LPCR_HOST_BAND_STAT	BIT(0)
1006 
1007 #define MT_TOP_MISC			MT_TOP(0xf0)
1008 #define MT_TOP_MISC_FW_STATE		GENMASK(2, 0)
1009 
1010 #define MT_TOP_WFSYS_WAKEUP		MT_TOP(0x1a4)
1011 #define MT_TOP_WFSYS_WAKEUP_MASK	BIT(0)
1012 
1013 #define MT_TOP_MCU_EMI_BASE		MT_TOP(0x1c4)
1014 #define MT_TOP_MCU_EMI_BASE_MASK	GENMASK(19, 0)
1015 
1016 #define MT_TOP_CONN_INFRA_WAKEUP	MT_TOP(0x1a0)
1017 #define MT_TOP_CONN_INFRA_WAKEUP_MASK	BIT(0)
1018 
1019 #define MT_TOP_WFSYS_RESET_STATUS	MT_TOP(0x2cc)
1020 #define MT_TOP_WFSYS_RESET_STATUS_MASK	BIT(30)
1021 
1022 /* SEMA */
1023 #define MT_SEMA_BASE			0x18070000
1024 #define MT_SEMA(ofs)			(MT_SEMA_BASE + (ofs))
1025 
1026 #define MT_SEMA_RFSPI_STATUS		(MT_SEMA(0x2000) + (11 * 4))
1027 #define MT_SEMA_RFSPI_RELEASE		(MT_SEMA(0x2200) + (11 * 4))
1028 #define MT_SEMA_RFSPI_STATUS_MASK	BIT(1)
1029 
1030 /* MCU BUS */
1031 #define MT_MCU_BUS_BASE			0x18400000
1032 #define MT_MCU_BUS(ofs)			(MT_MCU_BUS_BASE + (ofs))
1033 
1034 #define MT_MCU_BUS_TIMEOUT		MT_MCU_BUS(0xf0440)
1035 #define MT_MCU_BUS_TIMEOUT_SET_MASK	GENMASK(7, 0)
1036 #define MT_MCU_BUS_TIMEOUT_CG_EN_MASK	BIT(28)
1037 #define MT_MCU_BUS_TIMEOUT_EN_MASK	BIT(31)
1038 
1039 #define MT_MCU_BUS_REMAP		MT_MCU_BUS(0x120)
1040 
1041 /* TOP CFG */
1042 #define MT_TOP_CFG_BASE			0x184b0000
1043 #define MT_TOP_CFG(ofs)			(MT_TOP_CFG_BASE + (ofs))
1044 
1045 #define MT_TOP_CFG_IP_VERSION_ADDR	MT_TOP_CFG(0x010)
1046 
1047 /* TOP CFG ON */
1048 #define MT_TOP_CFG_ON_BASE		0x184c1000
1049 #define MT_TOP_CFG_ON(ofs)		(MT_TOP_CFG_ON_BASE + (ofs))
1050 
1051 #define MT_TOP_CFG_ON_ROM_IDX		MT_TOP_CFG_ON(0x604)
1052 
1053 /* SLP CTRL */
1054 #define MT_SLP_BASE			0x184c3000
1055 #define MT_SLP(ofs)			(MT_SLP_BASE + (ofs))
1056 
1057 #define MT_SLP_STATUS			MT_SLP(0x00c)
1058 #define MT_SLP_WFDMA2CONN_MASK		(BIT(21) | BIT(23))
1059 #define MT_SLP_CTRL_EN_MASK		BIT(0)
1060 #define MT_SLP_CTRL_BSY_MASK		BIT(1)
1061 
1062 /* MCU BUS DBG */
1063 #define MT_MCU_BUS_DBG_BASE		0x18500000
1064 #define MT_MCU_BUS_DBG(ofs)		(MT_MCU_BUS_DBG_BASE + (ofs))
1065 
1066 #define MT_MCU_BUS_DBG_TIMEOUT		MT_MCU_BUS_DBG(0x0)
1067 #define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16)
1068 #define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3)
1069 #define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK	BIT(2)
1070 
1071 #define MT_HW_BOUND			0x70010020
1072 #define MT_HW_REV			0x70010204
1073 #define MT_WF_SUBSYS_RST		0x70002600
1074 
1075 /* PCIE MAC */
1076 #define MT_PCIE_MAC_BASE		0x74030000
1077 #define MT_PCIE_MAC(ofs)		(MT_PCIE_MAC_BASE + (ofs))
1078 #define MT_PCIE_MAC_INT_ENABLE		MT_PCIE_MAC(0x188)
1079 
1080 #define MT_PCIE1_MAC_INT_ENABLE		0x74020188
1081 #define MT_PCIE1_MAC_INT_ENABLE_MT7916	0x74090188
1082 
1083 #define MT_WM_MCU_PC			0x7c060204
1084 #define MT_WA_MCU_PC			0x7c06020c
1085 
1086 /* PP TOP */
1087 #define MT_WF_PP_TOP_BASE		0x820cc000
1088 #define MT_WF_PP_TOP(ofs)		(MT_WF_PP_TOP_BASE + (ofs))
1089 
1090 #define MT_WF_PP_TOP_RXQ_WFDMA_CF_5	MT_WF_PP_TOP(0x0e8)
1091 #define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK	BIT(6)
1092 
1093 #define MT_WF_IRPI_BASE			0x83000000
1094 #define MT_WF_IRPI(ofs)			(MT_WF_IRPI_BASE + (ofs))
1095 
1096 #define MT_WF_IRPI_NSS(phy, nss)	MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16))
1097 #define MT_WF_IRPI_NSS_MT7916(phy, nss)	MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16))
1098 
1099 /* PHY */
1100 #define MT_WF_PHY_BASE			0x83080000
1101 #define MT_WF_PHY(ofs)			(MT_WF_PHY_BASE + (ofs))
1102 
1103 #define MT_WF_PHY_RX_CTRL1(_phy)	MT_WF_PHY(0x2004 + ((_phy) << 16))
1104 #define MT_WF_PHY_RX_CTRL1_MT7916(_phy)	MT_WF_PHY(0x2004 + ((_phy) << 20))
1105 #define MT_WF_PHY_RX_CTRL1_IPI_EN	GENMASK(2, 0)
1106 #define MT_WF_PHY_RX_CTRL1_STSCNT_EN	GENMASK(11, 9)
1107 
1108 #define MT_WF_PHY_RXTD12(_phy)		MT_WF_PHY(0x8230 + ((_phy) << 16))
1109 #define MT_WF_PHY_RXTD12_MT7916(_phy)	MT_WF_PHY(0x8230 + ((_phy) << 20))
1110 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY	BIT(18)
1111 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR		BIT(29)
1112 
1113 #define MT_MCU_WM_CIRQ_BASE			0x89010000
1114 #define MT_MCU_WM_CIRQ(ofs)			(MT_MCU_WM_CIRQ_BASE + (ofs))
1115 #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR	MT_MCU_WM_CIRQ(0x80)
1116 #define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR		MT_MCU_WM_CIRQ(0xc0)
1117 
1118 #endif
1119