1 /*
2 * arch/arm/include/asm/io.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
12 * constant addresses and variable addresses.
13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
14 * specific IO header files.
15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
16 * 04-Apr-1999 PJB Added check_signature.
17 * 12-Dec-1999 RMK More cleanups
18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
20 */
21 #ifndef __ASM_ARM_IO_H
22 #define __ASM_ARM_IO_H
23
24 #ifdef __KERNEL__
25
26 #include <linux/types.h>
27 #include <asm/byteorder.h>
28 #include <asm/memory.h>
29 #include <asm-generic/pci_iomap.h>
30
31 /*
32 * ISA I/O bus memory addresses are 1:1 with the physical address.
33 */
34 #define isa_virt_to_bus virt_to_phys
35 #define isa_page_to_bus page_to_phys
36 #define isa_bus_to_virt phys_to_virt
37
38 /*
39 * Generic IO read/write. These perform native-endian accesses. Note
40 * that some architectures will want to re-define __raw_{read,write}w.
41 */
42 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
43 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
44 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
45
46 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
47 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
48 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
49
50 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))
51 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
52 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))
53
54 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a))
55 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
56 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a))
57
58 /*
59 * Architecture ioremap implementation.
60 */
61 #define MT_DEVICE 0
62 #define MT_DEVICE_NONSHARED 1
63 #define MT_DEVICE_CACHED 2
64 #define MT_DEVICE_WC 3
65 /*
66 * types 4 onwards can be found in asm/mach/map.h and are undefined
67 * for ioremap
68 */
69
70 /*
71 * __arm_ioremap takes CPU physical address.
72 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
73 * The _caller variety takes a __builtin_return_address(0) value for
74 * /proc/vmalloc to use - and should only be used in non-inline functions.
75 */
76 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
77 size_t, unsigned int, void *);
78 extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
79 void *);
80
81 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
82 extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
83 extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
84 extern void __iounmap(volatile void __iomem *addr);
85 extern void __arm_iounmap(volatile void __iomem *addr);
86
87 extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
88 unsigned int, void *);
89 extern void (*arch_iounmap)(volatile void __iomem *);
90
91 /*
92 * Bad read/write accesses...
93 */
94 extern void __readwrite_bug(const char *fn);
95
96 /*
97 * A typesafe __io() helper
98 */
__typesafe_io(unsigned long addr)99 static inline void __iomem *__typesafe_io(unsigned long addr)
100 {
101 return (void __iomem *)addr;
102 }
103
104 #define IOMEM(x) ((void __force __iomem *)(x))
105
106 /* IO barriers */
107 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
108 #include <asm/barrier.h>
109 #define __iormb() rmb()
110 #define __iowmb() wmb()
111 #else
112 #define __iormb() do { } while (0)
113 #define __iowmb() do { } while (0)
114 #endif
115
116 /*
117 * Now, pick up the machine-defined IO definitions
118 */
119 #ifdef CONFIG_NEED_MACH_IO_H
120 #include <mach/io.h>
121 #else
122 #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
123 #endif
124
125 /*
126 * This is the limit of PC card/PCI/ISA IO space, which is by default
127 * 64K if we have PC card, PCI or ISA support. Otherwise, default to
128 * zero to prevent ISA/PCI drivers claiming IO space (and potentially
129 * oopsing.)
130 *
131 * Only set this larger if you really need inb() et.al. to operate over
132 * a larger address space. Note that SOC_COMMON ioremaps each sockets
133 * IO space area, and so inb() et.al. must be defined to operate as per
134 * readb() et.al. on such platforms.
135 */
136 #ifndef IO_SPACE_LIMIT
137 #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
138 #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
139 #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
140 #define IO_SPACE_LIMIT ((resource_size_t)0xffff)
141 #else
142 #define IO_SPACE_LIMIT ((resource_size_t)0)
143 #endif
144 #endif
145
146 /*
147 * IO port access primitives
148 * -------------------------
149 *
150 * The ARM doesn't have special IO access instructions; all IO is memory
151 * mapped. Note that these are defined to perform little endian accesses
152 * only. Their primary purpose is to access PCI and ISA peripherals.
153 *
154 * Note that for a big endian machine, this implies that the following
155 * big endian mode connectivity is in place, as described by numerous
156 * ARM documents:
157 *
158 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
159 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
160 *
161 * The machine specific io.h include defines __io to translate an "IO"
162 * address to a memory address.
163 *
164 * Note that we prevent GCC re-ordering or caching values in expressions
165 * by introducing sequence points into the in*() definitions. Note that
166 * __raw_* do not guarantee this behaviour.
167 *
168 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
169 */
170 #ifdef __io
171 #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
172 #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
173 cpu_to_le16(v),__io(p)); })
174 #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
175 cpu_to_le32(v),__io(p)); })
176
177 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
178 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
179 __raw_readw(__io(p))); __iormb(); __v; })
180 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
181 __raw_readl(__io(p))); __iormb(); __v; })
182
183 #define outsb(p,d,l) __raw_writesb(__io(p),d,l)
184 #define outsw(p,d,l) __raw_writesw(__io(p),d,l)
185 #define outsl(p,d,l) __raw_writesl(__io(p),d,l)
186
187 #define insb(p,d,l) __raw_readsb(__io(p),d,l)
188 #define insw(p,d,l) __raw_readsw(__io(p),d,l)
189 #define insl(p,d,l) __raw_readsl(__io(p),d,l)
190 #endif
191
192 #define outb_p(val,port) outb((val),(port))
193 #define outw_p(val,port) outw((val),(port))
194 #define outl_p(val,port) outl((val),(port))
195 #define inb_p(port) inb((port))
196 #define inw_p(port) inw((port))
197 #define inl_p(port) inl((port))
198
199 #define outsb_p(port,from,len) outsb(port,from,len)
200 #define outsw_p(port,from,len) outsw(port,from,len)
201 #define outsl_p(port,from,len) outsl(port,from,len)
202 #define insb_p(port,to,len) insb(port,to,len)
203 #define insw_p(port,to,len) insw(port,to,len)
204 #define insl_p(port,to,len) insl(port,to,len)
205
206 /*
207 * String version of IO memory access ops:
208 */
209 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
210 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
211 extern void _memset_io(volatile void __iomem *, int, size_t);
212
213 #define mmiowb()
214
215 /*
216 * Memory access primitives
217 * ------------------------
218 *
219 * These perform PCI memory accesses via an ioremap region. They don't
220 * take an address as such, but a cookie.
221 *
222 * Again, this are defined to perform little endian accesses. See the
223 * IO port primitives for more information.
224 */
225 #ifndef readl
226 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
227 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
228 __raw_readw(c)); __r; })
229 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
230 __raw_readl(c)); __r; })
231
232 #define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
233 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
234 cpu_to_le16(v),c))
235 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
236 cpu_to_le32(v),c))
237
238 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
239 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
240 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
241
242 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
243 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
244 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
245
246 #define readsb(p,d,l) __raw_readsb(p,d,l)
247 #define readsw(p,d,l) __raw_readsw(p,d,l)
248 #define readsl(p,d,l) __raw_readsl(p,d,l)
249
250 #define writesb(p,d,l) __raw_writesb(p,d,l)
251 #define writesw(p,d,l) __raw_writesw(p,d,l)
252 #define writesl(p,d,l) __raw_writesl(p,d,l)
253
254 #define memset_io(c,v,l) _memset_io(c,(v),(l))
255 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
256 #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
257
258 #endif /* readl */
259
260 /*
261 * ioremap and friends.
262 *
263 * ioremap takes a PCI memory address, as specified in
264 * Documentation/io-mapping.txt.
265 *
266 */
267 #define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
268 #define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
269 #define ioremap_cached(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
270 #define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)
271 #define iounmap __arm_iounmap
272
273 /*
274 * io{read,write}{8,16,32} macros
275 */
276 #ifndef ioread8
277 #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
278 #define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
279 #define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
280
281 #define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
282 #define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
283
284 #define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); })
285 #define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); })
286 #define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); })
287
288 #define iowrite16be(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_be16(v), p); })
289 #define iowrite32be(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_be32(v), p); })
290
291 #define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
292 #define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
293 #define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
294
295 #define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
296 #define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
297 #define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
298
299 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
300 extern void ioport_unmap(void __iomem *addr);
301 #endif
302
303 struct pci_dev;
304
305 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
306
307 /*
308 * can the hardware map this into one segment or not, given no other
309 * constraints.
310 */
311 #define BIOVEC_MERGEABLE(vec1, vec2) \
312 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
313
314 #ifdef CONFIG_MMU
315 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
316 extern int valid_phys_addr_range(unsigned long addr, size_t size);
317 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
318 extern int devmem_is_allowed(unsigned long pfn);
319 #endif
320
321 /*
322 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
323 * access
324 */
325 #define xlate_dev_mem_ptr(p) __va(p)
326
327 /*
328 * Convert a virtual cached pointer to an uncached pointer
329 */
330 #define xlate_dev_kmem_ptr(p) p
331
332 /*
333 * Register ISA memory and port locations for glibc iopl/inb/outb
334 * emulation.
335 */
336 extern void register_isa_ports(unsigned int mmio, unsigned int io,
337 unsigned int io_shift);
338
339 #endif /* __KERNEL__ */
340 #endif /* __ASM_ARM_IO_H */
341