1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * Copyright(c) 2020-2022 Intel Corporation. All rights reserved.
7  */
8 
9 /* DSP Registers */
10 #define MTL_HFDSSCS			0x1000
11 #define MTL_HFDSSCS_SPA_MASK		BIT(16)
12 #define MTL_HFDSSCS_CPA_MASK		BIT(24)
13 #define MTL_HFSNDWIE			0x114C
14 #define MTL_HFPWRCTL			0x1D18
15 #define MTL_HfPWRCTL_WPIOXPG(x)		BIT((x) + 8)
16 #define MTL_HFPWRCTL_WPDSPHPXPG		BIT(0)
17 #define MTL_HFPWRSTS			0x1D1C
18 #define MTL_HFPWRSTS_DSPHPXPGS_MASK	BIT(0)
19 #define MTL_HFINTIPPTR			0x1108
20 #define MTL_IRQ_INTEN_L_HOST_IPC_MASK	BIT(0)
21 #define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK	BIT(6)
22 #define MTL_HFINTIPPTR_PTR_MASK		GENMASK(20, 0)
23 
24 #define MTL_DSP2CXCAP_PRIMARY_CORE	0x178D00
25 #define MTL_DSP2CXCTL_PRIMARY_CORE	0x178D04
26 #define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK BIT(0)
27 #define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK BIT(8)
28 #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24)
29 #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT 24
30 
31 /* IPC Registers */
32 #define MTL_DSP_REG_HFIPCXTDR		0x73200
33 #define MTL_DSP_REG_HFIPCXTDR_BUSY	BIT(31)
34 #define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0)
35 #define MTL_DSP_REG_HFIPCXTDA		0x73204
36 #define MTL_DSP_REG_HFIPCXTDA_BUSY	BIT(31)
37 #define MTL_DSP_REG_HFIPCXIDR		0x73210
38 #define MTL_DSP_REG_HFIPCXIDR_BUSY	BIT(31)
39 #define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0)
40 #define MTL_DSP_REG_HFIPCXIDA		0x73214
41 #define MTL_DSP_REG_HFIPCXIDA_DONE	BIT(31)
42 #define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0)
43 #define MTL_DSP_REG_HFIPCXCTL		0x73228
44 #define MTL_DSP_REG_HFIPCXCTL_BUSY	BIT(0)
45 #define MTL_DSP_REG_HFIPCXCTL_DONE	BIT(1)
46 #define MTL_DSP_REG_HFIPCXTDDY		0x73300
47 #define MTL_DSP_REG_HFIPCXIDDY		0x73380
48 #define MTL_DSP_REG_HfHIPCIE		0x1140
49 #define MTL_DSP_REG_HfHIPCIE_IE_MASK	BIT(0)
50 #define MTL_DSP_REG_HfSNDWIE		0x114C
51 #define MTL_DSP_REG_HfSNDWIE_IE_MASK	GENMASK(3, 0)
52 
53 #define MTL_DSP_IRQSTS			0x20
54 #define MTL_DSP_IRQSTS_IPC		BIT(0)
55 #define MTL_DSP_IRQSTS_SDW		BIT(6)
56 
57 #define MTL_DSP_PURGE_TIMEOUT_US	20000000 /* 20s */
58 #define MTL_DSP_REG_POLL_INTERVAL_US	10	/* 10 us */
59 
60 /* Memory windows */
61 #define MTL_SRAM_WINDOW_OFFSET(x)	(0x180000 + 0x8000 * (x))
62 
63 #define MTL_DSP_MBOX_UPLINK_OFFSET	(MTL_SRAM_WINDOW_OFFSET(0) + 0x1000)
64 #define MTL_DSP_MBOX_UPLINK_SIZE	0x1000
65 #define MTL_DSP_MBOX_DOWNLINK_OFFSET	MTL_SRAM_WINDOW_OFFSET(1)
66 #define MTL_DSP_MBOX_DOWNLINK_SIZE	0x1000
67 
68 /* FW registers */
69 #define MTL_DSP_ROM_STS			MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */
70 #define MTL_DSP_ROM_ERROR		(MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */
71 
72 #define MTL_DSP_REG_HFFLGPXQWY		0x163200 /* ROM debug status */
73 #define MTL_DSP_REG_HFFLGPXQWY_ERROR	0x163204 /* ROM debug error code */
74 #define MTL_DSP_REG_HfIMRIS1		0x162088
75 #define MTL_DSP_REG_HfIMRIS1_IU_MASK	BIT(0)
76 
77