1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8186_MMSYS_H 4 #define __SOC_MEDIATEK_MT8186_MMSYS_H 5 6 /* Values for DPI configuration in MMSYS address space */ 7 #define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400 8 #define DPI_FORMAT_MASK 0x1 9 #define DPI_RGB888_DDR_CON BIT(0) 10 #define DPI_RGB565_SDR_CON BIT(1) 11 12 #define MT8186_MMSYS_OVL_CON 0xF04 13 #define MT8186_MMSYS_OVL0_CON_MASK 0x3 14 #define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC 15 #define MT8186_OVL0_GO_BLEND BIT(0) 16 #define MT8186_OVL0_GO_BG BIT(1) 17 #define MT8186_OVL0_2L_GO_BLEND BIT(2) 18 #define MT8186_OVL0_2L_GO_BG BIT(3) 19 #define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C 20 #define MT8186_RDMA0_SOUT_SEL_MASK 0xF 21 #define MT8186_RDMA0_SOUT_TO_DSI0 (0) 22 #define MT8186_RDMA0_SOUT_TO_COLOR0 (1) 23 #define MT8186_RDMA0_SOUT_TO_DPI0 (2) 24 #define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14 25 #define MT8186_OVL0_2L_MOUT_EN_MASK 0xF 26 #define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0) 27 #define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3) 28 #define MT8186_DISP_OVL0_MOUT_EN 0xF18 29 #define MT8186_OVL0_MOUT_EN_MASK 0xF 30 #define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0) 31 #define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3) 32 #define MT8186_DISP_DITHER0_MOUT_EN 0xF20 33 #define MT8186_DITHER0_MOUT_EN_MASK 0xF 34 #define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0) 35 #define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2) 36 #define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3) 37 #define MT8186_DISP_RDMA0_SEL_IN 0xF28 38 #define MT8186_RDMA0_SEL_IN_MASK 0xF 39 #define MT8186_RDMA0_FROM_OVL0 0 40 #define MT8186_RDMA0_FROM_OVL0_2L 2 41 #define MT8186_DISP_DSI0_SEL_IN 0xF30 42 #define MT8186_DSI0_SEL_IN_MASK 0xF 43 #define MT8186_DSI0_FROM_RDMA0 0 44 #define MT8186_DSI0_FROM_DITHER0 1 45 #define MT8186_DSI0_FROM_RDMA1 2 46 #define MT8186_DISP_RDMA1_MOUT_EN 0xF3C 47 #define MT8186_RDMA1_MOUT_EN_MASK 0xF 48 #define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0) 49 #define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2) 50 #define MT8186_DISP_RDMA1_SEL_IN 0xF40 51 #define MT8186_RDMA1_SEL_IN_MASK 0xF 52 #define MT8186_RDMA1_FROM_OVL0 0 53 #define MT8186_RDMA1_FROM_OVL0_2L 2 54 #define MT8186_RDMA1_FROM_DITHER0 3 55 #define MT8186_DISP_DPI0_SEL_IN 0xF44 56 #define MT8186_DPI0_SEL_IN_MASK 0xF 57 #define MT8186_DPI0_FROM_RDMA1 0 58 #define MT8186_DPI0_FROM_DITHER0 1 59 #define MT8186_DPI0_FROM_RDMA0 2 60 61 #define MT8186_MMSYS_SW0_RST_B 0x160 62 63 static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = { 64 { 65 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 66 MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK, 67 MT8186_OVL0_MOUT_TO_RDMA0 68 }, 69 { 70 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 71 MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK, 72 MT8186_RDMA0_FROM_OVL0 73 }, 74 { 75 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 76 MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK, 77 MT8186_OVL0_GO_BLEND 78 }, 79 { 80 DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, 81 MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK, 82 MT8186_RDMA0_SOUT_TO_COLOR0 83 }, 84 { 85 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 86 MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK, 87 MT8186_DITHER0_MOUT_TO_DSI0, 88 }, 89 { 90 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 91 MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK, 92 MT8186_DSI0_FROM_DITHER0 93 }, 94 { 95 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 96 MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK, 97 MT8186_OVL0_2L_MOUT_TO_RDMA1 98 }, 99 { 100 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 101 MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK, 102 MT8186_RDMA1_FROM_OVL0_2L 103 }, 104 { 105 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 106 MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK, 107 MT8186_OVL0_2L_GO_BLEND 108 }, 109 { 110 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 111 MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK, 112 MT8186_RDMA1_MOUT_TO_DPI0_SEL 113 }, 114 { 115 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 116 MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK, 117 MT8186_DPI0_FROM_RDMA1 118 }, 119 }; 120 121 #endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */ 122