1 /*
2 * AMD CS5535/CS5536 definitions
3 * Copyright (C) 2006 Advanced Micro Devices, Inc.
4 * Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 */
10
11 #ifndef _CS5535_H
12 #define _CS5535_H
13
14 /* MSRs */
15 #define MSR_GLIU_P2D_RO0 0x10000029
16
17 #define MSR_LX_GLD_MSR_CONFIG 0x48002001
18 #define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data
19 * sheet has the wrong value */
20 #define MSR_GLCP_SYS_RSTPLL 0x4C000014
21 #define MSR_GLCP_DOTPLL 0x4C000015
22
23 #define MSR_LBAR_SMB 0x5140000B
24 #define MSR_LBAR_GPIO 0x5140000C
25 #define MSR_LBAR_MFGPT 0x5140000D
26 #define MSR_LBAR_ACPI 0x5140000E
27 #define MSR_LBAR_PMS 0x5140000F
28
29 #define MSR_DIVIL_SOFT_RESET 0x51400017
30
31 #define MSR_PIC_YSEL_LOW 0x51400020
32 #define MSR_PIC_YSEL_HIGH 0x51400021
33 #define MSR_PIC_ZSEL_LOW 0x51400022
34 #define MSR_PIC_ZSEL_HIGH 0x51400023
35 #define MSR_PIC_IRQM_LPC 0x51400025
36
37 #define MSR_MFGPT_IRQ 0x51400028
38 #define MSR_MFGPT_NR 0x51400029
39 #define MSR_MFGPT_SETUP 0x5140002B
40
41 #define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */
42
43 #define MSR_GX_GLD_MSR_CONFIG 0xC0002001
44 #define MSR_GX_MSR_PADSEL 0xC0002011
45
46 /* resource sizes */
47 #define LBAR_GPIO_SIZE 0xFF
48 #define LBAR_MFGPT_SIZE 0x40
49 #define LBAR_ACPI_SIZE 0x40
50 #define LBAR_PMS_SIZE 0x80
51
52 /* VSA2 magic values */
53 #define VSA_VRC_INDEX 0xAC1C
54 #define VSA_VRC_DATA 0xAC1E
55 #define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */
56 #define VSA_VR_SIGNATURE 0x0003
57 #define VSA_VR_MEM_SIZE 0x0200
58 #define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
59 #define GSW_VSA_SIG 0x534d /* General Software signature */
60
61 #include <linux/io.h>
62
cs5535_has_vsa2(void)63 static inline int cs5535_has_vsa2(void)
64 {
65 static int has_vsa2 = -1;
66
67 if (has_vsa2 == -1) {
68 uint16_t val;
69
70 /*
71 * The VSA has virtual registers that we can query for a
72 * signature.
73 */
74 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
75 outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
76
77 val = inw(VSA_VRC_DATA);
78 has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
79 }
80
81 return has_vsa2;
82 }
83
84 /* GPIOs */
85 #define GPIO_OUTPUT_VAL 0x00
86 #define GPIO_OUTPUT_ENABLE 0x04
87 #define GPIO_OUTPUT_OPEN_DRAIN 0x08
88 #define GPIO_OUTPUT_INVERT 0x0C
89 #define GPIO_OUTPUT_AUX1 0x10
90 #define GPIO_OUTPUT_AUX2 0x14
91 #define GPIO_PULL_UP 0x18
92 #define GPIO_PULL_DOWN 0x1C
93 #define GPIO_INPUT_ENABLE 0x20
94 #define GPIO_INPUT_INVERT 0x24
95 #define GPIO_INPUT_FILTER 0x28
96 #define GPIO_INPUT_EVENT_COUNT 0x2C
97 #define GPIO_READ_BACK 0x30
98 #define GPIO_INPUT_AUX1 0x34
99 #define GPIO_EVENTS_ENABLE 0x38
100 #define GPIO_LOCK_ENABLE 0x3C
101 #define GPIO_POSITIVE_EDGE_EN 0x40
102 #define GPIO_NEGATIVE_EDGE_EN 0x44
103 #define GPIO_POSITIVE_EDGE_STS 0x48
104 #define GPIO_NEGATIVE_EDGE_STS 0x4C
105
106 #define GPIO_FLTR7_AMOUNT 0xD8
107
108 #define GPIO_MAP_X 0xE0
109 #define GPIO_MAP_Y 0xE4
110 #define GPIO_MAP_Z 0xE8
111 #define GPIO_MAP_W 0xEC
112
113 #define GPIO_FE7_SEL 0xF7
114
115 void cs5535_gpio_set(unsigned offset, unsigned int reg);
116 void cs5535_gpio_clear(unsigned offset, unsigned int reg);
117 int cs5535_gpio_isset(unsigned offset, unsigned int reg);
118 int cs5535_gpio_set_irq(unsigned group, unsigned irq);
119 void cs5535_gpio_setup_event(unsigned offset, int pair, int pme);
120
121 /* MFGPTs */
122
123 #define MFGPT_MAX_TIMERS 8
124 #define MFGPT_TIMER_ANY (-1)
125
126 #define MFGPT_DOMAIN_WORKING 1
127 #define MFGPT_DOMAIN_STANDBY 2
128 #define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
129
130 #define MFGPT_CMP1 0
131 #define MFGPT_CMP2 1
132
133 #define MFGPT_EVENT_IRQ 0
134 #define MFGPT_EVENT_NMI 1
135 #define MFGPT_EVENT_RESET 3
136
137 #define MFGPT_REG_CMP1 0
138 #define MFGPT_REG_CMP2 2
139 #define MFGPT_REG_COUNTER 4
140 #define MFGPT_REG_SETUP 6
141
142 #define MFGPT_SETUP_CNTEN (1 << 15)
143 #define MFGPT_SETUP_CMP2 (1 << 14)
144 #define MFGPT_SETUP_CMP1 (1 << 13)
145 #define MFGPT_SETUP_SETUP (1 << 12)
146 #define MFGPT_SETUP_STOPEN (1 << 11)
147 #define MFGPT_SETUP_EXTEN (1 << 10)
148 #define MFGPT_SETUP_REVEN (1 << 5)
149 #define MFGPT_SETUP_CLKSEL (1 << 4)
150
151 struct cs5535_mfgpt_timer;
152
153 extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
154 uint16_t reg);
155 extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
156 uint16_t value);
157
158 extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
159 int event, int enable);
160 extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
161 int *irq, int enable);
162 extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
163 int domain);
164 extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
165
cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer * timer,int cmp,int * irq)166 static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
167 int cmp, int *irq)
168 {
169 return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
170 }
171
cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer * timer,int cmp,int * irq)172 static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
173 int cmp, int *irq)
174 {
175 return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
176 }
177
178 #endif
179