1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * This file contains the routines for handling the MMU on those
4  * PowerPC implementations where the MMU substantially follows the
5  * architecture specification.  This includes the 6xx, 7xx, 7xxx,
6  * and 8260 implementations but excludes the 8xx and 4xx.
7  *  -- paulus
8  *
9  *  Derived from arch/ppc/mm/init.c:
10  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11  *
12  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
13  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
14  *    Copyright (C) 1996 Paul Mackerras
15  *
16  *  Derived from "arch/i386/mm/init.c"
17  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
18  */
19 
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <linux/init.h>
23 #include <linux/highmem.h>
24 #include <linux/memblock.h>
25 
26 #include <asm/mmu.h>
27 #include <asm/machdep.h>
28 #include <asm/code-patching.h>
29 #include <asm/sections.h>
30 
31 #include <mm/mmu_decl.h>
32 
33 u8 __initdata early_hash[SZ_256K] __aligned(SZ_256K) = {0};
34 
35 static struct hash_pte __initdata *Hash = (struct hash_pte *)early_hash;
36 static unsigned long __initdata Hash_size, Hash_mask;
37 static unsigned int __initdata hash_mb, hash_mb2;
38 unsigned long __initdata _SDR1;
39 
40 struct ppc_bat BATS[8][2];	/* 8 pairs of IBAT, DBAT */
41 
42 static struct batrange {	/* stores address ranges mapped by BATs */
43 	unsigned long start;
44 	unsigned long limit;
45 	phys_addr_t phys;
46 } bat_addrs[8];
47 
48 #ifdef CONFIG_SMP
49 unsigned long mmu_hash_lock;
50 #endif
51 
52 /*
53  * Return PA for this VA if it is mapped by a BAT, or 0
54  */
v_block_mapped(unsigned long va)55 phys_addr_t v_block_mapped(unsigned long va)
56 {
57 	int b;
58 	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
59 		if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
60 			return bat_addrs[b].phys + (va - bat_addrs[b].start);
61 	return 0;
62 }
63 
64 /*
65  * Return VA for a given PA or 0 if not mapped
66  */
p_block_mapped(phys_addr_t pa)67 unsigned long p_block_mapped(phys_addr_t pa)
68 {
69 	int b;
70 	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
71 		if (pa >= bat_addrs[b].phys
72 	    	    && pa < (bat_addrs[b].limit-bat_addrs[b].start)
73 		              +bat_addrs[b].phys)
74 			return bat_addrs[b].start+(pa-bat_addrs[b].phys);
75 	return 0;
76 }
77 
find_free_bat(void)78 int __init find_free_bat(void)
79 {
80 	int b;
81 	int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
82 
83 	for (b = 0; b < n; b++) {
84 		struct ppc_bat *bat = BATS[b];
85 
86 		if (!(bat[1].batu & 3))
87 			return b;
88 	}
89 	return -1;
90 }
91 
92 /*
93  * This function calculates the size of the larger block usable to map the
94  * beginning of an area based on the start address and size of that area:
95  * - max block size is 256 on 6xx.
96  * - base address must be aligned to the block size. So the maximum block size
97  *   is identified by the lowest bit set to 1 in the base address (for instance
98  *   if base is 0x16000000, max size is 0x02000000).
99  * - block size has to be a power of two. This is calculated by finding the
100  *   highest bit set to 1.
101  */
bat_block_size(unsigned long base,unsigned long top)102 unsigned int bat_block_size(unsigned long base, unsigned long top)
103 {
104 	unsigned int max_size = SZ_256M;
105 	unsigned int base_shift = (ffs(base) - 1) & 31;
106 	unsigned int block_shift = (fls(top - base) - 1) & 31;
107 
108 	return min3(max_size, 1U << base_shift, 1U << block_shift);
109 }
110 
111 /*
112  * Set up one of the IBAT (block address translation) register pairs.
113  * The parameters are not checked; in particular size must be a power
114  * of 2 between 128k and 256M.
115  */
setibat(int index,unsigned long virt,phys_addr_t phys,unsigned int size,pgprot_t prot)116 static void setibat(int index, unsigned long virt, phys_addr_t phys,
117 		    unsigned int size, pgprot_t prot)
118 {
119 	unsigned int bl = (size >> 17) - 1;
120 	int wimgxpp;
121 	struct ppc_bat *bat = BATS[index];
122 	unsigned long flags = pgprot_val(prot);
123 
124 	if (!cpu_has_feature(CPU_FTR_NEED_COHERENT))
125 		flags &= ~_PAGE_COHERENT;
126 
127 	wimgxpp = (flags & _PAGE_COHERENT) | (_PAGE_EXEC ? BPP_RX : BPP_XX);
128 	bat[0].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
129 	bat[0].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
130 	if (flags & _PAGE_USER)
131 		bat[0].batu |= 1;	/* Vp = 1 */
132 }
133 
clearibat(int index)134 static void clearibat(int index)
135 {
136 	struct ppc_bat *bat = BATS[index];
137 
138 	bat[0].batu = 0;
139 	bat[0].batl = 0;
140 }
141 
__mmu_mapin_ram(unsigned long base,unsigned long top)142 static unsigned long __init __mmu_mapin_ram(unsigned long base, unsigned long top)
143 {
144 	int idx;
145 
146 	while ((idx = find_free_bat()) != -1 && base != top) {
147 		unsigned int size = bat_block_size(base, top);
148 
149 		if (size < 128 << 10)
150 			break;
151 		setbat(idx, PAGE_OFFSET + base, base, size, PAGE_KERNEL_X);
152 		base += size;
153 	}
154 
155 	return base;
156 }
157 
mmu_mapin_ram(unsigned long base,unsigned long top)158 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
159 {
160 	unsigned long done;
161 	unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
162 	unsigned long size;
163 
164 	size = roundup_pow_of_two((unsigned long)_einittext - PAGE_OFFSET);
165 	setibat(0, PAGE_OFFSET, 0, size, PAGE_KERNEL_X);
166 
167 	if (debug_pagealloc_enabled_or_kfence() || __map_without_bats) {
168 		pr_debug_once("Read-Write memory mapped without BATs\n");
169 		if (base >= border)
170 			return base;
171 		if (top >= border)
172 			top = border;
173 	}
174 
175 	if (!strict_kernel_rwx_enabled() || base >= border || top <= border)
176 		return __mmu_mapin_ram(base, top);
177 
178 	done = __mmu_mapin_ram(base, border);
179 	if (done != border)
180 		return done;
181 
182 	return __mmu_mapin_ram(border, top);
183 }
184 
is_module_segment(unsigned long addr)185 static bool is_module_segment(unsigned long addr)
186 {
187 	if (!IS_ENABLED(CONFIG_MODULES))
188 		return false;
189 	if (addr < ALIGN_DOWN(MODULES_VADDR, SZ_256M))
190 		return false;
191 	if (addr > ALIGN(MODULES_END, SZ_256M) - 1)
192 		return false;
193 	return true;
194 }
195 
mmu_mark_initmem_nx(void)196 void mmu_mark_initmem_nx(void)
197 {
198 	int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
199 	int i;
200 	unsigned long base = (unsigned long)_stext - PAGE_OFFSET;
201 	unsigned long top = ALIGN((unsigned long)_etext - PAGE_OFFSET, SZ_128K);
202 	unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
203 	unsigned long size;
204 
205 	for (i = 0; i < nb - 1 && base < top;) {
206 		size = bat_block_size(base, top);
207 		setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
208 		base += size;
209 	}
210 	if (base < top) {
211 		size = bat_block_size(base, top);
212 		if ((top - base) > size) {
213 			size <<= 1;
214 			if (strict_kernel_rwx_enabled() && base + size > border)
215 				pr_warn("Some RW data is getting mapped X. "
216 					"Adjust CONFIG_DATA_SHIFT to avoid that.\n");
217 		}
218 		setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
219 		base += size;
220 	}
221 	for (; i < nb; i++)
222 		clearibat(i);
223 
224 	update_bats();
225 
226 	for (i = TASK_SIZE >> 28; i < 16; i++) {
227 		/* Do not set NX on VM space for modules */
228 		if (is_module_segment(i << 28))
229 			continue;
230 
231 		mtsr(mfsr(i << 28) | 0x10000000, i << 28);
232 	}
233 }
234 
mmu_mark_rodata_ro(void)235 void mmu_mark_rodata_ro(void)
236 {
237 	int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
238 	int i;
239 
240 	for (i = 0; i < nb; i++) {
241 		struct ppc_bat *bat = BATS[i];
242 
243 		if (bat_addrs[i].start < (unsigned long)__init_begin)
244 			bat[1].batl = (bat[1].batl & ~BPP_RW) | BPP_RX;
245 	}
246 
247 	update_bats();
248 }
249 
250 /*
251  * Set up one of the D BAT (block address translation) register pairs.
252  * The parameters are not checked; in particular size must be a power
253  * of 2 between 128k and 256M.
254  */
setbat(int index,unsigned long virt,phys_addr_t phys,unsigned int size,pgprot_t prot)255 void __init setbat(int index, unsigned long virt, phys_addr_t phys,
256 		   unsigned int size, pgprot_t prot)
257 {
258 	unsigned int bl;
259 	int wimgxpp;
260 	struct ppc_bat *bat;
261 	unsigned long flags = pgprot_val(prot);
262 
263 	if (index == -1)
264 		index = find_free_bat();
265 	if (index == -1) {
266 		pr_err("%s: no BAT available for mapping 0x%llx\n", __func__,
267 		       (unsigned long long)phys);
268 		return;
269 	}
270 	bat = BATS[index];
271 
272 	if ((flags & _PAGE_NO_CACHE) ||
273 	    (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
274 		flags &= ~_PAGE_COHERENT;
275 
276 	bl = (size >> 17) - 1;
277 	/* Do DBAT first */
278 	wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
279 			   | _PAGE_COHERENT | _PAGE_GUARDED);
280 	wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
281 	bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
282 	bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
283 	if (flags & _PAGE_USER)
284 		bat[1].batu |= 1; 	/* Vp = 1 */
285 	if (flags & _PAGE_GUARDED) {
286 		/* G bit must be zero in IBATs */
287 		flags &= ~_PAGE_EXEC;
288 	}
289 
290 	bat_addrs[index].start = virt;
291 	bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
292 	bat_addrs[index].phys = phys;
293 }
294 
295 /*
296  * Preload a translation in the hash table
297  */
hash_preload(struct mm_struct * mm,unsigned long ea)298 static void hash_preload(struct mm_struct *mm, unsigned long ea)
299 {
300 	pmd_t *pmd;
301 
302 	if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
303 		return;
304 	pmd = pmd_off(mm, ea);
305 	if (!pmd_none(*pmd))
306 		add_hash_page(mm->context.id, ea, pmd_val(*pmd));
307 }
308 
309 /*
310  * This is called at the end of handling a user page fault, when the
311  * fault has been handled by updating a PTE in the linux page tables.
312  * We use it to preload an HPTE into the hash table corresponding to
313  * the updated linux PTE.
314  *
315  * This must always be called with the pte lock held.
316  */
update_mmu_cache(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)317 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
318 		      pte_t *ptep)
319 {
320 	if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
321 		return;
322 	/*
323 	 * We don't need to worry about _PAGE_PRESENT here because we are
324 	 * called with either mm->page_table_lock held or ptl lock held
325 	 */
326 
327 	/* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
328 	if (!pte_young(*ptep) || address >= TASK_SIZE)
329 		return;
330 
331 	/* We have to test for regs NULL since init will get here first thing at boot */
332 	if (!current->thread.regs)
333 		return;
334 
335 	/* We also avoid filling the hash if not coming from a fault */
336 	if (TRAP(current->thread.regs) != 0x300 && TRAP(current->thread.regs) != 0x400)
337 		return;
338 
339 	hash_preload(vma->vm_mm, address);
340 }
341 
342 /*
343  * Initialize the hash table and patch the instructions in hashtable.S.
344  */
MMU_init_hw(void)345 void __init MMU_init_hw(void)
346 {
347 	unsigned int n_hpteg, lg_n_hpteg;
348 
349 	if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
350 		return;
351 
352 	if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
353 
354 #define LG_HPTEG_SIZE	6		/* 64 bytes per HPTEG */
355 #define SDR1_LOW_BITS	((n_hpteg - 1) >> 10)
356 #define MIN_N_HPTEG	1024		/* min 64kB hash table */
357 
358 	/*
359 	 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
360 	 * This is less than the recommended amount, but then
361 	 * Linux ain't AIX.
362 	 */
363 	n_hpteg = total_memory / (PAGE_SIZE * 8);
364 	if (n_hpteg < MIN_N_HPTEG)
365 		n_hpteg = MIN_N_HPTEG;
366 	lg_n_hpteg = __ilog2(n_hpteg);
367 	if (n_hpteg & (n_hpteg - 1)) {
368 		++lg_n_hpteg;		/* round up if not power of 2 */
369 		n_hpteg = 1 << lg_n_hpteg;
370 	}
371 	Hash_size = n_hpteg << LG_HPTEG_SIZE;
372 
373 	/*
374 	 * Find some memory for the hash table.
375 	 */
376 	if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
377 	Hash = memblock_alloc(Hash_size, Hash_size);
378 	if (!Hash)
379 		panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
380 		      __func__, Hash_size, Hash_size);
381 	_SDR1 = __pa(Hash) | SDR1_LOW_BITS;
382 
383 	pr_info("Total memory = %lldMB; using %ldkB for hash table\n",
384 		(unsigned long long)(total_memory >> 20), Hash_size >> 10);
385 
386 
387 	Hash_mask = n_hpteg - 1;
388 	hash_mb2 = hash_mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
389 	if (lg_n_hpteg > 16)
390 		hash_mb2 = 16 - LG_HPTEG_SIZE;
391 }
392 
MMU_init_hw_patch(void)393 void __init MMU_init_hw_patch(void)
394 {
395 	unsigned int hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
396 	unsigned int hash = (unsigned int)Hash - PAGE_OFFSET;
397 
398 	if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
399 		return;
400 
401 	if (ppc_md.progress)
402 		ppc_md.progress("hash:patch", 0x345);
403 	if (ppc_md.progress)
404 		ppc_md.progress("hash:done", 0x205);
405 
406 	/* WARNING: Make sure nothing can trigger a KASAN check past this point */
407 
408 	/*
409 	 * Patch up the instructions in hashtable.S:create_hpte
410 	 */
411 	modify_instruction_site(&patch__hash_page_A0, 0xffff, hash >> 16);
412 	modify_instruction_site(&patch__hash_page_A1, 0x7c0, hash_mb << 6);
413 	modify_instruction_site(&patch__hash_page_A2, 0x7c0, hash_mb2 << 6);
414 	modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);
415 	modify_instruction_site(&patch__hash_page_C, 0xffff, hmask);
416 
417 	/*
418 	 * Patch up the instructions in hashtable.S:flush_hash_page
419 	 */
420 	modify_instruction_site(&patch__flush_hash_A0, 0xffff, hash >> 16);
421 	modify_instruction_site(&patch__flush_hash_A1, 0x7c0, hash_mb << 6);
422 	modify_instruction_site(&patch__flush_hash_A2, 0x7c0, hash_mb2 << 6);
423 	modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);
424 }
425 
setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)426 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
427 				phys_addr_t first_memblock_size)
428 {
429 	/* We don't currently support the first MEMBLOCK not mapping 0
430 	 * physical on those processors
431 	 */
432 	BUG_ON(first_memblock_base != 0);
433 
434 	memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_256M));
435 }
436 
print_system_hash_info(void)437 void __init print_system_hash_info(void)
438 {
439 	pr_info("Hash_size         = 0x%lx\n", Hash_size);
440 	if (Hash_mask)
441 		pr_info("Hash_mask         = 0x%lx\n", Hash_mask);
442 }
443 
early_init_mmu(void)444 void __init early_init_mmu(void)
445 {
446 }
447