1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4 #ifndef _MLXSW_PCI_HW_H
5 #define _MLXSW_PCI_HW_H
6
7 #include <linux/bitops.h>
8
9 #include "item.h"
10
11 #define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */
12 #define MLXSW_PCI_PAGE_SIZE 4096
13
14 #define MLXSW_PCI_CIR_BASE 0x71000
15 #define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE
16 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
17 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
18 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
19 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
20 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
21 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
22 #define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23)
23 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22)
24 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12
25 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24
26 #define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000
27
28 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 900000
29 #define MLXSW_PCI_SW_RESET_WAIT_MSECS 200
30 #define MLXSW_PCI_FW_READY 0xA1844
31 #define MLXSW_PCI_FW_READY_MASK 0xFFFF
32 #define MLXSW_PCI_FW_READY_MAGIC 0x5E
33
34 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000
35 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200
36 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400
37 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600
38 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800
39 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00
40
41 #define MLXSW_PCI_DOORBELL(offset, type_offset, num) \
42 ((offset) + (type_offset) + (num) * 4)
43
44 #define MLXSW_PCI_CQS_MAX 96
45 #define MLXSW_PCI_EQS_COUNT 2
46 #define MLXSW_PCI_EQ_ASYNC_NUM 0
47 #define MLXSW_PCI_EQ_COMP_NUM 1
48
49 #define MLXSW_PCI_SDQS_MIN 2 /* EMAD and control traffic */
50 #define MLXSW_PCI_SDQ_EMAD_INDEX 0
51 #define MLXSW_PCI_SDQ_EMAD_TC 0
52 #define MLXSW_PCI_SDQ_CTL_TC 3
53
54 #define MLXSW_PCI_AQ_PAGES 8
55 #define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
56 #define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */
57 #define MLXSW_PCI_CQE01_SIZE 16 /* 16 bytes per element */
58 #define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */
59 #define MLXSW_PCI_CQE_SIZE_MAX MLXSW_PCI_CQE2_SIZE
60 #define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */
61 #define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
62 #define MLXSW_PCI_CQE01_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
63 #define MLXSW_PCI_CQE2_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
64 #define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
65 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80
66
67 #define MLXSW_PCI_WQE_SG_ENTRIES 3
68 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
69
70 /* pci_wqe_c
71 * If set it indicates that a completion should be reported upon
72 * execution of this descriptor.
73 */
74 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
75
76 /* pci_wqe_lp
77 * Local Processing, set if packet should be processed by the local
78 * switch hardware:
79 * For Ethernet EMAD (Direct Route and non Direct Route) -
80 * must be set if packet destination is local device
81 * For InfiniBand CTL - must be set if packet destination is local device
82 * Otherwise it must be clear
83 * Local Process packets must not exceed the size of 2K (including payload
84 * and headers).
85 */
86 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
87
88 /* pci_wqe_type
89 * Packet type.
90 */
91 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
92
93 /* pci_wqe_byte_count
94 * Size of i-th scatter/gather entry, 0 if entry is unused.
95 */
96 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
97
98 /* pci_wqe_address
99 * Physical address of i-th scatter/gather entry.
100 * Gather Entries must be 2Byte aligned.
101 */
102 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
103
104 enum mlxsw_pci_cqe_v {
105 MLXSW_PCI_CQE_V0,
106 MLXSW_PCI_CQE_V1,
107 MLXSW_PCI_CQE_V2,
108 };
109
110 #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \
111 static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \
112 { \
113 switch (v) { \
114 default: \
115 case MLXSW_PCI_CQE_V0: \
116 return mlxsw_pci_cqe##v0##_##name##_get(cqe); \
117 case MLXSW_PCI_CQE_V1: \
118 return mlxsw_pci_cqe##v1##_##name##_get(cqe); \
119 case MLXSW_PCI_CQE_V2: \
120 return mlxsw_pci_cqe##v2##_##name##_get(cqe); \
121 } \
122 } \
123 static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \
124 char *cqe, u32 val) \
125 { \
126 switch (v) { \
127 default: \
128 case MLXSW_PCI_CQE_V0: \
129 mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \
130 break; \
131 case MLXSW_PCI_CQE_V1: \
132 mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \
133 break; \
134 case MLXSW_PCI_CQE_V2: \
135 mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \
136 break; \
137 } \
138 }
139
140 /* pci_cqe_lag
141 * Packet arrives from a port which is a LAG
142 */
143 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
144 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
145 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
146
147 /* pci_cqe_system_port/lag_id
148 * When lag=0: System port on which the packet was received
149 * When lag=1:
150 * bits [15:4] LAG ID on which the packet was received
151 * bits [3:0] sub_port on which the packet was received
152 */
153 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
154 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
155 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
156 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
157 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
158 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
159 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
160
161 /* pci_cqe_wqe_counter
162 * WQE count of the WQEs completed on the associated dqn
163 */
164 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
165
166 /* pci_cqe_byte_count
167 * Byte count of received packets including additional two
168 * Reserved Bytes that are append to the end of the frame.
169 * Reserved for Send CQE.
170 */
171 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
172
173 #define MLXSW_PCI_CQE2_MIRROR_CONG_INVALID 0xFFFF
174
175 /* pci_cqe_mirror_cong_high
176 * Congestion level in units of 8KB of the egress traffic class of the original
177 * packet that does mirroring to the CPU. Value of 0xFFFF means that the
178 * congestion level is invalid.
179 */
180 MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);
181
182 /* pci_cqe_trap_id
183 * Trap ID that captured the packet.
184 */
185 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);
186
187 /* pci_cqe_crc
188 * Length include CRC. Indicates the length field includes
189 * the packet's CRC.
190 */
191 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
192 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
193 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
194
195 /* pci_cqe_e
196 * CQE with Error.
197 */
198 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
199 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
200 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
201
202 /* pci_cqe_sr
203 * 1 - Send Queue
204 * 0 - Receive Queue
205 */
206 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
207 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
208 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
209
210 /* pci_cqe_dqn
211 * Descriptor Queue (DQ) Number.
212 */
213 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
214 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
215 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
216
217 /* pci_cqe_time_stamp_low
218 * Time stamp of the CQE
219 * Format according to time_stamp_type:
220 * 0: uSec - 1.024uSec (default for devices which do not support
221 * time_stamp_type). Only bits 15:0 are valid
222 * 1: FRC - Free Running Clock - units of 1nSec
223 * 2: UTC - time_stamp[37:30] = Sec
224 * - time_stamp[29:0] = nSec
225 * 3: Mirror_UTC. UTC time stamp of the original packet that has
226 * MIRROR_SESSION traps
227 * - time_stamp[37:30] = Sec
228 * - time_stamp[29:0] = nSec
229 * Formats 0..2 are configured by
230 * CONFIG_PROFILE.cqe_time_stamp_type for PTP traps
231 * Format 3 is used for MIRROR_SESSION traps
232 * Note that Spectrum does not reveal FRC, UTC and Mirror_UTC
233 */
234 MLXSW_ITEM32(pci, cqe2, time_stamp_low, 0x0C, 16, 16);
235
236 #define MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID 0x1F
237
238 /* pci_cqe_mirror_tclass
239 * The egress traffic class of the original packet that does mirroring to the
240 * CPU. Value of 0x1F means that the traffic class is invalid.
241 */
242 MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);
243
244 /* pci_cqe_tx_lag
245 * The Tx port of a packet that is mirrored / sampled to the CPU is a LAG.
246 */
247 MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);
248
249 /* pci_cqe_tx_lag_subport
250 * The port index within the LAG of a packet that is mirrored / sampled to the
251 * CPU. Reserved when tx_lag is 0.
252 */
253 MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);
254
255 #define MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT 0xFFFE
256 #define MLXSW_PCI_CQE2_TX_PORT_INVALID 0xFFFF
257
258 /* pci_cqe_tx_lag_id
259 * The Tx LAG ID of the original packet that is mirrored / sampled to the CPU.
260 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx LAG ID
261 * is invalid. Reserved when tx_lag is 0.
262 */
263 MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);
264
265 /* pci_cqe_tx_system_port
266 * The Tx port of the original packet that is mirrored / sampled to the CPU.
267 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx port is
268 * invalid. Reserved when tx_lag is 1.
269 */
270 MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);
271
272 /* pci_cqe_mirror_cong_low
273 * Congestion level in units of 8KB of the egress traffic class of the original
274 * packet that does mirroring to the CPU. Value of 0xFFFF means that the
275 * congestion level is invalid.
276 */
277 MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);
278
279 #define MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT 13 /* Units of 8KB. */
280
mlxsw_pci_cqe2_mirror_cong_get(const char * cqe)281 static inline u16 mlxsw_pci_cqe2_mirror_cong_get(const char *cqe)
282 {
283 u16 cong_high = mlxsw_pci_cqe2_mirror_cong_high_get(cqe);
284 u16 cong_low = mlxsw_pci_cqe2_mirror_cong_low_get(cqe);
285
286 return cong_high << 12 | cong_low;
287 }
288
289 /* pci_cqe_user_def_val_orig_pkt_len
290 * When trap_id is an ACL: User defined value from policy engine action.
291 */
292 MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
293
294 /* pci_cqe_mirror_reason
295 * Mirror reason.
296 */
297 MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
298
299 enum mlxsw_pci_cqe_time_stamp_type {
300 MLXSW_PCI_CQE_TIME_STAMP_TYPE_USEC,
301 MLXSW_PCI_CQE_TIME_STAMP_TYPE_FRC,
302 MLXSW_PCI_CQE_TIME_STAMP_TYPE_UTC,
303 MLXSW_PCI_CQE_TIME_STAMP_TYPE_MIRROR_UTC,
304 };
305
306 /* pci_cqe_time_stamp_type
307 * Time stamp type:
308 * 0: uSec - 1.024uSec (default for devices which do not support
309 * time_stamp_type)
310 * 1: FRC - Free Running Clock - units of 1nSec
311 * 2: UTC
312 * 3: Mirror_UTC. UTC time stamp of the original packet that has
313 * MIRROR_SESSION traps
314 */
315 MLXSW_ITEM32(pci, cqe2, time_stamp_type, 0x18, 22, 2);
316
317 #define MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID 0xFFFFFF
318
319 /* pci_cqe_time_stamp_high
320 * Time stamp of the CQE
321 * Format according to time_stamp_type:
322 * 0: uSec - 1.024uSec (default for devices which do not support
323 * time_stamp_type). Only bits 15:0 are valid
324 * 1: FRC - Free Running Clock - units of 1nSec
325 * 2: UTC - time_stamp[37:30] = Sec
326 * - time_stamp[29:0] = nSec
327 * 3: Mirror_UTC. UTC time stamp of the original packet that has
328 * MIRROR_SESSION traps
329 * - time_stamp[37:30] = Sec
330 * - time_stamp[29:0] = nSec
331 * Formats 0..2 are configured by
332 * CONFIG_PROFILE.cqe_time_stamp_type for PTP traps
333 * Format 3 is used for MIRROR_SESSION traps
334 * Note that Spectrum does not reveal FRC, UTC and Mirror_UTC
335 */
336 MLXSW_ITEM32(pci, cqe2, time_stamp_high, 0x18, 0, 22);
337
mlxsw_pci_cqe2_time_stamp_get(const char * cqe)338 static inline u64 mlxsw_pci_cqe2_time_stamp_get(const char *cqe)
339 {
340 u64 ts_high = mlxsw_pci_cqe2_time_stamp_high_get(cqe);
341 u64 ts_low = mlxsw_pci_cqe2_time_stamp_low_get(cqe);
342
343 return ts_high << 16 | ts_low;
344 }
345
mlxsw_pci_cqe2_time_stamp_sec_get(const char * cqe)346 static inline u8 mlxsw_pci_cqe2_time_stamp_sec_get(const char *cqe)
347 {
348 u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);
349
350 return full_ts >> 30 & 0xFF;
351 }
352
mlxsw_pci_cqe2_time_stamp_nsec_get(const char * cqe)353 static inline u32 mlxsw_pci_cqe2_time_stamp_nsec_get(const char *cqe)
354 {
355 u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);
356
357 return full_ts & 0x3FFFFFFF;
358 }
359
360 /* pci_cqe_mirror_latency
361 * End-to-end latency of the original packet that does mirroring to the CPU.
362 * Value of 0xFFFFFF means that the latency is invalid. Units are according to
363 * MOGCR.mirror_latency_units.
364 */
365 MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);
366
367 /* pci_cqe_owner
368 * Ownership bit.
369 */
370 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
371 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
372 mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);
373
374 /* pci_eqe_event_type
375 * Event type.
376 */
377 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
378 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00
379 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A
380
381 /* pci_eqe_event_sub_type
382 * Event type.
383 */
384 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
385
386 /* pci_eqe_cqn
387 * Completion Queue that triggered this EQE.
388 */
389 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
390
391 /* pci_eqe_owner
392 * Ownership bit.
393 */
394 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
395
396 /* pci_eqe_cmd_token
397 * Command completion event - token
398 */
399 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
400
401 /* pci_eqe_cmd_status
402 * Command completion event - status
403 */
404 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
405
406 /* pci_eqe_cmd_out_param_h
407 * Command completion event - output parameter - higher part
408 */
409 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
410
411 /* pci_eqe_cmd_out_param_l
412 * Command completion event - output parameter - lower part
413 */
414 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
415
416 #endif
417