1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 #include <rdma/ib_user_ioctl_verbs.h> 40 41 enum { 42 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 43 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 44 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 45 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 46 MLX5_QP_FLAG_TYPE_DCT = 1 << 4, 47 MLX5_QP_FLAG_TYPE_DCI = 1 << 5, 48 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6, 49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7, 50 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8, 51 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9, 52 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, 53 MLX5_QP_FLAG_DCI_STREAM = 1 << 11, 54 }; 55 56 enum { 57 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 58 }; 59 60 enum { 61 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 62 }; 63 64 /* Increment this value if any changes that break userspace ABI 65 * compatibility are made. 66 */ 67 #define MLX5_IB_UVERBS_ABI_VERSION 1 68 69 /* Make sure that all structs defined in this file remain laid out so 70 * that they pack the same way on 32-bit and 64-bit architectures (to 71 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 72 * In particular do not use pointer types -- pass pointers in __u64 73 * instead. 74 */ 75 76 struct mlx5_ib_alloc_ucontext_req { 77 __u32 total_num_bfregs; 78 __u32 num_low_latency_bfregs; 79 }; 80 81 enum mlx5_lib_caps { 82 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 83 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1, 84 }; 85 86 enum mlx5_ib_alloc_uctx_v2_flags { 87 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 88 }; 89 struct mlx5_ib_alloc_ucontext_req_v2 { 90 __u32 total_num_bfregs; 91 __u32 num_low_latency_bfregs; 92 __u32 flags; 93 __u32 comp_mask; 94 __u8 max_cqe_version; 95 __u8 reserved0; 96 __u16 reserved1; 97 __u32 reserved2; 98 __aligned_u64 lib_caps; 99 }; 100 101 enum mlx5_ib_alloc_ucontext_resp_mask { 102 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 103 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1, 104 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2, 105 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3, 106 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4, 107 }; 108 109 enum mlx5_user_cmds_supp_uhw { 110 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 111 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 112 }; 113 114 /* The eth_min_inline response value is set to off-by-one vs the FW 115 * returned value to allow user-space to deal with older kernels. 116 */ 117 enum mlx5_user_inline_mode { 118 MLX5_USER_INLINE_MODE_NA, 119 MLX5_USER_INLINE_MODE_NONE, 120 MLX5_USER_INLINE_MODE_L2, 121 MLX5_USER_INLINE_MODE_IP, 122 MLX5_USER_INLINE_MODE_TCP_UDP, 123 }; 124 125 enum { 126 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, 127 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, 128 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, 129 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, 130 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, 131 }; 132 133 struct mlx5_ib_alloc_ucontext_resp { 134 __u32 qp_tab_size; 135 __u32 bf_reg_size; 136 __u32 tot_bfregs; 137 __u32 cache_line_size; 138 __u16 max_sq_desc_sz; 139 __u16 max_rq_desc_sz; 140 __u32 max_send_wqebb; 141 __u32 max_recv_wr; 142 __u32 max_srq_recv_wr; 143 __u16 num_ports; 144 __u16 flow_action_flags; 145 __u32 comp_mask; 146 __u32 response_length; 147 __u8 cqe_version; 148 __u8 cmds_supp_uhw; 149 __u8 eth_min_inline; 150 __u8 clock_info_versions; 151 __aligned_u64 hca_core_clock_offset; 152 __u32 log_uar_size; 153 __u32 num_uars_per_page; 154 __u32 num_dyn_bfregs; 155 __u32 dump_fill_mkey; 156 }; 157 158 struct mlx5_ib_alloc_pd_resp { 159 __u32 pdn; 160 }; 161 162 struct mlx5_ib_tso_caps { 163 __u32 max_tso; /* Maximum tso payload size in bytes */ 164 165 /* Corresponding bit will be set if qp type from 166 * 'enum ib_qp_type' is supported, e.g. 167 * supported_qpts |= 1 << IB_QPT_UD 168 */ 169 __u32 supported_qpts; 170 }; 171 172 struct mlx5_ib_rss_caps { 173 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 174 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 175 __u8 reserved[7]; 176 }; 177 178 enum mlx5_ib_cqe_comp_res_format { 179 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 180 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 181 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, 182 }; 183 184 struct mlx5_ib_cqe_comp_caps { 185 __u32 max_num; 186 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 187 }; 188 189 enum mlx5_ib_packet_pacing_cap_flags { 190 MLX5_IB_PP_SUPPORT_BURST = 1 << 0, 191 }; 192 193 struct mlx5_packet_pacing_caps { 194 __u32 qp_rate_limit_min; 195 __u32 qp_rate_limit_max; /* In kpbs */ 196 197 /* Corresponding bit will be set if qp type from 198 * 'enum ib_qp_type' is supported, e.g. 199 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 200 */ 201 __u32 supported_qpts; 202 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */ 203 __u8 reserved[3]; 204 }; 205 206 enum mlx5_ib_mpw_caps { 207 MPW_RESERVED = 1 << 0, 208 MLX5_IB_ALLOW_MPW = 1 << 1, 209 MLX5_IB_SUPPORT_EMPW = 1 << 2, 210 }; 211 212 enum mlx5_ib_sw_parsing_offloads { 213 MLX5_IB_SW_PARSING = 1 << 0, 214 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 215 MLX5_IB_SW_PARSING_LSO = 1 << 2, 216 }; 217 218 struct mlx5_ib_sw_parsing_caps { 219 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 220 221 /* Corresponding bit will be set if qp type from 222 * 'enum ib_qp_type' is supported, e.g. 223 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 224 */ 225 __u32 supported_qpts; 226 }; 227 228 struct mlx5_ib_striding_rq_caps { 229 __u32 min_single_stride_log_num_of_bytes; 230 __u32 max_single_stride_log_num_of_bytes; 231 __u32 min_single_wqe_log_num_of_strides; 232 __u32 max_single_wqe_log_num_of_strides; 233 234 /* Corresponding bit will be set if qp type from 235 * 'enum ib_qp_type' is supported, e.g. 236 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 237 */ 238 __u32 supported_qpts; 239 __u32 reserved; 240 }; 241 242 struct mlx5_ib_dci_streams_caps { 243 __u8 max_log_num_concurent; 244 __u8 max_log_num_errored; 245 }; 246 247 enum mlx5_ib_query_dev_resp_flags { 248 /* Support 128B CQE compression */ 249 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 250 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 251 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2, 252 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3, 253 }; 254 255 enum mlx5_ib_tunnel_offloads { 256 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 257 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 258 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2, 259 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3, 260 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4, 261 }; 262 263 struct mlx5_ib_query_device_resp { 264 __u32 comp_mask; 265 __u32 response_length; 266 struct mlx5_ib_tso_caps tso_caps; 267 struct mlx5_ib_rss_caps rss_caps; 268 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 269 struct mlx5_packet_pacing_caps packet_pacing_caps; 270 __u32 mlx5_ib_support_multi_pkt_send_wqes; 271 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */ 272 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 273 struct mlx5_ib_striding_rq_caps striding_rq_caps; 274 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 275 struct mlx5_ib_dci_streams_caps dci_streams_caps; 276 __u16 reserved; 277 }; 278 279 enum mlx5_ib_create_cq_flags { 280 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 281 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1, 282 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS = 1 << 2, 283 }; 284 285 struct mlx5_ib_create_cq { 286 __aligned_u64 buf_addr; 287 __aligned_u64 db_addr; 288 __u32 cqe_size; 289 __u8 cqe_comp_en; 290 __u8 cqe_comp_res_format; 291 __u16 flags; 292 __u16 uar_page_index; 293 __u16 reserved0; 294 __u32 reserved1; 295 }; 296 297 struct mlx5_ib_create_cq_resp { 298 __u32 cqn; 299 __u32 reserved; 300 }; 301 302 struct mlx5_ib_resize_cq { 303 __aligned_u64 buf_addr; 304 __u16 cqe_size; 305 __u16 reserved0; 306 __u32 reserved1; 307 }; 308 309 struct mlx5_ib_create_srq { 310 __aligned_u64 buf_addr; 311 __aligned_u64 db_addr; 312 __u32 flags; 313 __u32 reserved0; /* explicit padding (optional on i386) */ 314 __u32 uidx; 315 __u32 reserved1; 316 }; 317 318 struct mlx5_ib_create_srq_resp { 319 __u32 srqn; 320 __u32 reserved; 321 }; 322 323 struct mlx5_ib_create_qp_dci_streams { 324 __u8 log_num_concurent; 325 __u8 log_num_errored; 326 }; 327 328 struct mlx5_ib_create_qp { 329 __aligned_u64 buf_addr; 330 __aligned_u64 db_addr; 331 __u32 sq_wqe_count; 332 __u32 rq_wqe_count; 333 __u32 rq_wqe_shift; 334 __u32 flags; 335 __u32 uidx; 336 __u32 bfreg_index; 337 union { 338 __aligned_u64 sq_buf_addr; 339 __aligned_u64 access_key; 340 }; 341 __u32 ece_options; 342 struct mlx5_ib_create_qp_dci_streams dci_streams; 343 __u16 reserved; 344 }; 345 346 /* RX Hash function flags */ 347 enum mlx5_rx_hash_function_flags { 348 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 349 }; 350 351 /* 352 * RX Hash flags, these flags allows to set which incoming packet's field should 353 * participates in RX Hash. Each flag represent certain packet's field, 354 * when the flag is set the field that is represented by the flag will 355 * participate in RX Hash calculation. 356 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 357 * and *TCP and *UDP flags can't be enabled together on the same QP. 358 */ 359 enum mlx5_rx_hash_fields { 360 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 361 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 362 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 363 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 364 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 365 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 366 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 367 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 368 MLX5_RX_HASH_IPSEC_SPI = 1 << 8, 369 /* Save bits for future fields */ 370 MLX5_RX_HASH_INNER = (1UL << 31), 371 }; 372 373 struct mlx5_ib_create_qp_rss { 374 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 375 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 376 __u8 rx_key_len; /* valid only for Toeplitz */ 377 __u8 reserved[6]; 378 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 379 __u32 comp_mask; 380 __u32 flags; 381 }; 382 383 enum mlx5_ib_create_qp_resp_mask { 384 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0, 385 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1, 386 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2, 387 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3, 388 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4, 389 }; 390 391 struct mlx5_ib_create_qp_resp { 392 __u32 bfreg_index; 393 __u32 ece_options; 394 __u32 comp_mask; 395 __u32 tirn; 396 __u32 tisn; 397 __u32 rqn; 398 __u32 sqn; 399 __u32 reserved1; 400 __u64 tir_icm_addr; 401 }; 402 403 struct mlx5_ib_alloc_mw { 404 __u32 comp_mask; 405 __u8 num_klms; 406 __u8 reserved1; 407 __u16 reserved2; 408 }; 409 410 enum mlx5_ib_create_wq_mask { 411 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 412 }; 413 414 struct mlx5_ib_create_wq { 415 __aligned_u64 buf_addr; 416 __aligned_u64 db_addr; 417 __u32 rq_wqe_count; 418 __u32 rq_wqe_shift; 419 __u32 user_index; 420 __u32 flags; 421 __u32 comp_mask; 422 __u32 single_stride_log_num_of_bytes; 423 __u32 single_wqe_log_num_of_strides; 424 __u32 two_byte_shift_en; 425 }; 426 427 struct mlx5_ib_create_ah_resp { 428 __u32 response_length; 429 __u8 dmac[ETH_ALEN]; 430 __u8 reserved[6]; 431 }; 432 433 struct mlx5_ib_burst_info { 434 __u32 max_burst_sz; 435 __u16 typical_pkt_sz; 436 __u16 reserved; 437 }; 438 439 struct mlx5_ib_modify_qp { 440 __u32 comp_mask; 441 struct mlx5_ib_burst_info burst_info; 442 __u32 ece_options; 443 }; 444 445 struct mlx5_ib_modify_qp_resp { 446 __u32 response_length; 447 __u32 dctn; 448 __u32 ece_options; 449 __u32 reserved; 450 }; 451 452 struct mlx5_ib_create_wq_resp { 453 __u32 response_length; 454 __u32 reserved; 455 }; 456 457 struct mlx5_ib_create_rwq_ind_tbl_resp { 458 __u32 response_length; 459 __u32 reserved; 460 }; 461 462 struct mlx5_ib_modify_wq { 463 __u32 comp_mask; 464 __u32 reserved; 465 }; 466 467 struct mlx5_ib_clock_info { 468 __u32 sign; 469 __u32 resv; 470 __aligned_u64 nsec; 471 __aligned_u64 cycles; 472 __aligned_u64 frac; 473 __u32 mult; 474 __u32 shift; 475 __aligned_u64 mask; 476 __aligned_u64 overflow_period; 477 }; 478 479 enum mlx5_ib_mmap_cmd { 480 MLX5_IB_MMAP_REGULAR_PAGE = 0, 481 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 482 MLX5_IB_MMAP_WC_PAGE = 2, 483 MLX5_IB_MMAP_NC_PAGE = 3, 484 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 485 MLX5_IB_MMAP_CORE_CLOCK = 5, 486 MLX5_IB_MMAP_ALLOC_WC = 6, 487 MLX5_IB_MMAP_CLOCK_INFO = 7, 488 MLX5_IB_MMAP_DEVICE_MEM = 8, 489 }; 490 491 enum { 492 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, 493 }; 494 495 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 496 enum { 497 MLX5_IB_CLOCK_INFO_V1 = 0, 498 }; 499 500 struct mlx5_ib_flow_counters_desc { 501 __u32 description; 502 __u32 index; 503 }; 504 505 struct mlx5_ib_flow_counters_data { 506 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data); 507 __u32 ncounters; 508 __u32 reserved; 509 }; 510 511 struct mlx5_ib_create_flow { 512 __u32 ncounters_data; 513 __u32 reserved; 514 /* 515 * Following are counters data based on ncounters_data, each 516 * entry in the data[] should match a corresponding counter object 517 * that was pointed by a counters spec upon the flow creation 518 */ 519 struct mlx5_ib_flow_counters_data data[]; 520 }; 521 522 #endif /* MLX5_ABI_USER_H */ 523