1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_QP_H
34 #define MLX5_QP_H
35
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
38
39 #define MLX5_INVALID_LKEY 0x100
40 /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */
41 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8)
42 #define MLX5_DIF_SIZE 8
43 #define MLX5_STRIDE_BLOCK_OP 0x400
44 #define MLX5_CPY_GRD_MASK 0xc0
45 #define MLX5_CPY_APP_MASK 0x30
46 #define MLX5_CPY_REF_MASK 0x0f
47 #define MLX5_BSF_INC_REFTAG (1 << 6)
48 #define MLX5_BSF_INL_VALID (1 << 15)
49 #define MLX5_BSF_REFRESH_DIF (1 << 14)
50 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
51 #define MLX5_BSF_APPTAG_ESCAPE 0x1
52 #define MLX5_BSF_APPREF_ESCAPE 0x2
53
54 enum mlx5_qp_optpar {
55 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
56 MLX5_QP_OPTPAR_RRE = 1 << 1,
57 MLX5_QP_OPTPAR_RAE = 1 << 2,
58 MLX5_QP_OPTPAR_RWE = 1 << 3,
59 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
60 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
61 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
62 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
63 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
64 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
65 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
66 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
67 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
68 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
69 MLX5_QP_OPTPAR_LAG_TX_AFF = 1 << 15,
70 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
71 MLX5_QP_OPTPAR_SRQN = 1 << 18,
72 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
73 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
74 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
75 MLX5_QP_OPTPAR_COUNTER_SET_ID = 1 << 25,
76 };
77
78 enum mlx5_qp_state {
79 MLX5_QP_STATE_RST = 0,
80 MLX5_QP_STATE_INIT = 1,
81 MLX5_QP_STATE_RTR = 2,
82 MLX5_QP_STATE_RTS = 3,
83 MLX5_QP_STATE_SQER = 4,
84 MLX5_QP_STATE_SQD = 5,
85 MLX5_QP_STATE_ERR = 6,
86 MLX5_QP_STATE_SQ_DRAINING = 7,
87 MLX5_QP_STATE_SUSPENDED = 9,
88 MLX5_QP_NUM_STATE,
89 MLX5_QP_STATE,
90 MLX5_QP_STATE_BAD,
91 };
92
93 enum {
94 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
95 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
96 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
97 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
98 };
99
100 enum {
101 MLX5_QP_ST_RC = 0x0,
102 MLX5_QP_ST_UC = 0x1,
103 MLX5_QP_ST_UD = 0x2,
104 MLX5_QP_ST_XRC = 0x3,
105 MLX5_QP_ST_MLX = 0x4,
106 MLX5_QP_ST_DCI = 0x5,
107 MLX5_QP_ST_DCT = 0x6,
108 MLX5_QP_ST_QP0 = 0x7,
109 MLX5_QP_ST_QP1 = 0x8,
110 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
111 MLX5_QP_ST_RAW_IPV6 = 0xa,
112 MLX5_QP_ST_SNIFFER = 0xb,
113 MLX5_QP_ST_SYNC_UMR = 0xe,
114 MLX5_QP_ST_PTP_1588 = 0xd,
115 MLX5_QP_ST_REG_UMR = 0xc,
116 MLX5_QP_ST_MAX
117 };
118
119 enum {
120 MLX5_QP_PM_MIGRATED = 0x3,
121 MLX5_QP_PM_ARMED = 0x0,
122 MLX5_QP_PM_REARM = 0x1
123 };
124
125 enum {
126 MLX5_NON_ZERO_RQ = 0x0,
127 MLX5_SRQ_RQ = 0x1,
128 MLX5_CRQ_RQ = 0x2,
129 MLX5_ZERO_LEN_RQ = 0x3
130 };
131
132 /* TODO REM */
133 enum {
134 /* params1 */
135 MLX5_QP_BIT_SRE = 1 << 15,
136 MLX5_QP_BIT_SWE = 1 << 14,
137 MLX5_QP_BIT_SAE = 1 << 13,
138 /* params2 */
139 MLX5_QP_BIT_RRE = 1 << 15,
140 MLX5_QP_BIT_RWE = 1 << 14,
141 MLX5_QP_BIT_RAE = 1 << 13,
142 MLX5_QP_BIT_RIC = 1 << 4,
143 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
144 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
145 MLX5_QP_BIT_CC_MASTER = 1 << 0
146 };
147
148 enum {
149 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
150 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
151 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
152 };
153
154 enum {
155 MLX5_SEND_WQE_DS = 16,
156 MLX5_SEND_WQE_BB = 64,
157 };
158
159 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
160
161 enum {
162 MLX5_SEND_WQE_MAX_WQEBBS = 16,
163 };
164
165 enum {
166 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
167 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
168 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
169 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
170 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
171 };
172
173 enum {
174 MLX5_FENCE_MODE_NONE = 0 << 5,
175 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
176 MLX5_FENCE_MODE_FENCE = 2 << 5,
177 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
178 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
179 };
180
181 enum {
182 MLX5_RCV_DBR = 0,
183 MLX5_SND_DBR = 1,
184 };
185
186 enum {
187 MLX5_FLAGS_INLINE = 1<<7,
188 MLX5_FLAGS_CHECK_FREE = 1<<5,
189 };
190
191 struct mlx5_wqe_fmr_seg {
192 __be32 flags;
193 __be32 mem_key;
194 __be64 buf_list;
195 __be64 start_addr;
196 __be64 reg_len;
197 __be32 offset;
198 __be32 page_size;
199 u32 reserved[2];
200 };
201
202 struct mlx5_wqe_ctrl_seg {
203 __be32 opmod_idx_opcode;
204 __be32 qpn_ds;
205
206 struct_group(trailer,
207
208 u8 signature;
209 u8 rsvd[2];
210 u8 fm_ce_se;
211 union {
212 __be32 general_id;
213 __be32 imm;
214 __be32 umr_mkey;
215 __be32 tis_tir_num;
216 };
217
218 ); /* end of trailer group */
219 };
220
221 #define MLX5_WQE_CTRL_DS_MASK 0x3f
222 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
223 #define MLX5_WQE_CTRL_QPN_SHIFT 8
224 #define MLX5_WQE_DS_UNITS 16
225 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
226 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
227 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
228
229 enum {
230 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
231 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
232 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
233 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
234 };
235
236 enum {
237 MLX5_ETH_WQE_SVLAN = 1 << 0,
238 MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26,
239 MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27,
240 MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26,
241 MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28,
242 MLX5_ETH_WQE_INSERT_TRAILER = 1 << 30,
243 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15,
244 };
245
246 enum {
247 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0,
248 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1,
249 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4,
250 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5,
251 };
252
253 enum {
254 MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
255 };
256
257 struct mlx5_wqe_eth_seg {
258 u8 swp_outer_l4_offset;
259 u8 swp_outer_l3_offset;
260 u8 swp_inner_l4_offset;
261 u8 swp_inner_l3_offset;
262 u8 cs_flags;
263 u8 swp_flags;
264 __be16 mss;
265 __be32 flow_table_metadata;
266 union {
267 struct {
268 __be16 sz;
269 u8 start[2];
270 } inline_hdr;
271 struct {
272 __be16 type;
273 __be16 vlan_tci;
274 } insert;
275 __be32 trailer;
276 };
277 };
278
279 struct mlx5_wqe_xrc_seg {
280 __be32 xrc_srqn;
281 u8 rsvd[12];
282 };
283
284 struct mlx5_wqe_masked_atomic_seg {
285 __be64 swap_add;
286 __be64 compare;
287 __be64 swap_add_mask;
288 __be64 compare_mask;
289 };
290
291 struct mlx5_base_av {
292 union {
293 struct {
294 __be32 qkey;
295 __be32 reserved;
296 } qkey;
297 __be64 dc_key;
298 } key;
299 __be32 dqp_dct;
300 u8 stat_rate_sl;
301 u8 fl_mlid;
302 union {
303 __be16 rlid;
304 __be16 udp_sport;
305 };
306 };
307
308 struct mlx5_av {
309 union {
310 struct {
311 __be32 qkey;
312 __be32 reserved;
313 } qkey;
314 __be64 dc_key;
315 } key;
316 __be32 dqp_dct;
317 u8 stat_rate_sl;
318 u8 fl_mlid;
319 union {
320 __be16 rlid;
321 __be16 udp_sport;
322 };
323 u8 reserved0[4];
324 u8 rmac[6];
325 u8 tclass;
326 u8 hop_limit;
327 __be32 grh_gid_fl;
328 u8 rgid[16];
329 };
330
331 struct mlx5_ib_ah {
332 struct ib_ah ibah;
333 struct mlx5_av av;
334 u8 xmit_port;
335 };
336
to_mah(struct ib_ah * ibah)337 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
338 {
339 return container_of(ibah, struct mlx5_ib_ah, ibah);
340 }
341
342 struct mlx5_wqe_datagram_seg {
343 struct mlx5_av av;
344 };
345
346 struct mlx5_wqe_raddr_seg {
347 __be64 raddr;
348 __be32 rkey;
349 u32 reserved;
350 };
351
352 struct mlx5_wqe_atomic_seg {
353 __be64 swap_add;
354 __be64 compare;
355 };
356
357 struct mlx5_wqe_data_seg {
358 __be32 byte_count;
359 __be32 lkey;
360 __be64 addr;
361 };
362
363 struct mlx5_wqe_umr_ctrl_seg {
364 u8 flags;
365 u8 rsvd0[3];
366 __be16 xlt_octowords;
367 union {
368 __be16 xlt_offset;
369 __be16 bsf_octowords;
370 };
371 __be64 mkey_mask;
372 __be32 xlt_offset_47_16;
373 u8 rsvd1[28];
374 };
375
376 struct mlx5_seg_set_psv {
377 __be32 psv_num;
378 __be16 syndrome;
379 __be16 status;
380 __be32 transient_sig;
381 __be32 ref_tag;
382 };
383
384 struct mlx5_seg_get_psv {
385 u8 rsvd[19];
386 u8 num_psv;
387 __be32 l_key;
388 __be64 va;
389 __be32 psv_index[4];
390 };
391
392 struct mlx5_seg_check_psv {
393 u8 rsvd0[2];
394 __be16 err_coalescing_op;
395 u8 rsvd1[2];
396 __be16 xport_err_op;
397 u8 rsvd2[2];
398 __be16 xport_err_mask;
399 u8 rsvd3[7];
400 u8 num_psv;
401 __be32 l_key;
402 __be64 va;
403 __be32 psv_index[4];
404 };
405
406 struct mlx5_rwqe_sig {
407 u8 rsvd0[4];
408 u8 signature;
409 u8 rsvd1[11];
410 };
411
412 struct mlx5_wqe_signature_seg {
413 u8 rsvd0[4];
414 u8 signature;
415 u8 rsvd1[11];
416 };
417
418 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
419
420 struct mlx5_wqe_inline_seg {
421 __be32 byte_count;
422 __be32 data[];
423 };
424
425 enum mlx5_sig_type {
426 MLX5_DIF_CRC = 0x1,
427 MLX5_DIF_IPCS = 0x2,
428 };
429
430 struct mlx5_bsf_inl {
431 __be16 vld_refresh;
432 __be16 dif_apptag;
433 __be32 dif_reftag;
434 u8 sig_type;
435 u8 rp_inv_seed;
436 u8 rsvd[3];
437 u8 dif_inc_ref_guard_check;
438 __be16 dif_app_bitmask_check;
439 };
440
441 struct mlx5_bsf {
442 struct mlx5_bsf_basic {
443 u8 bsf_size_sbs;
444 u8 check_byte_mask;
445 union {
446 u8 copy_byte_mask;
447 u8 bs_selector;
448 u8 rsvd_wflags;
449 } wire;
450 union {
451 u8 bs_selector;
452 u8 rsvd_mflags;
453 } mem;
454 __be32 raw_data_size;
455 __be32 w_bfs_psv;
456 __be32 m_bfs_psv;
457 } basic;
458 struct mlx5_bsf_ext {
459 __be32 t_init_gen_pro_size;
460 __be32 rsvd_epi_size;
461 __be32 w_tfs_psv;
462 __be32 m_tfs_psv;
463 } ext;
464 struct mlx5_bsf_inl w_inl;
465 struct mlx5_bsf_inl m_inl;
466 };
467
468 struct mlx5_mtt {
469 __be64 ptag;
470 };
471
472 struct mlx5_klm {
473 __be32 bcount;
474 __be32 key;
475 __be64 va;
476 };
477
478 struct mlx5_stride_block_entry {
479 __be16 stride;
480 __be16 bcount;
481 __be32 key;
482 __be64 va;
483 };
484
485 struct mlx5_stride_block_ctrl_seg {
486 __be32 bcount_per_cycle;
487 __be32 op;
488 __be32 repeat_count;
489 u16 rsvd;
490 __be16 num_entries;
491 };
492
493 struct mlx5_core_qp {
494 struct mlx5_core_rsc_common common; /* must be first */
495 void (*event) (struct mlx5_core_qp *, int);
496 int qpn;
497 struct mlx5_rsc_debug *dbg;
498 int pid;
499 u16 uid;
500 };
501
502 struct mlx5_core_dct {
503 struct mlx5_core_qp mqp;
504 struct completion drained;
505 };
506
507 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
508 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
509
mlx5_qp_type_str(int type)510 static inline const char *mlx5_qp_type_str(int type)
511 {
512 switch (type) {
513 case MLX5_QP_ST_RC: return "RC";
514 case MLX5_QP_ST_UC: return "C";
515 case MLX5_QP_ST_UD: return "UD";
516 case MLX5_QP_ST_XRC: return "XRC";
517 case MLX5_QP_ST_MLX: return "MLX";
518 case MLX5_QP_ST_QP0: return "QP0";
519 case MLX5_QP_ST_QP1: return "QP1";
520 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
521 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
522 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
523 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
524 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
525 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
526 default: return "Invalid transport type";
527 }
528 }
529
mlx5_qp_state_str(int state)530 static inline const char *mlx5_qp_state_str(int state)
531 {
532 switch (state) {
533 case MLX5_QP_STATE_RST:
534 return "RST";
535 case MLX5_QP_STATE_INIT:
536 return "INIT";
537 case MLX5_QP_STATE_RTR:
538 return "RTR";
539 case MLX5_QP_STATE_RTS:
540 return "RTS";
541 case MLX5_QP_STATE_SQER:
542 return "SQER";
543 case MLX5_QP_STATE_SQD:
544 return "SQD";
545 case MLX5_QP_STATE_ERR:
546 return "ERR";
547 case MLX5_QP_STATE_SQ_DRAINING:
548 return "SQ_DRAINING";
549 case MLX5_QP_STATE_SUSPENDED:
550 return "SUSPENDED";
551 default: return "Invalid QP state";
552 }
553 }
554
mlx5_get_qp_default_ts(struct mlx5_core_dev * dev)555 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
556 {
557 return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
558 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING :
559 MLX5_TIMESTAMP_FORMAT_DEFAULT;
560 }
561
562 #endif /* MLX5_QP_H */
563