1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 }; 86 87 enum { 88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 90 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 91 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 92 MLX5_OBJ_TYPE_MKEY = 0xff01, 93 MLX5_OBJ_TYPE_QP = 0xff02, 94 MLX5_OBJ_TYPE_PSV = 0xff03, 95 MLX5_OBJ_TYPE_RMP = 0xff04, 96 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 97 MLX5_OBJ_TYPE_RQ = 0xff06, 98 MLX5_OBJ_TYPE_SQ = 0xff07, 99 MLX5_OBJ_TYPE_TIR = 0xff08, 100 MLX5_OBJ_TYPE_TIS = 0xff09, 101 MLX5_OBJ_TYPE_DCT = 0xff0a, 102 MLX5_OBJ_TYPE_XRQ = 0xff0b, 103 MLX5_OBJ_TYPE_RQT = 0xff0e, 104 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 105 MLX5_OBJ_TYPE_CQ = 0xff10, 106 }; 107 108 enum { 109 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 110 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 111 MLX5_CMD_OP_INIT_HCA = 0x102, 112 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 113 MLX5_CMD_OP_ENABLE_HCA = 0x104, 114 MLX5_CMD_OP_DISABLE_HCA = 0x105, 115 MLX5_CMD_OP_QUERY_PAGES = 0x107, 116 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 117 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 118 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 119 MLX5_CMD_OP_SET_ISSI = 0x10b, 120 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 121 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 122 MLX5_CMD_OP_ALLOC_SF = 0x113, 123 MLX5_CMD_OP_DEALLOC_SF = 0x114, 124 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 125 MLX5_CMD_OP_RESUME_VHCA = 0x116, 126 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 127 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 128 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 137 MLX5_CMD_OP_CREATE_EQ = 0x301, 138 MLX5_CMD_OP_DESTROY_EQ = 0x302, 139 MLX5_CMD_OP_QUERY_EQ = 0x303, 140 MLX5_CMD_OP_GEN_EQE = 0x304, 141 MLX5_CMD_OP_CREATE_CQ = 0x400, 142 MLX5_CMD_OP_DESTROY_CQ = 0x401, 143 MLX5_CMD_OP_QUERY_CQ = 0x402, 144 MLX5_CMD_OP_MODIFY_CQ = 0x403, 145 MLX5_CMD_OP_CREATE_QP = 0x500, 146 MLX5_CMD_OP_DESTROY_QP = 0x501, 147 MLX5_CMD_OP_RST2INIT_QP = 0x502, 148 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 149 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 150 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 152 MLX5_CMD_OP_2ERR_QP = 0x507, 153 MLX5_CMD_OP_2RST_QP = 0x50a, 154 MLX5_CMD_OP_QUERY_QP = 0x50b, 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 157 MLX5_CMD_OP_CREATE_PSV = 0x600, 158 MLX5_CMD_OP_DESTROY_PSV = 0x601, 159 MLX5_CMD_OP_CREATE_SRQ = 0x700, 160 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 161 MLX5_CMD_OP_QUERY_SRQ = 0x702, 162 MLX5_CMD_OP_ARM_RQ = 0x703, 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 167 MLX5_CMD_OP_CREATE_DCT = 0x710, 168 MLX5_CMD_OP_DESTROY_DCT = 0x711, 169 MLX5_CMD_OP_DRAIN_DCT = 0x712, 170 MLX5_CMD_OP_QUERY_DCT = 0x713, 171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 172 MLX5_CMD_OP_CREATE_XRQ = 0x717, 173 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 174 MLX5_CMD_OP_QUERY_XRQ = 0x719, 175 MLX5_CMD_OP_ARM_XRQ = 0x71a, 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 209 MLX5_CMD_OP_ALLOC_PD = 0x800, 210 MLX5_CMD_OP_DEALLOC_PD = 0x801, 211 MLX5_CMD_OP_ALLOC_UAR = 0x802, 212 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 214 MLX5_CMD_OP_ACCESS_REG = 0x805, 215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 218 MLX5_CMD_OP_MAD_IFC = 0x50d, 219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 221 MLX5_CMD_OP_NOP = 0x80d, 222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 238 MLX5_CMD_OP_CREATE_LAG = 0x840, 239 MLX5_CMD_OP_MODIFY_LAG = 0x841, 240 MLX5_CMD_OP_QUERY_LAG = 0x842, 241 MLX5_CMD_OP_DESTROY_LAG = 0x843, 242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 244 MLX5_CMD_OP_CREATE_TIR = 0x900, 245 MLX5_CMD_OP_MODIFY_TIR = 0x901, 246 MLX5_CMD_OP_DESTROY_TIR = 0x902, 247 MLX5_CMD_OP_QUERY_TIR = 0x903, 248 MLX5_CMD_OP_CREATE_SQ = 0x904, 249 MLX5_CMD_OP_MODIFY_SQ = 0x905, 250 MLX5_CMD_OP_DESTROY_SQ = 0x906, 251 MLX5_CMD_OP_QUERY_SQ = 0x907, 252 MLX5_CMD_OP_CREATE_RQ = 0x908, 253 MLX5_CMD_OP_MODIFY_RQ = 0x909, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 256 MLX5_CMD_OP_QUERY_RQ = 0x90b, 257 MLX5_CMD_OP_CREATE_RMP = 0x90c, 258 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 259 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 260 MLX5_CMD_OP_QUERY_RMP = 0x90f, 261 MLX5_CMD_OP_CREATE_TIS = 0x912, 262 MLX5_CMD_OP_MODIFY_TIS = 0x913, 263 MLX5_CMD_OP_DESTROY_TIS = 0x914, 264 MLX5_CMD_OP_QUERY_TIS = 0x915, 265 MLX5_CMD_OP_CREATE_RQT = 0x916, 266 MLX5_CMD_OP_MODIFY_RQT = 0x917, 267 MLX5_CMD_OP_DESTROY_RQT = 0x918, 268 MLX5_CMD_OP_QUERY_RQT = 0x919, 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 300 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 305 MLX5_CMD_OP_MAX 306 }; 307 308 /* Valid range for general commands that don't work over an object */ 309 enum { 310 MLX5_CMD_OP_GENERAL_START = 0xb00, 311 MLX5_CMD_OP_GENERAL_END = 0xd00, 312 }; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits { 315 u8 outer_dmac[0x1]; 316 u8 outer_smac[0x1]; 317 u8 outer_ether_type[0x1]; 318 u8 outer_ip_version[0x1]; 319 u8 outer_first_prio[0x1]; 320 u8 outer_first_cfi[0x1]; 321 u8 outer_first_vid[0x1]; 322 u8 outer_ipv4_ttl[0x1]; 323 u8 outer_second_prio[0x1]; 324 u8 outer_second_cfi[0x1]; 325 u8 outer_second_vid[0x1]; 326 u8 reserved_at_b[0x1]; 327 u8 outer_sip[0x1]; 328 u8 outer_dip[0x1]; 329 u8 outer_frag[0x1]; 330 u8 outer_ip_protocol[0x1]; 331 u8 outer_ip_ecn[0x1]; 332 u8 outer_ip_dscp[0x1]; 333 u8 outer_udp_sport[0x1]; 334 u8 outer_udp_dport[0x1]; 335 u8 outer_tcp_sport[0x1]; 336 u8 outer_tcp_dport[0x1]; 337 u8 outer_tcp_flags[0x1]; 338 u8 outer_gre_protocol[0x1]; 339 u8 outer_gre_key[0x1]; 340 u8 outer_vxlan_vni[0x1]; 341 u8 outer_geneve_vni[0x1]; 342 u8 outer_geneve_oam[0x1]; 343 u8 outer_geneve_protocol_type[0x1]; 344 u8 outer_geneve_opt_len[0x1]; 345 u8 source_vhca_port[0x1]; 346 u8 source_eswitch_port[0x1]; 347 348 u8 inner_dmac[0x1]; 349 u8 inner_smac[0x1]; 350 u8 inner_ether_type[0x1]; 351 u8 inner_ip_version[0x1]; 352 u8 inner_first_prio[0x1]; 353 u8 inner_first_cfi[0x1]; 354 u8 inner_first_vid[0x1]; 355 u8 reserved_at_27[0x1]; 356 u8 inner_second_prio[0x1]; 357 u8 inner_second_cfi[0x1]; 358 u8 inner_second_vid[0x1]; 359 u8 reserved_at_2b[0x1]; 360 u8 inner_sip[0x1]; 361 u8 inner_dip[0x1]; 362 u8 inner_frag[0x1]; 363 u8 inner_ip_protocol[0x1]; 364 u8 inner_ip_ecn[0x1]; 365 u8 inner_ip_dscp[0x1]; 366 u8 inner_udp_sport[0x1]; 367 u8 inner_udp_dport[0x1]; 368 u8 inner_tcp_sport[0x1]; 369 u8 inner_tcp_dport[0x1]; 370 u8 inner_tcp_flags[0x1]; 371 u8 reserved_at_37[0x9]; 372 373 u8 geneve_tlv_option_0_data[0x1]; 374 u8 geneve_tlv_option_0_exist[0x1]; 375 u8 reserved_at_42[0x3]; 376 u8 outer_first_mpls_over_udp[0x4]; 377 u8 outer_first_mpls_over_gre[0x4]; 378 u8 inner_first_mpls[0x4]; 379 u8 outer_first_mpls[0x4]; 380 u8 reserved_at_55[0x2]; 381 u8 outer_esp_spi[0x1]; 382 u8 reserved_at_58[0x2]; 383 u8 bth_dst_qp[0x1]; 384 u8 reserved_at_5b[0x5]; 385 386 u8 reserved_at_60[0x18]; 387 u8 metadata_reg_c_7[0x1]; 388 u8 metadata_reg_c_6[0x1]; 389 u8 metadata_reg_c_5[0x1]; 390 u8 metadata_reg_c_4[0x1]; 391 u8 metadata_reg_c_3[0x1]; 392 u8 metadata_reg_c_2[0x1]; 393 u8 metadata_reg_c_1[0x1]; 394 u8 metadata_reg_c_0[0x1]; 395 }; 396 397 struct mlx5_ifc_flow_table_fields_supported_2_bits { 398 u8 reserved_at_0[0xe]; 399 u8 bth_opcode[0x1]; 400 u8 reserved_at_f[0x11]; 401 402 u8 reserved_at_20[0x60]; 403 }; 404 405 struct mlx5_ifc_flow_table_prop_layout_bits { 406 u8 ft_support[0x1]; 407 u8 reserved_at_1[0x1]; 408 u8 flow_counter[0x1]; 409 u8 flow_modify_en[0x1]; 410 u8 modify_root[0x1]; 411 u8 identified_miss_table_mode[0x1]; 412 u8 flow_table_modify[0x1]; 413 u8 reformat[0x1]; 414 u8 decap[0x1]; 415 u8 reserved_at_9[0x1]; 416 u8 pop_vlan[0x1]; 417 u8 push_vlan[0x1]; 418 u8 reserved_at_c[0x1]; 419 u8 pop_vlan_2[0x1]; 420 u8 push_vlan_2[0x1]; 421 u8 reformat_and_vlan_action[0x1]; 422 u8 reserved_at_10[0x1]; 423 u8 sw_owner[0x1]; 424 u8 reformat_l3_tunnel_to_l2[0x1]; 425 u8 reformat_l2_to_l3_tunnel[0x1]; 426 u8 reformat_and_modify_action[0x1]; 427 u8 ignore_flow_level[0x1]; 428 u8 reserved_at_16[0x1]; 429 u8 table_miss_action_domain[0x1]; 430 u8 termination_table[0x1]; 431 u8 reformat_and_fwd_to_table[0x1]; 432 u8 reserved_at_1a[0x2]; 433 u8 ipsec_encrypt[0x1]; 434 u8 ipsec_decrypt[0x1]; 435 u8 sw_owner_v2[0x1]; 436 u8 reserved_at_1f[0x1]; 437 438 u8 termination_table_raw_traffic[0x1]; 439 u8 reserved_at_21[0x1]; 440 u8 log_max_ft_size[0x6]; 441 u8 log_max_modify_header_context[0x8]; 442 u8 max_modify_header_actions[0x8]; 443 u8 max_ft_level[0x8]; 444 445 u8 reserved_at_40[0x20]; 446 447 u8 reserved_at_60[0x2]; 448 u8 reformat_insert[0x1]; 449 u8 reformat_remove[0x1]; 450 u8 reserver_at_64[0x14]; 451 u8 log_max_ft_num[0x8]; 452 453 u8 reserved_at_80[0x10]; 454 u8 log_max_flow_counter[0x8]; 455 u8 log_max_destination[0x8]; 456 457 u8 reserved_at_a0[0x18]; 458 u8 log_max_flow[0x8]; 459 460 u8 reserved_at_c0[0x40]; 461 462 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 463 464 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 465 }; 466 467 struct mlx5_ifc_odp_per_transport_service_cap_bits { 468 u8 send[0x1]; 469 u8 receive[0x1]; 470 u8 write[0x1]; 471 u8 read[0x1]; 472 u8 atomic[0x1]; 473 u8 srq_receive[0x1]; 474 u8 reserved_at_6[0x1a]; 475 }; 476 477 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 478 u8 smac_47_16[0x20]; 479 480 u8 smac_15_0[0x10]; 481 u8 ethertype[0x10]; 482 483 u8 dmac_47_16[0x20]; 484 485 u8 dmac_15_0[0x10]; 486 u8 first_prio[0x3]; 487 u8 first_cfi[0x1]; 488 u8 first_vid[0xc]; 489 490 u8 ip_protocol[0x8]; 491 u8 ip_dscp[0x6]; 492 u8 ip_ecn[0x2]; 493 u8 cvlan_tag[0x1]; 494 u8 svlan_tag[0x1]; 495 u8 frag[0x1]; 496 u8 ip_version[0x4]; 497 u8 tcp_flags[0x9]; 498 499 u8 tcp_sport[0x10]; 500 u8 tcp_dport[0x10]; 501 502 u8 reserved_at_c0[0x10]; 503 u8 ipv4_ihl[0x4]; 504 u8 reserved_at_c4[0x4]; 505 506 u8 ttl_hoplimit[0x8]; 507 508 u8 udp_sport[0x10]; 509 u8 udp_dport[0x10]; 510 511 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 512 513 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 514 }; 515 516 struct mlx5_ifc_nvgre_key_bits { 517 u8 hi[0x18]; 518 u8 lo[0x8]; 519 }; 520 521 union mlx5_ifc_gre_key_bits { 522 struct mlx5_ifc_nvgre_key_bits nvgre; 523 u8 key[0x20]; 524 }; 525 526 struct mlx5_ifc_fte_match_set_misc_bits { 527 u8 gre_c_present[0x1]; 528 u8 reserved_at_1[0x1]; 529 u8 gre_k_present[0x1]; 530 u8 gre_s_present[0x1]; 531 u8 source_vhca_port[0x4]; 532 u8 source_sqn[0x18]; 533 534 u8 source_eswitch_owner_vhca_id[0x10]; 535 u8 source_port[0x10]; 536 537 u8 outer_second_prio[0x3]; 538 u8 outer_second_cfi[0x1]; 539 u8 outer_second_vid[0xc]; 540 u8 inner_second_prio[0x3]; 541 u8 inner_second_cfi[0x1]; 542 u8 inner_second_vid[0xc]; 543 544 u8 outer_second_cvlan_tag[0x1]; 545 u8 inner_second_cvlan_tag[0x1]; 546 u8 outer_second_svlan_tag[0x1]; 547 u8 inner_second_svlan_tag[0x1]; 548 u8 reserved_at_64[0xc]; 549 u8 gre_protocol[0x10]; 550 551 union mlx5_ifc_gre_key_bits gre_key; 552 553 u8 vxlan_vni[0x18]; 554 u8 bth_opcode[0x8]; 555 556 u8 geneve_vni[0x18]; 557 u8 reserved_at_d8[0x6]; 558 u8 geneve_tlv_option_0_exist[0x1]; 559 u8 geneve_oam[0x1]; 560 561 u8 reserved_at_e0[0xc]; 562 u8 outer_ipv6_flow_label[0x14]; 563 564 u8 reserved_at_100[0xc]; 565 u8 inner_ipv6_flow_label[0x14]; 566 567 u8 reserved_at_120[0xa]; 568 u8 geneve_opt_len[0x6]; 569 u8 geneve_protocol_type[0x10]; 570 571 u8 reserved_at_140[0x8]; 572 u8 bth_dst_qp[0x18]; 573 u8 reserved_at_160[0x20]; 574 u8 outer_esp_spi[0x20]; 575 u8 reserved_at_1a0[0x60]; 576 }; 577 578 struct mlx5_ifc_fte_match_mpls_bits { 579 u8 mpls_label[0x14]; 580 u8 mpls_exp[0x3]; 581 u8 mpls_s_bos[0x1]; 582 u8 mpls_ttl[0x8]; 583 }; 584 585 struct mlx5_ifc_fte_match_set_misc2_bits { 586 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 587 588 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 589 590 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 591 592 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 593 594 u8 metadata_reg_c_7[0x20]; 595 596 u8 metadata_reg_c_6[0x20]; 597 598 u8 metadata_reg_c_5[0x20]; 599 600 u8 metadata_reg_c_4[0x20]; 601 602 u8 metadata_reg_c_3[0x20]; 603 604 u8 metadata_reg_c_2[0x20]; 605 606 u8 metadata_reg_c_1[0x20]; 607 608 u8 metadata_reg_c_0[0x20]; 609 610 u8 metadata_reg_a[0x20]; 611 612 u8 reserved_at_1a0[0x60]; 613 }; 614 615 struct mlx5_ifc_fte_match_set_misc3_bits { 616 u8 inner_tcp_seq_num[0x20]; 617 618 u8 outer_tcp_seq_num[0x20]; 619 620 u8 inner_tcp_ack_num[0x20]; 621 622 u8 outer_tcp_ack_num[0x20]; 623 624 u8 reserved_at_80[0x8]; 625 u8 outer_vxlan_gpe_vni[0x18]; 626 627 u8 outer_vxlan_gpe_next_protocol[0x8]; 628 u8 outer_vxlan_gpe_flags[0x8]; 629 u8 reserved_at_b0[0x10]; 630 631 u8 icmp_header_data[0x20]; 632 633 u8 icmpv6_header_data[0x20]; 634 635 u8 icmp_type[0x8]; 636 u8 icmp_code[0x8]; 637 u8 icmpv6_type[0x8]; 638 u8 icmpv6_code[0x8]; 639 640 u8 geneve_tlv_option_0_data[0x20]; 641 642 u8 gtpu_teid[0x20]; 643 644 u8 gtpu_msg_type[0x8]; 645 u8 gtpu_msg_flags[0x8]; 646 u8 reserved_at_170[0x10]; 647 648 u8 gtpu_dw_2[0x20]; 649 650 u8 gtpu_first_ext_dw_0[0x20]; 651 652 u8 gtpu_dw_0[0x20]; 653 654 u8 reserved_at_1e0[0x20]; 655 }; 656 657 struct mlx5_ifc_fte_match_set_misc4_bits { 658 u8 prog_sample_field_value_0[0x20]; 659 660 u8 prog_sample_field_id_0[0x20]; 661 662 u8 prog_sample_field_value_1[0x20]; 663 664 u8 prog_sample_field_id_1[0x20]; 665 666 u8 prog_sample_field_value_2[0x20]; 667 668 u8 prog_sample_field_id_2[0x20]; 669 670 u8 prog_sample_field_value_3[0x20]; 671 672 u8 prog_sample_field_id_3[0x20]; 673 674 u8 reserved_at_100[0x100]; 675 }; 676 677 struct mlx5_ifc_fte_match_set_misc5_bits { 678 u8 macsec_tag_0[0x20]; 679 680 u8 macsec_tag_1[0x20]; 681 682 u8 macsec_tag_2[0x20]; 683 684 u8 macsec_tag_3[0x20]; 685 686 u8 tunnel_header_0[0x20]; 687 688 u8 tunnel_header_1[0x20]; 689 690 u8 tunnel_header_2[0x20]; 691 692 u8 tunnel_header_3[0x20]; 693 694 u8 reserved_at_100[0x100]; 695 }; 696 697 struct mlx5_ifc_cmd_pas_bits { 698 u8 pa_h[0x20]; 699 700 u8 pa_l[0x14]; 701 u8 reserved_at_34[0xc]; 702 }; 703 704 struct mlx5_ifc_uint64_bits { 705 u8 hi[0x20]; 706 707 u8 lo[0x20]; 708 }; 709 710 enum { 711 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 712 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 713 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 714 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 715 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 716 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 717 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 718 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 719 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 720 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 721 }; 722 723 struct mlx5_ifc_ads_bits { 724 u8 fl[0x1]; 725 u8 free_ar[0x1]; 726 u8 reserved_at_2[0xe]; 727 u8 pkey_index[0x10]; 728 729 u8 reserved_at_20[0x8]; 730 u8 grh[0x1]; 731 u8 mlid[0x7]; 732 u8 rlid[0x10]; 733 734 u8 ack_timeout[0x5]; 735 u8 reserved_at_45[0x3]; 736 u8 src_addr_index[0x8]; 737 u8 reserved_at_50[0x4]; 738 u8 stat_rate[0x4]; 739 u8 hop_limit[0x8]; 740 741 u8 reserved_at_60[0x4]; 742 u8 tclass[0x8]; 743 u8 flow_label[0x14]; 744 745 u8 rgid_rip[16][0x8]; 746 747 u8 reserved_at_100[0x4]; 748 u8 f_dscp[0x1]; 749 u8 f_ecn[0x1]; 750 u8 reserved_at_106[0x1]; 751 u8 f_eth_prio[0x1]; 752 u8 ecn[0x2]; 753 u8 dscp[0x6]; 754 u8 udp_sport[0x10]; 755 756 u8 dei_cfi[0x1]; 757 u8 eth_prio[0x3]; 758 u8 sl[0x4]; 759 u8 vhca_port_num[0x8]; 760 u8 rmac_47_32[0x10]; 761 762 u8 rmac_31_0[0x20]; 763 }; 764 765 struct mlx5_ifc_flow_table_nic_cap_bits { 766 u8 nic_rx_multi_path_tirs[0x1]; 767 u8 nic_rx_multi_path_tirs_fts[0x1]; 768 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 769 u8 reserved_at_3[0x4]; 770 u8 sw_owner_reformat_supported[0x1]; 771 u8 reserved_at_8[0x18]; 772 773 u8 encap_general_header[0x1]; 774 u8 reserved_at_21[0xa]; 775 u8 log_max_packet_reformat_context[0x5]; 776 u8 reserved_at_30[0x6]; 777 u8 max_encap_header_size[0xa]; 778 u8 reserved_at_40[0x1c0]; 779 780 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 781 782 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 783 784 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 785 786 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 787 788 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 789 790 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 791 792 u8 reserved_at_e00[0x700]; 793 794 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 795 796 u8 reserved_at_1580[0x280]; 797 798 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 799 800 u8 reserved_at_1880[0x780]; 801 802 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 803 804 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 805 806 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 807 808 u8 reserved_at_20c0[0x5f40]; 809 }; 810 811 struct mlx5_ifc_port_selection_cap_bits { 812 u8 reserved_at_0[0x10]; 813 u8 port_select_flow_table[0x1]; 814 u8 reserved_at_11[0xf]; 815 816 u8 reserved_at_20[0x1e0]; 817 818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 819 820 u8 reserved_at_400[0x7c00]; 821 }; 822 823 enum { 824 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 825 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 826 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 827 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 828 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 829 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 830 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 831 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 832 }; 833 834 struct mlx5_ifc_flow_table_eswitch_cap_bits { 835 u8 fdb_to_vport_reg_c_id[0x8]; 836 u8 reserved_at_8[0xd]; 837 u8 fdb_modify_header_fwd_to_table[0x1]; 838 u8 fdb_ipv4_ttl_modify[0x1]; 839 u8 flow_source[0x1]; 840 u8 reserved_at_18[0x2]; 841 u8 multi_fdb_encap[0x1]; 842 u8 egress_acl_forward_to_vport[0x1]; 843 u8 fdb_multi_path_to_table[0x1]; 844 u8 reserved_at_1d[0x3]; 845 846 u8 reserved_at_20[0x1e0]; 847 848 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 849 850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 851 852 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 853 854 u8 reserved_at_800[0x1000]; 855 856 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 857 858 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 859 860 u8 sw_steering_uplink_icm_address_rx[0x40]; 861 862 u8 sw_steering_uplink_icm_address_tx[0x40]; 863 864 u8 reserved_at_1900[0x6700]; 865 }; 866 867 enum { 868 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 869 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 870 }; 871 872 struct mlx5_ifc_e_switch_cap_bits { 873 u8 vport_svlan_strip[0x1]; 874 u8 vport_cvlan_strip[0x1]; 875 u8 vport_svlan_insert[0x1]; 876 u8 vport_cvlan_insert_if_not_exist[0x1]; 877 u8 vport_cvlan_insert_overwrite[0x1]; 878 u8 reserved_at_5[0x2]; 879 u8 esw_shared_ingress_acl[0x1]; 880 u8 esw_uplink_ingress_acl[0x1]; 881 u8 root_ft_on_other_esw[0x1]; 882 u8 reserved_at_a[0xf]; 883 u8 esw_functions_changed[0x1]; 884 u8 reserved_at_1a[0x1]; 885 u8 ecpf_vport_exists[0x1]; 886 u8 counter_eswitch_affinity[0x1]; 887 u8 merged_eswitch[0x1]; 888 u8 nic_vport_node_guid_modify[0x1]; 889 u8 nic_vport_port_guid_modify[0x1]; 890 891 u8 vxlan_encap_decap[0x1]; 892 u8 nvgre_encap_decap[0x1]; 893 u8 reserved_at_22[0x1]; 894 u8 log_max_fdb_encap_uplink[0x5]; 895 u8 reserved_at_21[0x3]; 896 u8 log_max_packet_reformat_context[0x5]; 897 u8 reserved_2b[0x6]; 898 u8 max_encap_header_size[0xa]; 899 900 u8 reserved_at_40[0xb]; 901 u8 log_max_esw_sf[0x5]; 902 u8 esw_sf_base_id[0x10]; 903 904 u8 reserved_at_60[0x7a0]; 905 906 }; 907 908 struct mlx5_ifc_qos_cap_bits { 909 u8 packet_pacing[0x1]; 910 u8 esw_scheduling[0x1]; 911 u8 esw_bw_share[0x1]; 912 u8 esw_rate_limit[0x1]; 913 u8 reserved_at_4[0x1]; 914 u8 packet_pacing_burst_bound[0x1]; 915 u8 packet_pacing_typical_size[0x1]; 916 u8 reserved_at_7[0x1]; 917 u8 nic_sq_scheduling[0x1]; 918 u8 nic_bw_share[0x1]; 919 u8 nic_rate_limit[0x1]; 920 u8 packet_pacing_uid[0x1]; 921 u8 log_esw_max_sched_depth[0x4]; 922 u8 reserved_at_10[0x10]; 923 924 u8 reserved_at_20[0xb]; 925 u8 log_max_qos_nic_queue_group[0x5]; 926 u8 reserved_at_30[0x10]; 927 928 u8 packet_pacing_max_rate[0x20]; 929 930 u8 packet_pacing_min_rate[0x20]; 931 932 u8 reserved_at_80[0x10]; 933 u8 packet_pacing_rate_table_size[0x10]; 934 935 u8 esw_element_type[0x10]; 936 u8 esw_tsar_type[0x10]; 937 938 u8 reserved_at_c0[0x10]; 939 u8 max_qos_para_vport[0x10]; 940 941 u8 max_tsar_bw_share[0x20]; 942 943 u8 reserved_at_100[0x700]; 944 }; 945 946 struct mlx5_ifc_debug_cap_bits { 947 u8 core_dump_general[0x1]; 948 u8 core_dump_qp[0x1]; 949 u8 reserved_at_2[0x7]; 950 u8 resource_dump[0x1]; 951 u8 reserved_at_a[0x16]; 952 953 u8 reserved_at_20[0x2]; 954 u8 stall_detect[0x1]; 955 u8 reserved_at_23[0x1d]; 956 957 u8 reserved_at_40[0x7c0]; 958 }; 959 960 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 961 u8 csum_cap[0x1]; 962 u8 vlan_cap[0x1]; 963 u8 lro_cap[0x1]; 964 u8 lro_psh_flag[0x1]; 965 u8 lro_time_stamp[0x1]; 966 u8 reserved_at_5[0x2]; 967 u8 wqe_vlan_insert[0x1]; 968 u8 self_lb_en_modifiable[0x1]; 969 u8 reserved_at_9[0x2]; 970 u8 max_lso_cap[0x5]; 971 u8 multi_pkt_send_wqe[0x2]; 972 u8 wqe_inline_mode[0x2]; 973 u8 rss_ind_tbl_cap[0x4]; 974 u8 reg_umr_sq[0x1]; 975 u8 scatter_fcs[0x1]; 976 u8 enhanced_multi_pkt_send_wqe[0x1]; 977 u8 tunnel_lso_const_out_ip_id[0x1]; 978 u8 tunnel_lro_gre[0x1]; 979 u8 tunnel_lro_vxlan[0x1]; 980 u8 tunnel_stateless_gre[0x1]; 981 u8 tunnel_stateless_vxlan[0x1]; 982 983 u8 swp[0x1]; 984 u8 swp_csum[0x1]; 985 u8 swp_lso[0x1]; 986 u8 cqe_checksum_full[0x1]; 987 u8 tunnel_stateless_geneve_tx[0x1]; 988 u8 tunnel_stateless_mpls_over_udp[0x1]; 989 u8 tunnel_stateless_mpls_over_gre[0x1]; 990 u8 tunnel_stateless_vxlan_gpe[0x1]; 991 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 992 u8 tunnel_stateless_ip_over_ip[0x1]; 993 u8 insert_trailer[0x1]; 994 u8 reserved_at_2b[0x1]; 995 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 996 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 997 u8 reserved_at_2e[0x2]; 998 u8 max_vxlan_udp_ports[0x8]; 999 u8 reserved_at_38[0x6]; 1000 u8 max_geneve_opt_len[0x1]; 1001 u8 tunnel_stateless_geneve_rx[0x1]; 1002 1003 u8 reserved_at_40[0x10]; 1004 u8 lro_min_mss_size[0x10]; 1005 1006 u8 reserved_at_60[0x120]; 1007 1008 u8 lro_timer_supported_periods[4][0x20]; 1009 1010 u8 reserved_at_200[0x600]; 1011 }; 1012 1013 enum { 1014 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1015 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1016 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1017 }; 1018 1019 struct mlx5_ifc_roce_cap_bits { 1020 u8 roce_apm[0x1]; 1021 u8 reserved_at_1[0x3]; 1022 u8 sw_r_roce_src_udp_port[0x1]; 1023 u8 fl_rc_qp_when_roce_disabled[0x1]; 1024 u8 fl_rc_qp_when_roce_enabled[0x1]; 1025 u8 reserved_at_7[0x17]; 1026 u8 qp_ts_format[0x2]; 1027 1028 u8 reserved_at_20[0x60]; 1029 1030 u8 reserved_at_80[0xc]; 1031 u8 l3_type[0x4]; 1032 u8 reserved_at_90[0x8]; 1033 u8 roce_version[0x8]; 1034 1035 u8 reserved_at_a0[0x10]; 1036 u8 r_roce_dest_udp_port[0x10]; 1037 1038 u8 r_roce_max_src_udp_port[0x10]; 1039 u8 r_roce_min_src_udp_port[0x10]; 1040 1041 u8 reserved_at_e0[0x10]; 1042 u8 roce_address_table_size[0x10]; 1043 1044 u8 reserved_at_100[0x700]; 1045 }; 1046 1047 struct mlx5_ifc_sync_steering_in_bits { 1048 u8 opcode[0x10]; 1049 u8 uid[0x10]; 1050 1051 u8 reserved_at_20[0x10]; 1052 u8 op_mod[0x10]; 1053 1054 u8 reserved_at_40[0xc0]; 1055 }; 1056 1057 struct mlx5_ifc_sync_steering_out_bits { 1058 u8 status[0x8]; 1059 u8 reserved_at_8[0x18]; 1060 1061 u8 syndrome[0x20]; 1062 1063 u8 reserved_at_40[0x40]; 1064 }; 1065 1066 struct mlx5_ifc_device_mem_cap_bits { 1067 u8 memic[0x1]; 1068 u8 reserved_at_1[0x1f]; 1069 1070 u8 reserved_at_20[0xb]; 1071 u8 log_min_memic_alloc_size[0x5]; 1072 u8 reserved_at_30[0x8]; 1073 u8 log_max_memic_addr_alignment[0x8]; 1074 1075 u8 memic_bar_start_addr[0x40]; 1076 1077 u8 memic_bar_size[0x20]; 1078 1079 u8 max_memic_size[0x20]; 1080 1081 u8 steering_sw_icm_start_address[0x40]; 1082 1083 u8 reserved_at_100[0x8]; 1084 u8 log_header_modify_sw_icm_size[0x8]; 1085 u8 reserved_at_110[0x2]; 1086 u8 log_sw_icm_alloc_granularity[0x6]; 1087 u8 log_steering_sw_icm_size[0x8]; 1088 1089 u8 reserved_at_120[0x20]; 1090 1091 u8 header_modify_sw_icm_start_address[0x40]; 1092 1093 u8 reserved_at_180[0x80]; 1094 1095 u8 memic_operations[0x20]; 1096 1097 u8 reserved_at_220[0x5e0]; 1098 }; 1099 1100 struct mlx5_ifc_device_event_cap_bits { 1101 u8 user_affiliated_events[4][0x40]; 1102 1103 u8 user_unaffiliated_events[4][0x40]; 1104 }; 1105 1106 struct mlx5_ifc_virtio_emulation_cap_bits { 1107 u8 desc_tunnel_offload_type[0x1]; 1108 u8 eth_frame_offload_type[0x1]; 1109 u8 virtio_version_1_0[0x1]; 1110 u8 device_features_bits_mask[0xd]; 1111 u8 event_mode[0x8]; 1112 u8 virtio_queue_type[0x8]; 1113 1114 u8 max_tunnel_desc[0x10]; 1115 u8 reserved_at_30[0x3]; 1116 u8 log_doorbell_stride[0x5]; 1117 u8 reserved_at_38[0x3]; 1118 u8 log_doorbell_bar_size[0x5]; 1119 1120 u8 doorbell_bar_offset[0x40]; 1121 1122 u8 max_emulated_devices[0x8]; 1123 u8 max_num_virtio_queues[0x18]; 1124 1125 u8 reserved_at_a0[0x60]; 1126 1127 u8 umem_1_buffer_param_a[0x20]; 1128 1129 u8 umem_1_buffer_param_b[0x20]; 1130 1131 u8 umem_2_buffer_param_a[0x20]; 1132 1133 u8 umem_2_buffer_param_b[0x20]; 1134 1135 u8 umem_3_buffer_param_a[0x20]; 1136 1137 u8 umem_3_buffer_param_b[0x20]; 1138 1139 u8 reserved_at_1c0[0x640]; 1140 }; 1141 1142 enum { 1143 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1144 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1145 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1146 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1147 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1148 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1149 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1150 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1151 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1152 }; 1153 1154 enum { 1155 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1156 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1157 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1163 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1164 }; 1165 1166 struct mlx5_ifc_atomic_caps_bits { 1167 u8 reserved_at_0[0x40]; 1168 1169 u8 atomic_req_8B_endianness_mode[0x2]; 1170 u8 reserved_at_42[0x4]; 1171 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1172 1173 u8 reserved_at_47[0x19]; 1174 1175 u8 reserved_at_60[0x20]; 1176 1177 u8 reserved_at_80[0x10]; 1178 u8 atomic_operations[0x10]; 1179 1180 u8 reserved_at_a0[0x10]; 1181 u8 atomic_size_qp[0x10]; 1182 1183 u8 reserved_at_c0[0x10]; 1184 u8 atomic_size_dc[0x10]; 1185 1186 u8 reserved_at_e0[0x720]; 1187 }; 1188 1189 struct mlx5_ifc_odp_cap_bits { 1190 u8 reserved_at_0[0x40]; 1191 1192 u8 sig[0x1]; 1193 u8 reserved_at_41[0x1f]; 1194 1195 u8 reserved_at_60[0x20]; 1196 1197 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1198 1199 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1200 1201 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1202 1203 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1204 1205 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1206 1207 u8 reserved_at_120[0x6E0]; 1208 }; 1209 1210 struct mlx5_ifc_calc_op { 1211 u8 reserved_at_0[0x10]; 1212 u8 reserved_at_10[0x9]; 1213 u8 op_swap_endianness[0x1]; 1214 u8 op_min[0x1]; 1215 u8 op_xor[0x1]; 1216 u8 op_or[0x1]; 1217 u8 op_and[0x1]; 1218 u8 op_max[0x1]; 1219 u8 op_add[0x1]; 1220 }; 1221 1222 struct mlx5_ifc_vector_calc_cap_bits { 1223 u8 calc_matrix[0x1]; 1224 u8 reserved_at_1[0x1f]; 1225 u8 reserved_at_20[0x8]; 1226 u8 max_vec_count[0x8]; 1227 u8 reserved_at_30[0xd]; 1228 u8 max_chunk_size[0x3]; 1229 struct mlx5_ifc_calc_op calc0; 1230 struct mlx5_ifc_calc_op calc1; 1231 struct mlx5_ifc_calc_op calc2; 1232 struct mlx5_ifc_calc_op calc3; 1233 1234 u8 reserved_at_c0[0x720]; 1235 }; 1236 1237 struct mlx5_ifc_tls_cap_bits { 1238 u8 tls_1_2_aes_gcm_128[0x1]; 1239 u8 tls_1_3_aes_gcm_128[0x1]; 1240 u8 tls_1_2_aes_gcm_256[0x1]; 1241 u8 tls_1_3_aes_gcm_256[0x1]; 1242 u8 reserved_at_4[0x1c]; 1243 1244 u8 reserved_at_20[0x7e0]; 1245 }; 1246 1247 struct mlx5_ifc_ipsec_cap_bits { 1248 u8 ipsec_full_offload[0x1]; 1249 u8 ipsec_crypto_offload[0x1]; 1250 u8 ipsec_esn[0x1]; 1251 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1252 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1253 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1254 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1255 u8 reserved_at_7[0x4]; 1256 u8 log_max_ipsec_offload[0x5]; 1257 u8 reserved_at_10[0x10]; 1258 1259 u8 min_log_ipsec_full_replay_window[0x8]; 1260 u8 max_log_ipsec_full_replay_window[0x8]; 1261 u8 reserved_at_30[0x7d0]; 1262 }; 1263 1264 enum { 1265 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1266 MLX5_WQ_TYPE_CYCLIC = 0x1, 1267 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1268 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1269 }; 1270 1271 enum { 1272 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1273 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1274 }; 1275 1276 enum { 1277 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1278 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1279 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1280 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1281 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1282 }; 1283 1284 enum { 1285 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1286 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1287 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1288 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1289 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1290 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1291 }; 1292 1293 enum { 1294 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1295 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1296 }; 1297 1298 enum { 1299 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1300 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1301 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1302 }; 1303 1304 enum { 1305 MLX5_CAP_PORT_TYPE_IB = 0x0, 1306 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1307 }; 1308 1309 enum { 1310 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1311 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1312 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1313 }; 1314 1315 enum { 1316 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1317 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1318 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1319 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1320 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1321 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1322 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1323 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1324 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1325 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1326 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1327 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1328 }; 1329 1330 enum { 1331 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1332 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1333 }; 1334 1335 #define MLX5_FC_BULK_SIZE_FACTOR 128 1336 1337 enum mlx5_fc_bulk_alloc_bitmask { 1338 MLX5_FC_BULK_128 = (1 << 0), 1339 MLX5_FC_BULK_256 = (1 << 1), 1340 MLX5_FC_BULK_512 = (1 << 2), 1341 MLX5_FC_BULK_1024 = (1 << 3), 1342 MLX5_FC_BULK_2048 = (1 << 4), 1343 MLX5_FC_BULK_4096 = (1 << 5), 1344 MLX5_FC_BULK_8192 = (1 << 6), 1345 MLX5_FC_BULK_16384 = (1 << 7), 1346 }; 1347 1348 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1349 1350 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1351 1352 enum { 1353 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1354 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1355 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1356 }; 1357 1358 struct mlx5_ifc_cmd_hca_cap_bits { 1359 u8 reserved_at_0[0x1f]; 1360 u8 vhca_resource_manager[0x1]; 1361 1362 u8 hca_cap_2[0x1]; 1363 u8 create_lag_when_not_master_up[0x1]; 1364 u8 dtor[0x1]; 1365 u8 event_on_vhca_state_teardown_request[0x1]; 1366 u8 event_on_vhca_state_in_use[0x1]; 1367 u8 event_on_vhca_state_active[0x1]; 1368 u8 event_on_vhca_state_allocated[0x1]; 1369 u8 event_on_vhca_state_invalid[0x1]; 1370 u8 reserved_at_28[0x8]; 1371 u8 vhca_id[0x10]; 1372 1373 u8 reserved_at_40[0x40]; 1374 1375 u8 log_max_srq_sz[0x8]; 1376 u8 log_max_qp_sz[0x8]; 1377 u8 event_cap[0x1]; 1378 u8 reserved_at_91[0x2]; 1379 u8 isolate_vl_tc_new[0x1]; 1380 u8 reserved_at_94[0x4]; 1381 u8 prio_tag_required[0x1]; 1382 u8 reserved_at_99[0x2]; 1383 u8 log_max_qp[0x5]; 1384 1385 u8 reserved_at_a0[0x3]; 1386 u8 ece_support[0x1]; 1387 u8 reserved_at_a4[0x5]; 1388 u8 reg_c_preserve[0x1]; 1389 u8 reserved_at_aa[0x1]; 1390 u8 log_max_srq[0x5]; 1391 u8 reserved_at_b0[0x1]; 1392 u8 uplink_follow[0x1]; 1393 u8 ts_cqe_to_dest_cqn[0x1]; 1394 u8 reserved_at_b3[0x7]; 1395 u8 shampo[0x1]; 1396 u8 reserved_at_bb[0x5]; 1397 1398 u8 max_sgl_for_optimized_performance[0x8]; 1399 u8 log_max_cq_sz[0x8]; 1400 u8 relaxed_ordering_write_umr[0x1]; 1401 u8 relaxed_ordering_read_umr[0x1]; 1402 u8 reserved_at_d2[0x7]; 1403 u8 virtio_net_device_emualtion_manager[0x1]; 1404 u8 virtio_blk_device_emualtion_manager[0x1]; 1405 u8 log_max_cq[0x5]; 1406 1407 u8 log_max_eq_sz[0x8]; 1408 u8 relaxed_ordering_write[0x1]; 1409 u8 relaxed_ordering_read[0x1]; 1410 u8 log_max_mkey[0x6]; 1411 u8 reserved_at_f0[0x8]; 1412 u8 dump_fill_mkey[0x1]; 1413 u8 reserved_at_f9[0x2]; 1414 u8 fast_teardown[0x1]; 1415 u8 log_max_eq[0x4]; 1416 1417 u8 max_indirection[0x8]; 1418 u8 fixed_buffer_size[0x1]; 1419 u8 log_max_mrw_sz[0x7]; 1420 u8 force_teardown[0x1]; 1421 u8 reserved_at_111[0x1]; 1422 u8 log_max_bsf_list_size[0x6]; 1423 u8 umr_extended_translation_offset[0x1]; 1424 u8 null_mkey[0x1]; 1425 u8 log_max_klm_list_size[0x6]; 1426 1427 u8 reserved_at_120[0xa]; 1428 u8 log_max_ra_req_dc[0x6]; 1429 u8 reserved_at_130[0xa]; 1430 u8 log_max_ra_res_dc[0x6]; 1431 1432 u8 reserved_at_140[0x5]; 1433 u8 release_all_pages[0x1]; 1434 u8 must_not_use[0x1]; 1435 u8 reserved_at_147[0x2]; 1436 u8 roce_accl[0x1]; 1437 u8 log_max_ra_req_qp[0x6]; 1438 u8 reserved_at_150[0xa]; 1439 u8 log_max_ra_res_qp[0x6]; 1440 1441 u8 end_pad[0x1]; 1442 u8 cc_query_allowed[0x1]; 1443 u8 cc_modify_allowed[0x1]; 1444 u8 start_pad[0x1]; 1445 u8 cache_line_128byte[0x1]; 1446 u8 reserved_at_165[0x4]; 1447 u8 rts2rts_qp_counters_set_id[0x1]; 1448 u8 reserved_at_16a[0x2]; 1449 u8 vnic_env_int_rq_oob[0x1]; 1450 u8 sbcam_reg[0x1]; 1451 u8 reserved_at_16e[0x1]; 1452 u8 qcam_reg[0x1]; 1453 u8 gid_table_size[0x10]; 1454 1455 u8 out_of_seq_cnt[0x1]; 1456 u8 vport_counters[0x1]; 1457 u8 retransmission_q_counters[0x1]; 1458 u8 debug[0x1]; 1459 u8 modify_rq_counter_set_id[0x1]; 1460 u8 rq_delay_drop[0x1]; 1461 u8 max_qp_cnt[0xa]; 1462 u8 pkey_table_size[0x10]; 1463 1464 u8 vport_group_manager[0x1]; 1465 u8 vhca_group_manager[0x1]; 1466 u8 ib_virt[0x1]; 1467 u8 eth_virt[0x1]; 1468 u8 vnic_env_queue_counters[0x1]; 1469 u8 ets[0x1]; 1470 u8 nic_flow_table[0x1]; 1471 u8 eswitch_manager[0x1]; 1472 u8 device_memory[0x1]; 1473 u8 mcam_reg[0x1]; 1474 u8 pcam_reg[0x1]; 1475 u8 local_ca_ack_delay[0x5]; 1476 u8 port_module_event[0x1]; 1477 u8 enhanced_error_q_counters[0x1]; 1478 u8 ports_check[0x1]; 1479 u8 reserved_at_1b3[0x1]; 1480 u8 disable_link_up[0x1]; 1481 u8 beacon_led[0x1]; 1482 u8 port_type[0x2]; 1483 u8 num_ports[0x8]; 1484 1485 u8 reserved_at_1c0[0x1]; 1486 u8 pps[0x1]; 1487 u8 pps_modify[0x1]; 1488 u8 log_max_msg[0x5]; 1489 u8 reserved_at_1c8[0x4]; 1490 u8 max_tc[0x4]; 1491 u8 temp_warn_event[0x1]; 1492 u8 dcbx[0x1]; 1493 u8 general_notification_event[0x1]; 1494 u8 reserved_at_1d3[0x2]; 1495 u8 fpga[0x1]; 1496 u8 rol_s[0x1]; 1497 u8 rol_g[0x1]; 1498 u8 reserved_at_1d8[0x1]; 1499 u8 wol_s[0x1]; 1500 u8 wol_g[0x1]; 1501 u8 wol_a[0x1]; 1502 u8 wol_b[0x1]; 1503 u8 wol_m[0x1]; 1504 u8 wol_u[0x1]; 1505 u8 wol_p[0x1]; 1506 1507 u8 stat_rate_support[0x10]; 1508 u8 reserved_at_1f0[0x1]; 1509 u8 pci_sync_for_fw_update_event[0x1]; 1510 u8 reserved_at_1f2[0x6]; 1511 u8 init2_lag_tx_port_affinity[0x1]; 1512 u8 reserved_at_1fa[0x3]; 1513 u8 cqe_version[0x4]; 1514 1515 u8 compact_address_vector[0x1]; 1516 u8 striding_rq[0x1]; 1517 u8 reserved_at_202[0x1]; 1518 u8 ipoib_enhanced_offloads[0x1]; 1519 u8 ipoib_basic_offloads[0x1]; 1520 u8 reserved_at_205[0x1]; 1521 u8 repeated_block_disabled[0x1]; 1522 u8 umr_modify_entity_size_disabled[0x1]; 1523 u8 umr_modify_atomic_disabled[0x1]; 1524 u8 umr_indirect_mkey_disabled[0x1]; 1525 u8 umr_fence[0x2]; 1526 u8 dc_req_scat_data_cqe[0x1]; 1527 u8 reserved_at_20d[0x2]; 1528 u8 drain_sigerr[0x1]; 1529 u8 cmdif_checksum[0x2]; 1530 u8 sigerr_cqe[0x1]; 1531 u8 reserved_at_213[0x1]; 1532 u8 wq_signature[0x1]; 1533 u8 sctr_data_cqe[0x1]; 1534 u8 reserved_at_216[0x1]; 1535 u8 sho[0x1]; 1536 u8 tph[0x1]; 1537 u8 rf[0x1]; 1538 u8 dct[0x1]; 1539 u8 qos[0x1]; 1540 u8 eth_net_offloads[0x1]; 1541 u8 roce[0x1]; 1542 u8 atomic[0x1]; 1543 u8 reserved_at_21f[0x1]; 1544 1545 u8 cq_oi[0x1]; 1546 u8 cq_resize[0x1]; 1547 u8 cq_moderation[0x1]; 1548 u8 reserved_at_223[0x3]; 1549 u8 cq_eq_remap[0x1]; 1550 u8 pg[0x1]; 1551 u8 block_lb_mc[0x1]; 1552 u8 reserved_at_229[0x1]; 1553 u8 scqe_break_moderation[0x1]; 1554 u8 cq_period_start_from_cqe[0x1]; 1555 u8 cd[0x1]; 1556 u8 reserved_at_22d[0x1]; 1557 u8 apm[0x1]; 1558 u8 vector_calc[0x1]; 1559 u8 umr_ptr_rlky[0x1]; 1560 u8 imaicl[0x1]; 1561 u8 qp_packet_based[0x1]; 1562 u8 reserved_at_233[0x3]; 1563 u8 qkv[0x1]; 1564 u8 pkv[0x1]; 1565 u8 set_deth_sqpn[0x1]; 1566 u8 reserved_at_239[0x3]; 1567 u8 xrc[0x1]; 1568 u8 ud[0x1]; 1569 u8 uc[0x1]; 1570 u8 rc[0x1]; 1571 1572 u8 uar_4k[0x1]; 1573 u8 reserved_at_241[0x9]; 1574 u8 uar_sz[0x6]; 1575 u8 port_selection_cap[0x1]; 1576 u8 reserved_at_248[0x1]; 1577 u8 umem_uid_0[0x1]; 1578 u8 reserved_at_250[0x5]; 1579 u8 log_pg_sz[0x8]; 1580 1581 u8 bf[0x1]; 1582 u8 driver_version[0x1]; 1583 u8 pad_tx_eth_packet[0x1]; 1584 u8 reserved_at_263[0x3]; 1585 u8 mkey_by_name[0x1]; 1586 u8 reserved_at_267[0x4]; 1587 1588 u8 log_bf_reg_size[0x5]; 1589 1590 u8 reserved_at_270[0x6]; 1591 u8 lag_dct[0x2]; 1592 u8 lag_tx_port_affinity[0x1]; 1593 u8 lag_native_fdb_selection[0x1]; 1594 u8 reserved_at_27a[0x1]; 1595 u8 lag_master[0x1]; 1596 u8 num_lag_ports[0x4]; 1597 1598 u8 reserved_at_280[0x10]; 1599 u8 max_wqe_sz_sq[0x10]; 1600 1601 u8 reserved_at_2a0[0x10]; 1602 u8 max_wqe_sz_rq[0x10]; 1603 1604 u8 max_flow_counter_31_16[0x10]; 1605 u8 max_wqe_sz_sq_dc[0x10]; 1606 1607 u8 reserved_at_2e0[0x7]; 1608 u8 max_qp_mcg[0x19]; 1609 1610 u8 reserved_at_300[0x10]; 1611 u8 flow_counter_bulk_alloc[0x8]; 1612 u8 log_max_mcg[0x8]; 1613 1614 u8 reserved_at_320[0x3]; 1615 u8 log_max_transport_domain[0x5]; 1616 u8 reserved_at_328[0x3]; 1617 u8 log_max_pd[0x5]; 1618 u8 reserved_at_330[0xb]; 1619 u8 log_max_xrcd[0x5]; 1620 1621 u8 nic_receive_steering_discard[0x1]; 1622 u8 receive_discard_vport_down[0x1]; 1623 u8 transmit_discard_vport_down[0x1]; 1624 u8 reserved_at_343[0x5]; 1625 u8 log_max_flow_counter_bulk[0x8]; 1626 u8 max_flow_counter_15_0[0x10]; 1627 1628 1629 u8 reserved_at_360[0x3]; 1630 u8 log_max_rq[0x5]; 1631 u8 reserved_at_368[0x3]; 1632 u8 log_max_sq[0x5]; 1633 u8 reserved_at_370[0x3]; 1634 u8 log_max_tir[0x5]; 1635 u8 reserved_at_378[0x3]; 1636 u8 log_max_tis[0x5]; 1637 1638 u8 basic_cyclic_rcv_wqe[0x1]; 1639 u8 reserved_at_381[0x2]; 1640 u8 log_max_rmp[0x5]; 1641 u8 reserved_at_388[0x3]; 1642 u8 log_max_rqt[0x5]; 1643 u8 reserved_at_390[0x3]; 1644 u8 log_max_rqt_size[0x5]; 1645 u8 reserved_at_398[0x3]; 1646 u8 log_max_tis_per_sq[0x5]; 1647 1648 u8 ext_stride_num_range[0x1]; 1649 u8 roce_rw_supported[0x1]; 1650 u8 log_max_current_uc_list_wr_supported[0x1]; 1651 u8 log_max_stride_sz_rq[0x5]; 1652 u8 reserved_at_3a8[0x3]; 1653 u8 log_min_stride_sz_rq[0x5]; 1654 u8 reserved_at_3b0[0x3]; 1655 u8 log_max_stride_sz_sq[0x5]; 1656 u8 reserved_at_3b8[0x3]; 1657 u8 log_min_stride_sz_sq[0x5]; 1658 1659 u8 hairpin[0x1]; 1660 u8 reserved_at_3c1[0x2]; 1661 u8 log_max_hairpin_queues[0x5]; 1662 u8 reserved_at_3c8[0x3]; 1663 u8 log_max_hairpin_wq_data_sz[0x5]; 1664 u8 reserved_at_3d0[0x3]; 1665 u8 log_max_hairpin_num_packets[0x5]; 1666 u8 reserved_at_3d8[0x3]; 1667 u8 log_max_wq_sz[0x5]; 1668 1669 u8 nic_vport_change_event[0x1]; 1670 u8 disable_local_lb_uc[0x1]; 1671 u8 disable_local_lb_mc[0x1]; 1672 u8 log_min_hairpin_wq_data_sz[0x5]; 1673 u8 reserved_at_3e8[0x2]; 1674 u8 vhca_state[0x1]; 1675 u8 log_max_vlan_list[0x5]; 1676 u8 reserved_at_3f0[0x3]; 1677 u8 log_max_current_mc_list[0x5]; 1678 u8 reserved_at_3f8[0x3]; 1679 u8 log_max_current_uc_list[0x5]; 1680 1681 u8 general_obj_types[0x40]; 1682 1683 u8 sq_ts_format[0x2]; 1684 u8 rq_ts_format[0x2]; 1685 u8 steering_format_version[0x4]; 1686 u8 create_qp_start_hint[0x18]; 1687 1688 u8 reserved_at_460[0x3]; 1689 u8 log_max_uctx[0x5]; 1690 u8 reserved_at_468[0x2]; 1691 u8 ipsec_offload[0x1]; 1692 u8 log_max_umem[0x5]; 1693 u8 max_num_eqs[0x10]; 1694 1695 u8 reserved_at_480[0x1]; 1696 u8 tls_tx[0x1]; 1697 u8 tls_rx[0x1]; 1698 u8 log_max_l2_table[0x5]; 1699 u8 reserved_at_488[0x8]; 1700 u8 log_uar_page_sz[0x10]; 1701 1702 u8 reserved_at_4a0[0x20]; 1703 u8 device_frequency_mhz[0x20]; 1704 u8 device_frequency_khz[0x20]; 1705 1706 u8 reserved_at_500[0x20]; 1707 u8 num_of_uars_per_page[0x20]; 1708 1709 u8 flex_parser_protocols[0x20]; 1710 1711 u8 max_geneve_tlv_options[0x8]; 1712 u8 reserved_at_568[0x3]; 1713 u8 max_geneve_tlv_option_data_len[0x5]; 1714 u8 reserved_at_570[0x10]; 1715 1716 u8 reserved_at_580[0xb]; 1717 u8 log_max_dci_stream_channels[0x5]; 1718 u8 reserved_at_590[0x3]; 1719 u8 log_max_dci_errored_streams[0x5]; 1720 u8 reserved_at_598[0x8]; 1721 1722 u8 reserved_at_5a0[0x13]; 1723 u8 log_max_dek[0x5]; 1724 u8 reserved_at_5b8[0x4]; 1725 u8 mini_cqe_resp_stride_index[0x1]; 1726 u8 cqe_128_always[0x1]; 1727 u8 cqe_compression_128[0x1]; 1728 u8 cqe_compression[0x1]; 1729 1730 u8 cqe_compression_timeout[0x10]; 1731 u8 cqe_compression_max_num[0x10]; 1732 1733 u8 reserved_at_5e0[0x8]; 1734 u8 flex_parser_id_gtpu_dw_0[0x4]; 1735 u8 reserved_at_5ec[0x4]; 1736 u8 tag_matching[0x1]; 1737 u8 rndv_offload_rc[0x1]; 1738 u8 rndv_offload_dc[0x1]; 1739 u8 log_tag_matching_list_sz[0x5]; 1740 u8 reserved_at_5f8[0x3]; 1741 u8 log_max_xrq[0x5]; 1742 1743 u8 affiliate_nic_vport_criteria[0x8]; 1744 u8 native_port_num[0x8]; 1745 u8 num_vhca_ports[0x8]; 1746 u8 flex_parser_id_gtpu_teid[0x4]; 1747 u8 reserved_at_61c[0x2]; 1748 u8 sw_owner_id[0x1]; 1749 u8 reserved_at_61f[0x1]; 1750 1751 u8 max_num_of_monitor_counters[0x10]; 1752 u8 num_ppcnt_monitor_counters[0x10]; 1753 1754 u8 max_num_sf[0x10]; 1755 u8 num_q_monitor_counters[0x10]; 1756 1757 u8 reserved_at_660[0x20]; 1758 1759 u8 sf[0x1]; 1760 u8 sf_set_partition[0x1]; 1761 u8 reserved_at_682[0x1]; 1762 u8 log_max_sf[0x5]; 1763 u8 apu[0x1]; 1764 u8 reserved_at_689[0x4]; 1765 u8 migration[0x1]; 1766 u8 reserved_at_68e[0x2]; 1767 u8 log_min_sf_size[0x8]; 1768 u8 max_num_sf_partitions[0x8]; 1769 1770 u8 uctx_cap[0x20]; 1771 1772 u8 reserved_at_6c0[0x4]; 1773 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1774 u8 flex_parser_id_icmp_dw1[0x4]; 1775 u8 flex_parser_id_icmp_dw0[0x4]; 1776 u8 flex_parser_id_icmpv6_dw1[0x4]; 1777 u8 flex_parser_id_icmpv6_dw0[0x4]; 1778 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1779 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1780 1781 u8 max_num_match_definer[0x10]; 1782 u8 sf_base_id[0x10]; 1783 1784 u8 flex_parser_id_gtpu_dw_2[0x4]; 1785 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1786 u8 num_total_dynamic_vf_msix[0x18]; 1787 u8 reserved_at_720[0x14]; 1788 u8 dynamic_msix_table_size[0xc]; 1789 u8 reserved_at_740[0xc]; 1790 u8 min_dynamic_vf_msix_table_size[0x4]; 1791 u8 reserved_at_750[0x4]; 1792 u8 max_dynamic_vf_msix_table_size[0xc]; 1793 1794 u8 reserved_at_760[0x20]; 1795 u8 vhca_tunnel_commands[0x40]; 1796 u8 match_definer_format_supported[0x40]; 1797 }; 1798 1799 struct mlx5_ifc_cmd_hca_cap_2_bits { 1800 u8 reserved_at_0[0xa0]; 1801 1802 u8 max_reformat_insert_size[0x8]; 1803 u8 max_reformat_insert_offset[0x8]; 1804 u8 max_reformat_remove_size[0x8]; 1805 u8 max_reformat_remove_offset[0x8]; 1806 1807 u8 reserved_at_c0[0x160]; 1808 1809 u8 reserved_at_220[0x1]; 1810 u8 sw_vhca_id_valid[0x1]; 1811 u8 sw_vhca_id[0xe]; 1812 u8 reserved_at_230[0x10]; 1813 1814 u8 reserved_at_240[0x5c0]; 1815 }; 1816 1817 enum mlx5_ifc_flow_destination_type { 1818 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1819 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1820 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1821 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1822 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1823 }; 1824 1825 enum mlx5_flow_table_miss_action { 1826 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1827 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1828 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1829 }; 1830 1831 struct mlx5_ifc_dest_format_struct_bits { 1832 u8 destination_type[0x8]; 1833 u8 destination_id[0x18]; 1834 1835 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1836 u8 packet_reformat[0x1]; 1837 u8 reserved_at_22[0xe]; 1838 u8 destination_eswitch_owner_vhca_id[0x10]; 1839 }; 1840 1841 struct mlx5_ifc_flow_counter_list_bits { 1842 u8 flow_counter_id[0x20]; 1843 1844 u8 reserved_at_20[0x20]; 1845 }; 1846 1847 struct mlx5_ifc_extended_dest_format_bits { 1848 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1849 1850 u8 packet_reformat_id[0x20]; 1851 1852 u8 reserved_at_60[0x20]; 1853 }; 1854 1855 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1856 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1857 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1858 }; 1859 1860 struct mlx5_ifc_fte_match_param_bits { 1861 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1862 1863 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1864 1865 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1866 1867 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1868 1869 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1870 1871 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1872 1873 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1874 1875 u8 reserved_at_e00[0x200]; 1876 }; 1877 1878 enum { 1879 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1880 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1881 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1882 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1883 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1884 }; 1885 1886 struct mlx5_ifc_rx_hash_field_select_bits { 1887 u8 l3_prot_type[0x1]; 1888 u8 l4_prot_type[0x1]; 1889 u8 selected_fields[0x1e]; 1890 }; 1891 1892 enum { 1893 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1894 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1895 }; 1896 1897 enum { 1898 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1899 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1900 }; 1901 1902 struct mlx5_ifc_wq_bits { 1903 u8 wq_type[0x4]; 1904 u8 wq_signature[0x1]; 1905 u8 end_padding_mode[0x2]; 1906 u8 cd_slave[0x1]; 1907 u8 reserved_at_8[0x18]; 1908 1909 u8 hds_skip_first_sge[0x1]; 1910 u8 log2_hds_buf_size[0x3]; 1911 u8 reserved_at_24[0x7]; 1912 u8 page_offset[0x5]; 1913 u8 lwm[0x10]; 1914 1915 u8 reserved_at_40[0x8]; 1916 u8 pd[0x18]; 1917 1918 u8 reserved_at_60[0x8]; 1919 u8 uar_page[0x18]; 1920 1921 u8 dbr_addr[0x40]; 1922 1923 u8 hw_counter[0x20]; 1924 1925 u8 sw_counter[0x20]; 1926 1927 u8 reserved_at_100[0xc]; 1928 u8 log_wq_stride[0x4]; 1929 u8 reserved_at_110[0x3]; 1930 u8 log_wq_pg_sz[0x5]; 1931 u8 reserved_at_118[0x3]; 1932 u8 log_wq_sz[0x5]; 1933 1934 u8 dbr_umem_valid[0x1]; 1935 u8 wq_umem_valid[0x1]; 1936 u8 reserved_at_122[0x1]; 1937 u8 log_hairpin_num_packets[0x5]; 1938 u8 reserved_at_128[0x3]; 1939 u8 log_hairpin_data_sz[0x5]; 1940 1941 u8 reserved_at_130[0x4]; 1942 u8 log_wqe_num_of_strides[0x4]; 1943 u8 two_byte_shift_en[0x1]; 1944 u8 reserved_at_139[0x4]; 1945 u8 log_wqe_stride_size[0x3]; 1946 1947 u8 reserved_at_140[0x80]; 1948 1949 u8 headers_mkey[0x20]; 1950 1951 u8 shampo_enable[0x1]; 1952 u8 reserved_at_1e1[0x4]; 1953 u8 log_reservation_size[0x3]; 1954 u8 reserved_at_1e8[0x5]; 1955 u8 log_max_num_of_packets_per_reservation[0x3]; 1956 u8 reserved_at_1f0[0x6]; 1957 u8 log_headers_entry_size[0x2]; 1958 u8 reserved_at_1f8[0x4]; 1959 u8 log_headers_buffer_entry_num[0x4]; 1960 1961 u8 reserved_at_200[0x400]; 1962 1963 struct mlx5_ifc_cmd_pas_bits pas[]; 1964 }; 1965 1966 struct mlx5_ifc_rq_num_bits { 1967 u8 reserved_at_0[0x8]; 1968 u8 rq_num[0x18]; 1969 }; 1970 1971 struct mlx5_ifc_mac_address_layout_bits { 1972 u8 reserved_at_0[0x10]; 1973 u8 mac_addr_47_32[0x10]; 1974 1975 u8 mac_addr_31_0[0x20]; 1976 }; 1977 1978 struct mlx5_ifc_vlan_layout_bits { 1979 u8 reserved_at_0[0x14]; 1980 u8 vlan[0x0c]; 1981 1982 u8 reserved_at_20[0x20]; 1983 }; 1984 1985 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1986 u8 reserved_at_0[0xa0]; 1987 1988 u8 min_time_between_cnps[0x20]; 1989 1990 u8 reserved_at_c0[0x12]; 1991 u8 cnp_dscp[0x6]; 1992 u8 reserved_at_d8[0x4]; 1993 u8 cnp_prio_mode[0x1]; 1994 u8 cnp_802p_prio[0x3]; 1995 1996 u8 reserved_at_e0[0x720]; 1997 }; 1998 1999 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2000 u8 reserved_at_0[0x60]; 2001 2002 u8 reserved_at_60[0x4]; 2003 u8 clamp_tgt_rate[0x1]; 2004 u8 reserved_at_65[0x3]; 2005 u8 clamp_tgt_rate_after_time_inc[0x1]; 2006 u8 reserved_at_69[0x17]; 2007 2008 u8 reserved_at_80[0x20]; 2009 2010 u8 rpg_time_reset[0x20]; 2011 2012 u8 rpg_byte_reset[0x20]; 2013 2014 u8 rpg_threshold[0x20]; 2015 2016 u8 rpg_max_rate[0x20]; 2017 2018 u8 rpg_ai_rate[0x20]; 2019 2020 u8 rpg_hai_rate[0x20]; 2021 2022 u8 rpg_gd[0x20]; 2023 2024 u8 rpg_min_dec_fac[0x20]; 2025 2026 u8 rpg_min_rate[0x20]; 2027 2028 u8 reserved_at_1c0[0xe0]; 2029 2030 u8 rate_to_set_on_first_cnp[0x20]; 2031 2032 u8 dce_tcp_g[0x20]; 2033 2034 u8 dce_tcp_rtt[0x20]; 2035 2036 u8 rate_reduce_monitor_period[0x20]; 2037 2038 u8 reserved_at_320[0x20]; 2039 2040 u8 initial_alpha_value[0x20]; 2041 2042 u8 reserved_at_360[0x4a0]; 2043 }; 2044 2045 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2046 u8 reserved_at_0[0x80]; 2047 2048 u8 rppp_max_rps[0x20]; 2049 2050 u8 rpg_time_reset[0x20]; 2051 2052 u8 rpg_byte_reset[0x20]; 2053 2054 u8 rpg_threshold[0x20]; 2055 2056 u8 rpg_max_rate[0x20]; 2057 2058 u8 rpg_ai_rate[0x20]; 2059 2060 u8 rpg_hai_rate[0x20]; 2061 2062 u8 rpg_gd[0x20]; 2063 2064 u8 rpg_min_dec_fac[0x20]; 2065 2066 u8 rpg_min_rate[0x20]; 2067 2068 u8 reserved_at_1c0[0x640]; 2069 }; 2070 2071 enum { 2072 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2073 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2074 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2075 }; 2076 2077 struct mlx5_ifc_resize_field_select_bits { 2078 u8 resize_field_select[0x20]; 2079 }; 2080 2081 struct mlx5_ifc_resource_dump_bits { 2082 u8 more_dump[0x1]; 2083 u8 inline_dump[0x1]; 2084 u8 reserved_at_2[0xa]; 2085 u8 seq_num[0x4]; 2086 u8 segment_type[0x10]; 2087 2088 u8 reserved_at_20[0x10]; 2089 u8 vhca_id[0x10]; 2090 2091 u8 index1[0x20]; 2092 2093 u8 index2[0x20]; 2094 2095 u8 num_of_obj1[0x10]; 2096 u8 num_of_obj2[0x10]; 2097 2098 u8 reserved_at_a0[0x20]; 2099 2100 u8 device_opaque[0x40]; 2101 2102 u8 mkey[0x20]; 2103 2104 u8 size[0x20]; 2105 2106 u8 address[0x40]; 2107 2108 u8 inline_data[52][0x20]; 2109 }; 2110 2111 struct mlx5_ifc_resource_dump_menu_record_bits { 2112 u8 reserved_at_0[0x4]; 2113 u8 num_of_obj2_supports_active[0x1]; 2114 u8 num_of_obj2_supports_all[0x1]; 2115 u8 must_have_num_of_obj2[0x1]; 2116 u8 support_num_of_obj2[0x1]; 2117 u8 num_of_obj1_supports_active[0x1]; 2118 u8 num_of_obj1_supports_all[0x1]; 2119 u8 must_have_num_of_obj1[0x1]; 2120 u8 support_num_of_obj1[0x1]; 2121 u8 must_have_index2[0x1]; 2122 u8 support_index2[0x1]; 2123 u8 must_have_index1[0x1]; 2124 u8 support_index1[0x1]; 2125 u8 segment_type[0x10]; 2126 2127 u8 segment_name[4][0x20]; 2128 2129 u8 index1_name[4][0x20]; 2130 2131 u8 index2_name[4][0x20]; 2132 }; 2133 2134 struct mlx5_ifc_resource_dump_segment_header_bits { 2135 u8 length_dw[0x10]; 2136 u8 segment_type[0x10]; 2137 }; 2138 2139 struct mlx5_ifc_resource_dump_command_segment_bits { 2140 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2141 2142 u8 segment_called[0x10]; 2143 u8 vhca_id[0x10]; 2144 2145 u8 index1[0x20]; 2146 2147 u8 index2[0x20]; 2148 2149 u8 num_of_obj1[0x10]; 2150 u8 num_of_obj2[0x10]; 2151 }; 2152 2153 struct mlx5_ifc_resource_dump_error_segment_bits { 2154 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2155 2156 u8 reserved_at_20[0x10]; 2157 u8 syndrome_id[0x10]; 2158 2159 u8 reserved_at_40[0x40]; 2160 2161 u8 error[8][0x20]; 2162 }; 2163 2164 struct mlx5_ifc_resource_dump_info_segment_bits { 2165 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2166 2167 u8 reserved_at_20[0x18]; 2168 u8 dump_version[0x8]; 2169 2170 u8 hw_version[0x20]; 2171 2172 u8 fw_version[0x20]; 2173 }; 2174 2175 struct mlx5_ifc_resource_dump_menu_segment_bits { 2176 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2177 2178 u8 reserved_at_20[0x10]; 2179 u8 num_of_records[0x10]; 2180 2181 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2182 }; 2183 2184 struct mlx5_ifc_resource_dump_resource_segment_bits { 2185 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2186 2187 u8 reserved_at_20[0x20]; 2188 2189 u8 index1[0x20]; 2190 2191 u8 index2[0x20]; 2192 2193 u8 payload[][0x20]; 2194 }; 2195 2196 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2197 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2198 }; 2199 2200 struct mlx5_ifc_menu_resource_dump_response_bits { 2201 struct mlx5_ifc_resource_dump_info_segment_bits info; 2202 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2203 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2204 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2205 }; 2206 2207 enum { 2208 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2209 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2210 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2211 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2212 }; 2213 2214 struct mlx5_ifc_modify_field_select_bits { 2215 u8 modify_field_select[0x20]; 2216 }; 2217 2218 struct mlx5_ifc_field_select_r_roce_np_bits { 2219 u8 field_select_r_roce_np[0x20]; 2220 }; 2221 2222 struct mlx5_ifc_field_select_r_roce_rp_bits { 2223 u8 field_select_r_roce_rp[0x20]; 2224 }; 2225 2226 enum { 2227 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2228 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2229 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2230 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2231 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2232 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2233 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2234 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2235 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2236 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2237 }; 2238 2239 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2240 u8 field_select_8021qaurp[0x20]; 2241 }; 2242 2243 struct mlx5_ifc_phys_layer_cntrs_bits { 2244 u8 time_since_last_clear_high[0x20]; 2245 2246 u8 time_since_last_clear_low[0x20]; 2247 2248 u8 symbol_errors_high[0x20]; 2249 2250 u8 symbol_errors_low[0x20]; 2251 2252 u8 sync_headers_errors_high[0x20]; 2253 2254 u8 sync_headers_errors_low[0x20]; 2255 2256 u8 edpl_bip_errors_lane0_high[0x20]; 2257 2258 u8 edpl_bip_errors_lane0_low[0x20]; 2259 2260 u8 edpl_bip_errors_lane1_high[0x20]; 2261 2262 u8 edpl_bip_errors_lane1_low[0x20]; 2263 2264 u8 edpl_bip_errors_lane2_high[0x20]; 2265 2266 u8 edpl_bip_errors_lane2_low[0x20]; 2267 2268 u8 edpl_bip_errors_lane3_high[0x20]; 2269 2270 u8 edpl_bip_errors_lane3_low[0x20]; 2271 2272 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2273 2274 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2275 2276 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2277 2278 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2279 2280 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2281 2282 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2283 2284 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2285 2286 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2287 2288 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2289 2290 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2291 2292 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2293 2294 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2295 2296 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2297 2298 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2299 2300 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2301 2302 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2303 2304 u8 rs_fec_corrected_blocks_high[0x20]; 2305 2306 u8 rs_fec_corrected_blocks_low[0x20]; 2307 2308 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2309 2310 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2311 2312 u8 rs_fec_no_errors_blocks_high[0x20]; 2313 2314 u8 rs_fec_no_errors_blocks_low[0x20]; 2315 2316 u8 rs_fec_single_error_blocks_high[0x20]; 2317 2318 u8 rs_fec_single_error_blocks_low[0x20]; 2319 2320 u8 rs_fec_corrected_symbols_total_high[0x20]; 2321 2322 u8 rs_fec_corrected_symbols_total_low[0x20]; 2323 2324 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2325 2326 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2327 2328 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2329 2330 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2331 2332 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2333 2334 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2335 2336 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2337 2338 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2339 2340 u8 link_down_events[0x20]; 2341 2342 u8 successful_recovery_events[0x20]; 2343 2344 u8 reserved_at_640[0x180]; 2345 }; 2346 2347 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2348 u8 time_since_last_clear_high[0x20]; 2349 2350 u8 time_since_last_clear_low[0x20]; 2351 2352 u8 phy_received_bits_high[0x20]; 2353 2354 u8 phy_received_bits_low[0x20]; 2355 2356 u8 phy_symbol_errors_high[0x20]; 2357 2358 u8 phy_symbol_errors_low[0x20]; 2359 2360 u8 phy_corrected_bits_high[0x20]; 2361 2362 u8 phy_corrected_bits_low[0x20]; 2363 2364 u8 phy_corrected_bits_lane0_high[0x20]; 2365 2366 u8 phy_corrected_bits_lane0_low[0x20]; 2367 2368 u8 phy_corrected_bits_lane1_high[0x20]; 2369 2370 u8 phy_corrected_bits_lane1_low[0x20]; 2371 2372 u8 phy_corrected_bits_lane2_high[0x20]; 2373 2374 u8 phy_corrected_bits_lane2_low[0x20]; 2375 2376 u8 phy_corrected_bits_lane3_high[0x20]; 2377 2378 u8 phy_corrected_bits_lane3_low[0x20]; 2379 2380 u8 reserved_at_200[0x5c0]; 2381 }; 2382 2383 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2384 u8 symbol_error_counter[0x10]; 2385 2386 u8 link_error_recovery_counter[0x8]; 2387 2388 u8 link_downed_counter[0x8]; 2389 2390 u8 port_rcv_errors[0x10]; 2391 2392 u8 port_rcv_remote_physical_errors[0x10]; 2393 2394 u8 port_rcv_switch_relay_errors[0x10]; 2395 2396 u8 port_xmit_discards[0x10]; 2397 2398 u8 port_xmit_constraint_errors[0x8]; 2399 2400 u8 port_rcv_constraint_errors[0x8]; 2401 2402 u8 reserved_at_70[0x8]; 2403 2404 u8 link_overrun_errors[0x8]; 2405 2406 u8 reserved_at_80[0x10]; 2407 2408 u8 vl_15_dropped[0x10]; 2409 2410 u8 reserved_at_a0[0x80]; 2411 2412 u8 port_xmit_wait[0x20]; 2413 }; 2414 2415 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2416 u8 transmit_queue_high[0x20]; 2417 2418 u8 transmit_queue_low[0x20]; 2419 2420 u8 no_buffer_discard_uc_high[0x20]; 2421 2422 u8 no_buffer_discard_uc_low[0x20]; 2423 2424 u8 reserved_at_80[0x740]; 2425 }; 2426 2427 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2428 u8 wred_discard_high[0x20]; 2429 2430 u8 wred_discard_low[0x20]; 2431 2432 u8 ecn_marked_tc_high[0x20]; 2433 2434 u8 ecn_marked_tc_low[0x20]; 2435 2436 u8 reserved_at_80[0x740]; 2437 }; 2438 2439 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2440 u8 rx_octets_high[0x20]; 2441 2442 u8 rx_octets_low[0x20]; 2443 2444 u8 reserved_at_40[0xc0]; 2445 2446 u8 rx_frames_high[0x20]; 2447 2448 u8 rx_frames_low[0x20]; 2449 2450 u8 tx_octets_high[0x20]; 2451 2452 u8 tx_octets_low[0x20]; 2453 2454 u8 reserved_at_180[0xc0]; 2455 2456 u8 tx_frames_high[0x20]; 2457 2458 u8 tx_frames_low[0x20]; 2459 2460 u8 rx_pause_high[0x20]; 2461 2462 u8 rx_pause_low[0x20]; 2463 2464 u8 rx_pause_duration_high[0x20]; 2465 2466 u8 rx_pause_duration_low[0x20]; 2467 2468 u8 tx_pause_high[0x20]; 2469 2470 u8 tx_pause_low[0x20]; 2471 2472 u8 tx_pause_duration_high[0x20]; 2473 2474 u8 tx_pause_duration_low[0x20]; 2475 2476 u8 rx_pause_transition_high[0x20]; 2477 2478 u8 rx_pause_transition_low[0x20]; 2479 2480 u8 rx_discards_high[0x20]; 2481 2482 u8 rx_discards_low[0x20]; 2483 2484 u8 device_stall_minor_watermark_cnt_high[0x20]; 2485 2486 u8 device_stall_minor_watermark_cnt_low[0x20]; 2487 2488 u8 device_stall_critical_watermark_cnt_high[0x20]; 2489 2490 u8 device_stall_critical_watermark_cnt_low[0x20]; 2491 2492 u8 reserved_at_480[0x340]; 2493 }; 2494 2495 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2496 u8 port_transmit_wait_high[0x20]; 2497 2498 u8 port_transmit_wait_low[0x20]; 2499 2500 u8 reserved_at_40[0x100]; 2501 2502 u8 rx_buffer_almost_full_high[0x20]; 2503 2504 u8 rx_buffer_almost_full_low[0x20]; 2505 2506 u8 rx_buffer_full_high[0x20]; 2507 2508 u8 rx_buffer_full_low[0x20]; 2509 2510 u8 rx_icrc_encapsulated_high[0x20]; 2511 2512 u8 rx_icrc_encapsulated_low[0x20]; 2513 2514 u8 reserved_at_200[0x5c0]; 2515 }; 2516 2517 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2518 u8 dot3stats_alignment_errors_high[0x20]; 2519 2520 u8 dot3stats_alignment_errors_low[0x20]; 2521 2522 u8 dot3stats_fcs_errors_high[0x20]; 2523 2524 u8 dot3stats_fcs_errors_low[0x20]; 2525 2526 u8 dot3stats_single_collision_frames_high[0x20]; 2527 2528 u8 dot3stats_single_collision_frames_low[0x20]; 2529 2530 u8 dot3stats_multiple_collision_frames_high[0x20]; 2531 2532 u8 dot3stats_multiple_collision_frames_low[0x20]; 2533 2534 u8 dot3stats_sqe_test_errors_high[0x20]; 2535 2536 u8 dot3stats_sqe_test_errors_low[0x20]; 2537 2538 u8 dot3stats_deferred_transmissions_high[0x20]; 2539 2540 u8 dot3stats_deferred_transmissions_low[0x20]; 2541 2542 u8 dot3stats_late_collisions_high[0x20]; 2543 2544 u8 dot3stats_late_collisions_low[0x20]; 2545 2546 u8 dot3stats_excessive_collisions_high[0x20]; 2547 2548 u8 dot3stats_excessive_collisions_low[0x20]; 2549 2550 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2551 2552 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2553 2554 u8 dot3stats_carrier_sense_errors_high[0x20]; 2555 2556 u8 dot3stats_carrier_sense_errors_low[0x20]; 2557 2558 u8 dot3stats_frame_too_longs_high[0x20]; 2559 2560 u8 dot3stats_frame_too_longs_low[0x20]; 2561 2562 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2563 2564 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2565 2566 u8 dot3stats_symbol_errors_high[0x20]; 2567 2568 u8 dot3stats_symbol_errors_low[0x20]; 2569 2570 u8 dot3control_in_unknown_opcodes_high[0x20]; 2571 2572 u8 dot3control_in_unknown_opcodes_low[0x20]; 2573 2574 u8 dot3in_pause_frames_high[0x20]; 2575 2576 u8 dot3in_pause_frames_low[0x20]; 2577 2578 u8 dot3out_pause_frames_high[0x20]; 2579 2580 u8 dot3out_pause_frames_low[0x20]; 2581 2582 u8 reserved_at_400[0x3c0]; 2583 }; 2584 2585 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2586 u8 ether_stats_drop_events_high[0x20]; 2587 2588 u8 ether_stats_drop_events_low[0x20]; 2589 2590 u8 ether_stats_octets_high[0x20]; 2591 2592 u8 ether_stats_octets_low[0x20]; 2593 2594 u8 ether_stats_pkts_high[0x20]; 2595 2596 u8 ether_stats_pkts_low[0x20]; 2597 2598 u8 ether_stats_broadcast_pkts_high[0x20]; 2599 2600 u8 ether_stats_broadcast_pkts_low[0x20]; 2601 2602 u8 ether_stats_multicast_pkts_high[0x20]; 2603 2604 u8 ether_stats_multicast_pkts_low[0x20]; 2605 2606 u8 ether_stats_crc_align_errors_high[0x20]; 2607 2608 u8 ether_stats_crc_align_errors_low[0x20]; 2609 2610 u8 ether_stats_undersize_pkts_high[0x20]; 2611 2612 u8 ether_stats_undersize_pkts_low[0x20]; 2613 2614 u8 ether_stats_oversize_pkts_high[0x20]; 2615 2616 u8 ether_stats_oversize_pkts_low[0x20]; 2617 2618 u8 ether_stats_fragments_high[0x20]; 2619 2620 u8 ether_stats_fragments_low[0x20]; 2621 2622 u8 ether_stats_jabbers_high[0x20]; 2623 2624 u8 ether_stats_jabbers_low[0x20]; 2625 2626 u8 ether_stats_collisions_high[0x20]; 2627 2628 u8 ether_stats_collisions_low[0x20]; 2629 2630 u8 ether_stats_pkts64octets_high[0x20]; 2631 2632 u8 ether_stats_pkts64octets_low[0x20]; 2633 2634 u8 ether_stats_pkts65to127octets_high[0x20]; 2635 2636 u8 ether_stats_pkts65to127octets_low[0x20]; 2637 2638 u8 ether_stats_pkts128to255octets_high[0x20]; 2639 2640 u8 ether_stats_pkts128to255octets_low[0x20]; 2641 2642 u8 ether_stats_pkts256to511octets_high[0x20]; 2643 2644 u8 ether_stats_pkts256to511octets_low[0x20]; 2645 2646 u8 ether_stats_pkts512to1023octets_high[0x20]; 2647 2648 u8 ether_stats_pkts512to1023octets_low[0x20]; 2649 2650 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2651 2652 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2653 2654 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2655 2656 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2657 2658 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2659 2660 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2661 2662 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2663 2664 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2665 2666 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2667 2668 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2669 2670 u8 reserved_at_540[0x280]; 2671 }; 2672 2673 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2674 u8 if_in_octets_high[0x20]; 2675 2676 u8 if_in_octets_low[0x20]; 2677 2678 u8 if_in_ucast_pkts_high[0x20]; 2679 2680 u8 if_in_ucast_pkts_low[0x20]; 2681 2682 u8 if_in_discards_high[0x20]; 2683 2684 u8 if_in_discards_low[0x20]; 2685 2686 u8 if_in_errors_high[0x20]; 2687 2688 u8 if_in_errors_low[0x20]; 2689 2690 u8 if_in_unknown_protos_high[0x20]; 2691 2692 u8 if_in_unknown_protos_low[0x20]; 2693 2694 u8 if_out_octets_high[0x20]; 2695 2696 u8 if_out_octets_low[0x20]; 2697 2698 u8 if_out_ucast_pkts_high[0x20]; 2699 2700 u8 if_out_ucast_pkts_low[0x20]; 2701 2702 u8 if_out_discards_high[0x20]; 2703 2704 u8 if_out_discards_low[0x20]; 2705 2706 u8 if_out_errors_high[0x20]; 2707 2708 u8 if_out_errors_low[0x20]; 2709 2710 u8 if_in_multicast_pkts_high[0x20]; 2711 2712 u8 if_in_multicast_pkts_low[0x20]; 2713 2714 u8 if_in_broadcast_pkts_high[0x20]; 2715 2716 u8 if_in_broadcast_pkts_low[0x20]; 2717 2718 u8 if_out_multicast_pkts_high[0x20]; 2719 2720 u8 if_out_multicast_pkts_low[0x20]; 2721 2722 u8 if_out_broadcast_pkts_high[0x20]; 2723 2724 u8 if_out_broadcast_pkts_low[0x20]; 2725 2726 u8 reserved_at_340[0x480]; 2727 }; 2728 2729 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2730 u8 a_frames_transmitted_ok_high[0x20]; 2731 2732 u8 a_frames_transmitted_ok_low[0x20]; 2733 2734 u8 a_frames_received_ok_high[0x20]; 2735 2736 u8 a_frames_received_ok_low[0x20]; 2737 2738 u8 a_frame_check_sequence_errors_high[0x20]; 2739 2740 u8 a_frame_check_sequence_errors_low[0x20]; 2741 2742 u8 a_alignment_errors_high[0x20]; 2743 2744 u8 a_alignment_errors_low[0x20]; 2745 2746 u8 a_octets_transmitted_ok_high[0x20]; 2747 2748 u8 a_octets_transmitted_ok_low[0x20]; 2749 2750 u8 a_octets_received_ok_high[0x20]; 2751 2752 u8 a_octets_received_ok_low[0x20]; 2753 2754 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2755 2756 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2757 2758 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2759 2760 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2761 2762 u8 a_multicast_frames_received_ok_high[0x20]; 2763 2764 u8 a_multicast_frames_received_ok_low[0x20]; 2765 2766 u8 a_broadcast_frames_received_ok_high[0x20]; 2767 2768 u8 a_broadcast_frames_received_ok_low[0x20]; 2769 2770 u8 a_in_range_length_errors_high[0x20]; 2771 2772 u8 a_in_range_length_errors_low[0x20]; 2773 2774 u8 a_out_of_range_length_field_high[0x20]; 2775 2776 u8 a_out_of_range_length_field_low[0x20]; 2777 2778 u8 a_frame_too_long_errors_high[0x20]; 2779 2780 u8 a_frame_too_long_errors_low[0x20]; 2781 2782 u8 a_symbol_error_during_carrier_high[0x20]; 2783 2784 u8 a_symbol_error_during_carrier_low[0x20]; 2785 2786 u8 a_mac_control_frames_transmitted_high[0x20]; 2787 2788 u8 a_mac_control_frames_transmitted_low[0x20]; 2789 2790 u8 a_mac_control_frames_received_high[0x20]; 2791 2792 u8 a_mac_control_frames_received_low[0x20]; 2793 2794 u8 a_unsupported_opcodes_received_high[0x20]; 2795 2796 u8 a_unsupported_opcodes_received_low[0x20]; 2797 2798 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2799 2800 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2801 2802 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2803 2804 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2805 2806 u8 reserved_at_4c0[0x300]; 2807 }; 2808 2809 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2810 u8 life_time_counter_high[0x20]; 2811 2812 u8 life_time_counter_low[0x20]; 2813 2814 u8 rx_errors[0x20]; 2815 2816 u8 tx_errors[0x20]; 2817 2818 u8 l0_to_recovery_eieos[0x20]; 2819 2820 u8 l0_to_recovery_ts[0x20]; 2821 2822 u8 l0_to_recovery_framing[0x20]; 2823 2824 u8 l0_to_recovery_retrain[0x20]; 2825 2826 u8 crc_error_dllp[0x20]; 2827 2828 u8 crc_error_tlp[0x20]; 2829 2830 u8 tx_overflow_buffer_pkt_high[0x20]; 2831 2832 u8 tx_overflow_buffer_pkt_low[0x20]; 2833 2834 u8 outbound_stalled_reads[0x20]; 2835 2836 u8 outbound_stalled_writes[0x20]; 2837 2838 u8 outbound_stalled_reads_events[0x20]; 2839 2840 u8 outbound_stalled_writes_events[0x20]; 2841 2842 u8 reserved_at_200[0x5c0]; 2843 }; 2844 2845 struct mlx5_ifc_cmd_inter_comp_event_bits { 2846 u8 command_completion_vector[0x20]; 2847 2848 u8 reserved_at_20[0xc0]; 2849 }; 2850 2851 struct mlx5_ifc_stall_vl_event_bits { 2852 u8 reserved_at_0[0x18]; 2853 u8 port_num[0x1]; 2854 u8 reserved_at_19[0x3]; 2855 u8 vl[0x4]; 2856 2857 u8 reserved_at_20[0xa0]; 2858 }; 2859 2860 struct mlx5_ifc_db_bf_congestion_event_bits { 2861 u8 event_subtype[0x8]; 2862 u8 reserved_at_8[0x8]; 2863 u8 congestion_level[0x8]; 2864 u8 reserved_at_18[0x8]; 2865 2866 u8 reserved_at_20[0xa0]; 2867 }; 2868 2869 struct mlx5_ifc_gpio_event_bits { 2870 u8 reserved_at_0[0x60]; 2871 2872 u8 gpio_event_hi[0x20]; 2873 2874 u8 gpio_event_lo[0x20]; 2875 2876 u8 reserved_at_a0[0x40]; 2877 }; 2878 2879 struct mlx5_ifc_port_state_change_event_bits { 2880 u8 reserved_at_0[0x40]; 2881 2882 u8 port_num[0x4]; 2883 u8 reserved_at_44[0x1c]; 2884 2885 u8 reserved_at_60[0x80]; 2886 }; 2887 2888 struct mlx5_ifc_dropped_packet_logged_bits { 2889 u8 reserved_at_0[0xe0]; 2890 }; 2891 2892 struct mlx5_ifc_default_timeout_bits { 2893 u8 to_multiplier[0x3]; 2894 u8 reserved_at_3[0x9]; 2895 u8 to_value[0x14]; 2896 }; 2897 2898 struct mlx5_ifc_dtor_reg_bits { 2899 u8 reserved_at_0[0x20]; 2900 2901 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2902 2903 u8 reserved_at_40[0x60]; 2904 2905 struct mlx5_ifc_default_timeout_bits health_poll_to; 2906 2907 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2908 2909 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2910 2911 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2912 2913 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2914 2915 struct mlx5_ifc_default_timeout_bits tear_down_to; 2916 2917 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2918 2919 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2920 2921 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2922 2923 u8 reserved_at_1c0[0x40]; 2924 }; 2925 2926 enum { 2927 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2928 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2929 }; 2930 2931 struct mlx5_ifc_cq_error_bits { 2932 u8 reserved_at_0[0x8]; 2933 u8 cqn[0x18]; 2934 2935 u8 reserved_at_20[0x20]; 2936 2937 u8 reserved_at_40[0x18]; 2938 u8 syndrome[0x8]; 2939 2940 u8 reserved_at_60[0x80]; 2941 }; 2942 2943 struct mlx5_ifc_rdma_page_fault_event_bits { 2944 u8 bytes_committed[0x20]; 2945 2946 u8 r_key[0x20]; 2947 2948 u8 reserved_at_40[0x10]; 2949 u8 packet_len[0x10]; 2950 2951 u8 rdma_op_len[0x20]; 2952 2953 u8 rdma_va[0x40]; 2954 2955 u8 reserved_at_c0[0x5]; 2956 u8 rdma[0x1]; 2957 u8 write[0x1]; 2958 u8 requestor[0x1]; 2959 u8 qp_number[0x18]; 2960 }; 2961 2962 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2963 u8 bytes_committed[0x20]; 2964 2965 u8 reserved_at_20[0x10]; 2966 u8 wqe_index[0x10]; 2967 2968 u8 reserved_at_40[0x10]; 2969 u8 len[0x10]; 2970 2971 u8 reserved_at_60[0x60]; 2972 2973 u8 reserved_at_c0[0x5]; 2974 u8 rdma[0x1]; 2975 u8 write_read[0x1]; 2976 u8 requestor[0x1]; 2977 u8 qpn[0x18]; 2978 }; 2979 2980 struct mlx5_ifc_qp_events_bits { 2981 u8 reserved_at_0[0xa0]; 2982 2983 u8 type[0x8]; 2984 u8 reserved_at_a8[0x18]; 2985 2986 u8 reserved_at_c0[0x8]; 2987 u8 qpn_rqn_sqn[0x18]; 2988 }; 2989 2990 struct mlx5_ifc_dct_events_bits { 2991 u8 reserved_at_0[0xc0]; 2992 2993 u8 reserved_at_c0[0x8]; 2994 u8 dct_number[0x18]; 2995 }; 2996 2997 struct mlx5_ifc_comp_event_bits { 2998 u8 reserved_at_0[0xc0]; 2999 3000 u8 reserved_at_c0[0x8]; 3001 u8 cq_number[0x18]; 3002 }; 3003 3004 enum { 3005 MLX5_QPC_STATE_RST = 0x0, 3006 MLX5_QPC_STATE_INIT = 0x1, 3007 MLX5_QPC_STATE_RTR = 0x2, 3008 MLX5_QPC_STATE_RTS = 0x3, 3009 MLX5_QPC_STATE_SQER = 0x4, 3010 MLX5_QPC_STATE_ERR = 0x6, 3011 MLX5_QPC_STATE_SQD = 0x7, 3012 MLX5_QPC_STATE_SUSPENDED = 0x9, 3013 }; 3014 3015 enum { 3016 MLX5_QPC_ST_RC = 0x0, 3017 MLX5_QPC_ST_UC = 0x1, 3018 MLX5_QPC_ST_UD = 0x2, 3019 MLX5_QPC_ST_XRC = 0x3, 3020 MLX5_QPC_ST_DCI = 0x5, 3021 MLX5_QPC_ST_QP0 = 0x7, 3022 MLX5_QPC_ST_QP1 = 0x8, 3023 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3024 MLX5_QPC_ST_REG_UMR = 0xc, 3025 }; 3026 3027 enum { 3028 MLX5_QPC_PM_STATE_ARMED = 0x0, 3029 MLX5_QPC_PM_STATE_REARM = 0x1, 3030 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3031 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3032 }; 3033 3034 enum { 3035 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3036 }; 3037 3038 enum { 3039 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3040 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3041 }; 3042 3043 enum { 3044 MLX5_QPC_MTU_256_BYTES = 0x1, 3045 MLX5_QPC_MTU_512_BYTES = 0x2, 3046 MLX5_QPC_MTU_1K_BYTES = 0x3, 3047 MLX5_QPC_MTU_2K_BYTES = 0x4, 3048 MLX5_QPC_MTU_4K_BYTES = 0x5, 3049 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3050 }; 3051 3052 enum { 3053 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3054 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3055 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3056 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3057 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3058 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3059 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3060 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3061 }; 3062 3063 enum { 3064 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3065 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3066 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3067 }; 3068 3069 enum { 3070 MLX5_QPC_CS_RES_DISABLE = 0x0, 3071 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3072 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3073 }; 3074 3075 enum { 3076 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3077 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3078 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3079 }; 3080 3081 struct mlx5_ifc_qpc_bits { 3082 u8 state[0x4]; 3083 u8 lag_tx_port_affinity[0x4]; 3084 u8 st[0x8]; 3085 u8 reserved_at_10[0x2]; 3086 u8 isolate_vl_tc[0x1]; 3087 u8 pm_state[0x2]; 3088 u8 reserved_at_15[0x1]; 3089 u8 req_e2e_credit_mode[0x2]; 3090 u8 offload_type[0x4]; 3091 u8 end_padding_mode[0x2]; 3092 u8 reserved_at_1e[0x2]; 3093 3094 u8 wq_signature[0x1]; 3095 u8 block_lb_mc[0x1]; 3096 u8 atomic_like_write_en[0x1]; 3097 u8 latency_sensitive[0x1]; 3098 u8 reserved_at_24[0x1]; 3099 u8 drain_sigerr[0x1]; 3100 u8 reserved_at_26[0x2]; 3101 u8 pd[0x18]; 3102 3103 u8 mtu[0x3]; 3104 u8 log_msg_max[0x5]; 3105 u8 reserved_at_48[0x1]; 3106 u8 log_rq_size[0x4]; 3107 u8 log_rq_stride[0x3]; 3108 u8 no_sq[0x1]; 3109 u8 log_sq_size[0x4]; 3110 u8 reserved_at_55[0x3]; 3111 u8 ts_format[0x2]; 3112 u8 reserved_at_5a[0x1]; 3113 u8 rlky[0x1]; 3114 u8 ulp_stateless_offload_mode[0x4]; 3115 3116 u8 counter_set_id[0x8]; 3117 u8 uar_page[0x18]; 3118 3119 u8 reserved_at_80[0x8]; 3120 u8 user_index[0x18]; 3121 3122 u8 reserved_at_a0[0x3]; 3123 u8 log_page_size[0x5]; 3124 u8 remote_qpn[0x18]; 3125 3126 struct mlx5_ifc_ads_bits primary_address_path; 3127 3128 struct mlx5_ifc_ads_bits secondary_address_path; 3129 3130 u8 log_ack_req_freq[0x4]; 3131 u8 reserved_at_384[0x4]; 3132 u8 log_sra_max[0x3]; 3133 u8 reserved_at_38b[0x2]; 3134 u8 retry_count[0x3]; 3135 u8 rnr_retry[0x3]; 3136 u8 reserved_at_393[0x1]; 3137 u8 fre[0x1]; 3138 u8 cur_rnr_retry[0x3]; 3139 u8 cur_retry_count[0x3]; 3140 u8 reserved_at_39b[0x5]; 3141 3142 u8 reserved_at_3a0[0x20]; 3143 3144 u8 reserved_at_3c0[0x8]; 3145 u8 next_send_psn[0x18]; 3146 3147 u8 reserved_at_3e0[0x3]; 3148 u8 log_num_dci_stream_channels[0x5]; 3149 u8 cqn_snd[0x18]; 3150 3151 u8 reserved_at_400[0x3]; 3152 u8 log_num_dci_errored_streams[0x5]; 3153 u8 deth_sqpn[0x18]; 3154 3155 u8 reserved_at_420[0x20]; 3156 3157 u8 reserved_at_440[0x8]; 3158 u8 last_acked_psn[0x18]; 3159 3160 u8 reserved_at_460[0x8]; 3161 u8 ssn[0x18]; 3162 3163 u8 reserved_at_480[0x8]; 3164 u8 log_rra_max[0x3]; 3165 u8 reserved_at_48b[0x1]; 3166 u8 atomic_mode[0x4]; 3167 u8 rre[0x1]; 3168 u8 rwe[0x1]; 3169 u8 rae[0x1]; 3170 u8 reserved_at_493[0x1]; 3171 u8 page_offset[0x6]; 3172 u8 reserved_at_49a[0x3]; 3173 u8 cd_slave_receive[0x1]; 3174 u8 cd_slave_send[0x1]; 3175 u8 cd_master[0x1]; 3176 3177 u8 reserved_at_4a0[0x3]; 3178 u8 min_rnr_nak[0x5]; 3179 u8 next_rcv_psn[0x18]; 3180 3181 u8 reserved_at_4c0[0x8]; 3182 u8 xrcd[0x18]; 3183 3184 u8 reserved_at_4e0[0x8]; 3185 u8 cqn_rcv[0x18]; 3186 3187 u8 dbr_addr[0x40]; 3188 3189 u8 q_key[0x20]; 3190 3191 u8 reserved_at_560[0x5]; 3192 u8 rq_type[0x3]; 3193 u8 srqn_rmpn_xrqn[0x18]; 3194 3195 u8 reserved_at_580[0x8]; 3196 u8 rmsn[0x18]; 3197 3198 u8 hw_sq_wqebb_counter[0x10]; 3199 u8 sw_sq_wqebb_counter[0x10]; 3200 3201 u8 hw_rq_counter[0x20]; 3202 3203 u8 sw_rq_counter[0x20]; 3204 3205 u8 reserved_at_600[0x20]; 3206 3207 u8 reserved_at_620[0xf]; 3208 u8 cgs[0x1]; 3209 u8 cs_req[0x8]; 3210 u8 cs_res[0x8]; 3211 3212 u8 dc_access_key[0x40]; 3213 3214 u8 reserved_at_680[0x3]; 3215 u8 dbr_umem_valid[0x1]; 3216 3217 u8 reserved_at_684[0xbc]; 3218 }; 3219 3220 struct mlx5_ifc_roce_addr_layout_bits { 3221 u8 source_l3_address[16][0x8]; 3222 3223 u8 reserved_at_80[0x3]; 3224 u8 vlan_valid[0x1]; 3225 u8 vlan_id[0xc]; 3226 u8 source_mac_47_32[0x10]; 3227 3228 u8 source_mac_31_0[0x20]; 3229 3230 u8 reserved_at_c0[0x14]; 3231 u8 roce_l3_type[0x4]; 3232 u8 roce_version[0x8]; 3233 3234 u8 reserved_at_e0[0x20]; 3235 }; 3236 3237 struct mlx5_ifc_shampo_cap_bits { 3238 u8 reserved_at_0[0x3]; 3239 u8 shampo_log_max_reservation_size[0x5]; 3240 u8 reserved_at_8[0x3]; 3241 u8 shampo_log_min_reservation_size[0x5]; 3242 u8 shampo_min_mss_size[0x10]; 3243 3244 u8 reserved_at_20[0x3]; 3245 u8 shampo_max_log_headers_entry_size[0x5]; 3246 u8 reserved_at_28[0x18]; 3247 3248 u8 reserved_at_40[0x7c0]; 3249 }; 3250 3251 union mlx5_ifc_hca_cap_union_bits { 3252 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3253 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3254 struct mlx5_ifc_odp_cap_bits odp_cap; 3255 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3256 struct mlx5_ifc_roce_cap_bits roce_cap; 3257 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3258 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3259 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3260 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3261 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3262 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3263 struct mlx5_ifc_qos_cap_bits qos_cap; 3264 struct mlx5_ifc_debug_cap_bits debug_cap; 3265 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3266 struct mlx5_ifc_tls_cap_bits tls_cap; 3267 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3268 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3269 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3270 u8 reserved_at_0[0x8000]; 3271 }; 3272 3273 enum { 3274 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3275 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3276 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3277 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3278 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3279 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3280 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3281 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3282 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3283 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3284 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3285 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3286 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3287 }; 3288 3289 enum { 3290 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3291 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3292 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3293 }; 3294 3295 struct mlx5_ifc_vlan_bits { 3296 u8 ethtype[0x10]; 3297 u8 prio[0x3]; 3298 u8 cfi[0x1]; 3299 u8 vid[0xc]; 3300 }; 3301 3302 struct mlx5_ifc_flow_context_bits { 3303 struct mlx5_ifc_vlan_bits push_vlan; 3304 3305 u8 group_id[0x20]; 3306 3307 u8 reserved_at_40[0x8]; 3308 u8 flow_tag[0x18]; 3309 3310 u8 reserved_at_60[0x10]; 3311 u8 action[0x10]; 3312 3313 u8 extended_destination[0x1]; 3314 u8 reserved_at_81[0x1]; 3315 u8 flow_source[0x2]; 3316 u8 reserved_at_84[0x4]; 3317 u8 destination_list_size[0x18]; 3318 3319 u8 reserved_at_a0[0x8]; 3320 u8 flow_counter_list_size[0x18]; 3321 3322 u8 packet_reformat_id[0x20]; 3323 3324 u8 modify_header_id[0x20]; 3325 3326 struct mlx5_ifc_vlan_bits push_vlan_2; 3327 3328 u8 ipsec_obj_id[0x20]; 3329 u8 reserved_at_140[0xc0]; 3330 3331 struct mlx5_ifc_fte_match_param_bits match_value; 3332 3333 u8 reserved_at_1200[0x600]; 3334 3335 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3336 }; 3337 3338 enum { 3339 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3340 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3341 }; 3342 3343 struct mlx5_ifc_xrc_srqc_bits { 3344 u8 state[0x4]; 3345 u8 log_xrc_srq_size[0x4]; 3346 u8 reserved_at_8[0x18]; 3347 3348 u8 wq_signature[0x1]; 3349 u8 cont_srq[0x1]; 3350 u8 reserved_at_22[0x1]; 3351 u8 rlky[0x1]; 3352 u8 basic_cyclic_rcv_wqe[0x1]; 3353 u8 log_rq_stride[0x3]; 3354 u8 xrcd[0x18]; 3355 3356 u8 page_offset[0x6]; 3357 u8 reserved_at_46[0x1]; 3358 u8 dbr_umem_valid[0x1]; 3359 u8 cqn[0x18]; 3360 3361 u8 reserved_at_60[0x20]; 3362 3363 u8 user_index_equal_xrc_srqn[0x1]; 3364 u8 reserved_at_81[0x1]; 3365 u8 log_page_size[0x6]; 3366 u8 user_index[0x18]; 3367 3368 u8 reserved_at_a0[0x20]; 3369 3370 u8 reserved_at_c0[0x8]; 3371 u8 pd[0x18]; 3372 3373 u8 lwm[0x10]; 3374 u8 wqe_cnt[0x10]; 3375 3376 u8 reserved_at_100[0x40]; 3377 3378 u8 db_record_addr_h[0x20]; 3379 3380 u8 db_record_addr_l[0x1e]; 3381 u8 reserved_at_17e[0x2]; 3382 3383 u8 reserved_at_180[0x80]; 3384 }; 3385 3386 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3387 u8 counter_error_queues[0x20]; 3388 3389 u8 total_error_queues[0x20]; 3390 3391 u8 send_queue_priority_update_flow[0x20]; 3392 3393 u8 reserved_at_60[0x20]; 3394 3395 u8 nic_receive_steering_discard[0x40]; 3396 3397 u8 receive_discard_vport_down[0x40]; 3398 3399 u8 transmit_discard_vport_down[0x40]; 3400 3401 u8 reserved_at_140[0xa0]; 3402 3403 u8 internal_rq_out_of_buffer[0x20]; 3404 3405 u8 reserved_at_200[0xe00]; 3406 }; 3407 3408 struct mlx5_ifc_traffic_counter_bits { 3409 u8 packets[0x40]; 3410 3411 u8 octets[0x40]; 3412 }; 3413 3414 struct mlx5_ifc_tisc_bits { 3415 u8 strict_lag_tx_port_affinity[0x1]; 3416 u8 tls_en[0x1]; 3417 u8 reserved_at_2[0x2]; 3418 u8 lag_tx_port_affinity[0x04]; 3419 3420 u8 reserved_at_8[0x4]; 3421 u8 prio[0x4]; 3422 u8 reserved_at_10[0x10]; 3423 3424 u8 reserved_at_20[0x100]; 3425 3426 u8 reserved_at_120[0x8]; 3427 u8 transport_domain[0x18]; 3428 3429 u8 reserved_at_140[0x8]; 3430 u8 underlay_qpn[0x18]; 3431 3432 u8 reserved_at_160[0x8]; 3433 u8 pd[0x18]; 3434 3435 u8 reserved_at_180[0x380]; 3436 }; 3437 3438 enum { 3439 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3440 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3441 }; 3442 3443 enum { 3444 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3445 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3446 }; 3447 3448 enum { 3449 MLX5_RX_HASH_FN_NONE = 0x0, 3450 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3451 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3452 }; 3453 3454 enum { 3455 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3456 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3457 }; 3458 3459 struct mlx5_ifc_tirc_bits { 3460 u8 reserved_at_0[0x20]; 3461 3462 u8 disp_type[0x4]; 3463 u8 tls_en[0x1]; 3464 u8 reserved_at_25[0x1b]; 3465 3466 u8 reserved_at_40[0x40]; 3467 3468 u8 reserved_at_80[0x4]; 3469 u8 lro_timeout_period_usecs[0x10]; 3470 u8 packet_merge_mask[0x4]; 3471 u8 lro_max_ip_payload_size[0x8]; 3472 3473 u8 reserved_at_a0[0x40]; 3474 3475 u8 reserved_at_e0[0x8]; 3476 u8 inline_rqn[0x18]; 3477 3478 u8 rx_hash_symmetric[0x1]; 3479 u8 reserved_at_101[0x1]; 3480 u8 tunneled_offload_en[0x1]; 3481 u8 reserved_at_103[0x5]; 3482 u8 indirect_table[0x18]; 3483 3484 u8 rx_hash_fn[0x4]; 3485 u8 reserved_at_124[0x2]; 3486 u8 self_lb_block[0x2]; 3487 u8 transport_domain[0x18]; 3488 3489 u8 rx_hash_toeplitz_key[10][0x20]; 3490 3491 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3492 3493 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3494 3495 u8 reserved_at_2c0[0x4c0]; 3496 }; 3497 3498 enum { 3499 MLX5_SRQC_STATE_GOOD = 0x0, 3500 MLX5_SRQC_STATE_ERROR = 0x1, 3501 }; 3502 3503 struct mlx5_ifc_srqc_bits { 3504 u8 state[0x4]; 3505 u8 log_srq_size[0x4]; 3506 u8 reserved_at_8[0x18]; 3507 3508 u8 wq_signature[0x1]; 3509 u8 cont_srq[0x1]; 3510 u8 reserved_at_22[0x1]; 3511 u8 rlky[0x1]; 3512 u8 reserved_at_24[0x1]; 3513 u8 log_rq_stride[0x3]; 3514 u8 xrcd[0x18]; 3515 3516 u8 page_offset[0x6]; 3517 u8 reserved_at_46[0x2]; 3518 u8 cqn[0x18]; 3519 3520 u8 reserved_at_60[0x20]; 3521 3522 u8 reserved_at_80[0x2]; 3523 u8 log_page_size[0x6]; 3524 u8 reserved_at_88[0x18]; 3525 3526 u8 reserved_at_a0[0x20]; 3527 3528 u8 reserved_at_c0[0x8]; 3529 u8 pd[0x18]; 3530 3531 u8 lwm[0x10]; 3532 u8 wqe_cnt[0x10]; 3533 3534 u8 reserved_at_100[0x40]; 3535 3536 u8 dbr_addr[0x40]; 3537 3538 u8 reserved_at_180[0x80]; 3539 }; 3540 3541 enum { 3542 MLX5_SQC_STATE_RST = 0x0, 3543 MLX5_SQC_STATE_RDY = 0x1, 3544 MLX5_SQC_STATE_ERR = 0x3, 3545 }; 3546 3547 struct mlx5_ifc_sqc_bits { 3548 u8 rlky[0x1]; 3549 u8 cd_master[0x1]; 3550 u8 fre[0x1]; 3551 u8 flush_in_error_en[0x1]; 3552 u8 allow_multi_pkt_send_wqe[0x1]; 3553 u8 min_wqe_inline_mode[0x3]; 3554 u8 state[0x4]; 3555 u8 reg_umr[0x1]; 3556 u8 allow_swp[0x1]; 3557 u8 hairpin[0x1]; 3558 u8 reserved_at_f[0xb]; 3559 u8 ts_format[0x2]; 3560 u8 reserved_at_1c[0x4]; 3561 3562 u8 reserved_at_20[0x8]; 3563 u8 user_index[0x18]; 3564 3565 u8 reserved_at_40[0x8]; 3566 u8 cqn[0x18]; 3567 3568 u8 reserved_at_60[0x8]; 3569 u8 hairpin_peer_rq[0x18]; 3570 3571 u8 reserved_at_80[0x10]; 3572 u8 hairpin_peer_vhca[0x10]; 3573 3574 u8 reserved_at_a0[0x20]; 3575 3576 u8 reserved_at_c0[0x8]; 3577 u8 ts_cqe_to_dest_cqn[0x18]; 3578 3579 u8 reserved_at_e0[0x10]; 3580 u8 packet_pacing_rate_limit_index[0x10]; 3581 u8 tis_lst_sz[0x10]; 3582 u8 qos_queue_group_id[0x10]; 3583 3584 u8 reserved_at_120[0x40]; 3585 3586 u8 reserved_at_160[0x8]; 3587 u8 tis_num_0[0x18]; 3588 3589 struct mlx5_ifc_wq_bits wq; 3590 }; 3591 3592 enum { 3593 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3594 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3595 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3596 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3597 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3598 }; 3599 3600 enum { 3601 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3602 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3603 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3604 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3605 }; 3606 3607 struct mlx5_ifc_scheduling_context_bits { 3608 u8 element_type[0x8]; 3609 u8 reserved_at_8[0x18]; 3610 3611 u8 element_attributes[0x20]; 3612 3613 u8 parent_element_id[0x20]; 3614 3615 u8 reserved_at_60[0x40]; 3616 3617 u8 bw_share[0x20]; 3618 3619 u8 max_average_bw[0x20]; 3620 3621 u8 reserved_at_e0[0x120]; 3622 }; 3623 3624 struct mlx5_ifc_rqtc_bits { 3625 u8 reserved_at_0[0xa0]; 3626 3627 u8 reserved_at_a0[0x5]; 3628 u8 list_q_type[0x3]; 3629 u8 reserved_at_a8[0x8]; 3630 u8 rqt_max_size[0x10]; 3631 3632 u8 rq_vhca_id_format[0x1]; 3633 u8 reserved_at_c1[0xf]; 3634 u8 rqt_actual_size[0x10]; 3635 3636 u8 reserved_at_e0[0x6a0]; 3637 3638 struct mlx5_ifc_rq_num_bits rq_num[]; 3639 }; 3640 3641 enum { 3642 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3643 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3644 }; 3645 3646 enum { 3647 MLX5_RQC_STATE_RST = 0x0, 3648 MLX5_RQC_STATE_RDY = 0x1, 3649 MLX5_RQC_STATE_ERR = 0x3, 3650 }; 3651 3652 enum { 3653 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3654 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3655 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3656 }; 3657 3658 enum { 3659 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3660 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3661 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3662 }; 3663 3664 struct mlx5_ifc_rqc_bits { 3665 u8 rlky[0x1]; 3666 u8 delay_drop_en[0x1]; 3667 u8 scatter_fcs[0x1]; 3668 u8 vsd[0x1]; 3669 u8 mem_rq_type[0x4]; 3670 u8 state[0x4]; 3671 u8 reserved_at_c[0x1]; 3672 u8 flush_in_error_en[0x1]; 3673 u8 hairpin[0x1]; 3674 u8 reserved_at_f[0xb]; 3675 u8 ts_format[0x2]; 3676 u8 reserved_at_1c[0x4]; 3677 3678 u8 reserved_at_20[0x8]; 3679 u8 user_index[0x18]; 3680 3681 u8 reserved_at_40[0x8]; 3682 u8 cqn[0x18]; 3683 3684 u8 counter_set_id[0x8]; 3685 u8 reserved_at_68[0x18]; 3686 3687 u8 reserved_at_80[0x8]; 3688 u8 rmpn[0x18]; 3689 3690 u8 reserved_at_a0[0x8]; 3691 u8 hairpin_peer_sq[0x18]; 3692 3693 u8 reserved_at_c0[0x10]; 3694 u8 hairpin_peer_vhca[0x10]; 3695 3696 u8 reserved_at_e0[0x46]; 3697 u8 shampo_no_match_alignment_granularity[0x2]; 3698 u8 reserved_at_128[0x6]; 3699 u8 shampo_match_criteria_type[0x2]; 3700 u8 reservation_timeout[0x10]; 3701 3702 u8 reserved_at_140[0x40]; 3703 3704 struct mlx5_ifc_wq_bits wq; 3705 }; 3706 3707 enum { 3708 MLX5_RMPC_STATE_RDY = 0x1, 3709 MLX5_RMPC_STATE_ERR = 0x3, 3710 }; 3711 3712 struct mlx5_ifc_rmpc_bits { 3713 u8 reserved_at_0[0x8]; 3714 u8 state[0x4]; 3715 u8 reserved_at_c[0x14]; 3716 3717 u8 basic_cyclic_rcv_wqe[0x1]; 3718 u8 reserved_at_21[0x1f]; 3719 3720 u8 reserved_at_40[0x140]; 3721 3722 struct mlx5_ifc_wq_bits wq; 3723 }; 3724 3725 enum { 3726 VHCA_ID_TYPE_HW = 0, 3727 VHCA_ID_TYPE_SW = 1, 3728 }; 3729 3730 struct mlx5_ifc_nic_vport_context_bits { 3731 u8 reserved_at_0[0x5]; 3732 u8 min_wqe_inline_mode[0x3]; 3733 u8 reserved_at_8[0x15]; 3734 u8 disable_mc_local_lb[0x1]; 3735 u8 disable_uc_local_lb[0x1]; 3736 u8 roce_en[0x1]; 3737 3738 u8 arm_change_event[0x1]; 3739 u8 reserved_at_21[0x1a]; 3740 u8 event_on_mtu[0x1]; 3741 u8 event_on_promisc_change[0x1]; 3742 u8 event_on_vlan_change[0x1]; 3743 u8 event_on_mc_address_change[0x1]; 3744 u8 event_on_uc_address_change[0x1]; 3745 3746 u8 vhca_id_type[0x1]; 3747 u8 reserved_at_41[0xb]; 3748 u8 affiliation_criteria[0x4]; 3749 u8 affiliated_vhca_id[0x10]; 3750 3751 u8 reserved_at_60[0xd0]; 3752 3753 u8 mtu[0x10]; 3754 3755 u8 system_image_guid[0x40]; 3756 u8 port_guid[0x40]; 3757 u8 node_guid[0x40]; 3758 3759 u8 reserved_at_200[0x140]; 3760 u8 qkey_violation_counter[0x10]; 3761 u8 reserved_at_350[0x430]; 3762 3763 u8 promisc_uc[0x1]; 3764 u8 promisc_mc[0x1]; 3765 u8 promisc_all[0x1]; 3766 u8 reserved_at_783[0x2]; 3767 u8 allowed_list_type[0x3]; 3768 u8 reserved_at_788[0xc]; 3769 u8 allowed_list_size[0xc]; 3770 3771 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3772 3773 u8 reserved_at_7e0[0x20]; 3774 3775 u8 current_uc_mac_address[][0x40]; 3776 }; 3777 3778 enum { 3779 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3780 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3781 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3782 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3783 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3784 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3785 }; 3786 3787 struct mlx5_ifc_mkc_bits { 3788 u8 reserved_at_0[0x1]; 3789 u8 free[0x1]; 3790 u8 reserved_at_2[0x1]; 3791 u8 access_mode_4_2[0x3]; 3792 u8 reserved_at_6[0x7]; 3793 u8 relaxed_ordering_write[0x1]; 3794 u8 reserved_at_e[0x1]; 3795 u8 small_fence_on_rdma_read_response[0x1]; 3796 u8 umr_en[0x1]; 3797 u8 a[0x1]; 3798 u8 rw[0x1]; 3799 u8 rr[0x1]; 3800 u8 lw[0x1]; 3801 u8 lr[0x1]; 3802 u8 access_mode_1_0[0x2]; 3803 u8 reserved_at_18[0x8]; 3804 3805 u8 qpn[0x18]; 3806 u8 mkey_7_0[0x8]; 3807 3808 u8 reserved_at_40[0x20]; 3809 3810 u8 length64[0x1]; 3811 u8 bsf_en[0x1]; 3812 u8 sync_umr[0x1]; 3813 u8 reserved_at_63[0x2]; 3814 u8 expected_sigerr_count[0x1]; 3815 u8 reserved_at_66[0x1]; 3816 u8 en_rinval[0x1]; 3817 u8 pd[0x18]; 3818 3819 u8 start_addr[0x40]; 3820 3821 u8 len[0x40]; 3822 3823 u8 bsf_octword_size[0x20]; 3824 3825 u8 reserved_at_120[0x80]; 3826 3827 u8 translations_octword_size[0x20]; 3828 3829 u8 reserved_at_1c0[0x19]; 3830 u8 relaxed_ordering_read[0x1]; 3831 u8 reserved_at_1d9[0x1]; 3832 u8 log_page_size[0x5]; 3833 3834 u8 reserved_at_1e0[0x20]; 3835 }; 3836 3837 struct mlx5_ifc_pkey_bits { 3838 u8 reserved_at_0[0x10]; 3839 u8 pkey[0x10]; 3840 }; 3841 3842 struct mlx5_ifc_array128_auto_bits { 3843 u8 array128_auto[16][0x8]; 3844 }; 3845 3846 struct mlx5_ifc_hca_vport_context_bits { 3847 u8 field_select[0x20]; 3848 3849 u8 reserved_at_20[0xe0]; 3850 3851 u8 sm_virt_aware[0x1]; 3852 u8 has_smi[0x1]; 3853 u8 has_raw[0x1]; 3854 u8 grh_required[0x1]; 3855 u8 reserved_at_104[0xc]; 3856 u8 port_physical_state[0x4]; 3857 u8 vport_state_policy[0x4]; 3858 u8 port_state[0x4]; 3859 u8 vport_state[0x4]; 3860 3861 u8 reserved_at_120[0x20]; 3862 3863 u8 system_image_guid[0x40]; 3864 3865 u8 port_guid[0x40]; 3866 3867 u8 node_guid[0x40]; 3868 3869 u8 cap_mask1[0x20]; 3870 3871 u8 cap_mask1_field_select[0x20]; 3872 3873 u8 cap_mask2[0x20]; 3874 3875 u8 cap_mask2_field_select[0x20]; 3876 3877 u8 reserved_at_280[0x80]; 3878 3879 u8 lid[0x10]; 3880 u8 reserved_at_310[0x4]; 3881 u8 init_type_reply[0x4]; 3882 u8 lmc[0x3]; 3883 u8 subnet_timeout[0x5]; 3884 3885 u8 sm_lid[0x10]; 3886 u8 sm_sl[0x4]; 3887 u8 reserved_at_334[0xc]; 3888 3889 u8 qkey_violation_counter[0x10]; 3890 u8 pkey_violation_counter[0x10]; 3891 3892 u8 reserved_at_360[0xca0]; 3893 }; 3894 3895 struct mlx5_ifc_esw_vport_context_bits { 3896 u8 fdb_to_vport_reg_c[0x1]; 3897 u8 reserved_at_1[0x2]; 3898 u8 vport_svlan_strip[0x1]; 3899 u8 vport_cvlan_strip[0x1]; 3900 u8 vport_svlan_insert[0x1]; 3901 u8 vport_cvlan_insert[0x2]; 3902 u8 fdb_to_vport_reg_c_id[0x8]; 3903 u8 reserved_at_10[0x10]; 3904 3905 u8 reserved_at_20[0x20]; 3906 3907 u8 svlan_cfi[0x1]; 3908 u8 svlan_pcp[0x3]; 3909 u8 svlan_id[0xc]; 3910 u8 cvlan_cfi[0x1]; 3911 u8 cvlan_pcp[0x3]; 3912 u8 cvlan_id[0xc]; 3913 3914 u8 reserved_at_60[0x720]; 3915 3916 u8 sw_steering_vport_icm_address_rx[0x40]; 3917 3918 u8 sw_steering_vport_icm_address_tx[0x40]; 3919 }; 3920 3921 enum { 3922 MLX5_EQC_STATUS_OK = 0x0, 3923 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3924 }; 3925 3926 enum { 3927 MLX5_EQC_ST_ARMED = 0x9, 3928 MLX5_EQC_ST_FIRED = 0xa, 3929 }; 3930 3931 struct mlx5_ifc_eqc_bits { 3932 u8 status[0x4]; 3933 u8 reserved_at_4[0x9]; 3934 u8 ec[0x1]; 3935 u8 oi[0x1]; 3936 u8 reserved_at_f[0x5]; 3937 u8 st[0x4]; 3938 u8 reserved_at_18[0x8]; 3939 3940 u8 reserved_at_20[0x20]; 3941 3942 u8 reserved_at_40[0x14]; 3943 u8 page_offset[0x6]; 3944 u8 reserved_at_5a[0x6]; 3945 3946 u8 reserved_at_60[0x3]; 3947 u8 log_eq_size[0x5]; 3948 u8 uar_page[0x18]; 3949 3950 u8 reserved_at_80[0x20]; 3951 3952 u8 reserved_at_a0[0x14]; 3953 u8 intr[0xc]; 3954 3955 u8 reserved_at_c0[0x3]; 3956 u8 log_page_size[0x5]; 3957 u8 reserved_at_c8[0x18]; 3958 3959 u8 reserved_at_e0[0x60]; 3960 3961 u8 reserved_at_140[0x8]; 3962 u8 consumer_counter[0x18]; 3963 3964 u8 reserved_at_160[0x8]; 3965 u8 producer_counter[0x18]; 3966 3967 u8 reserved_at_180[0x80]; 3968 }; 3969 3970 enum { 3971 MLX5_DCTC_STATE_ACTIVE = 0x0, 3972 MLX5_DCTC_STATE_DRAINING = 0x1, 3973 MLX5_DCTC_STATE_DRAINED = 0x2, 3974 }; 3975 3976 enum { 3977 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3978 MLX5_DCTC_CS_RES_NA = 0x1, 3979 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3980 }; 3981 3982 enum { 3983 MLX5_DCTC_MTU_256_BYTES = 0x1, 3984 MLX5_DCTC_MTU_512_BYTES = 0x2, 3985 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3986 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3987 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3988 }; 3989 3990 struct mlx5_ifc_dctc_bits { 3991 u8 reserved_at_0[0x4]; 3992 u8 state[0x4]; 3993 u8 reserved_at_8[0x18]; 3994 3995 u8 reserved_at_20[0x8]; 3996 u8 user_index[0x18]; 3997 3998 u8 reserved_at_40[0x8]; 3999 u8 cqn[0x18]; 4000 4001 u8 counter_set_id[0x8]; 4002 u8 atomic_mode[0x4]; 4003 u8 rre[0x1]; 4004 u8 rwe[0x1]; 4005 u8 rae[0x1]; 4006 u8 atomic_like_write_en[0x1]; 4007 u8 latency_sensitive[0x1]; 4008 u8 rlky[0x1]; 4009 u8 free_ar[0x1]; 4010 u8 reserved_at_73[0xd]; 4011 4012 u8 reserved_at_80[0x8]; 4013 u8 cs_res[0x8]; 4014 u8 reserved_at_90[0x3]; 4015 u8 min_rnr_nak[0x5]; 4016 u8 reserved_at_98[0x8]; 4017 4018 u8 reserved_at_a0[0x8]; 4019 u8 srqn_xrqn[0x18]; 4020 4021 u8 reserved_at_c0[0x8]; 4022 u8 pd[0x18]; 4023 4024 u8 tclass[0x8]; 4025 u8 reserved_at_e8[0x4]; 4026 u8 flow_label[0x14]; 4027 4028 u8 dc_access_key[0x40]; 4029 4030 u8 reserved_at_140[0x5]; 4031 u8 mtu[0x3]; 4032 u8 port[0x8]; 4033 u8 pkey_index[0x10]; 4034 4035 u8 reserved_at_160[0x8]; 4036 u8 my_addr_index[0x8]; 4037 u8 reserved_at_170[0x8]; 4038 u8 hop_limit[0x8]; 4039 4040 u8 dc_access_key_violation_count[0x20]; 4041 4042 u8 reserved_at_1a0[0x14]; 4043 u8 dei_cfi[0x1]; 4044 u8 eth_prio[0x3]; 4045 u8 ecn[0x2]; 4046 u8 dscp[0x6]; 4047 4048 u8 reserved_at_1c0[0x20]; 4049 u8 ece[0x20]; 4050 }; 4051 4052 enum { 4053 MLX5_CQC_STATUS_OK = 0x0, 4054 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4055 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4056 }; 4057 4058 enum { 4059 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4060 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4061 }; 4062 4063 enum { 4064 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4065 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4066 MLX5_CQC_ST_FIRED = 0xa, 4067 }; 4068 4069 enum { 4070 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4071 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4072 MLX5_CQ_PERIOD_NUM_MODES 4073 }; 4074 4075 struct mlx5_ifc_cqc_bits { 4076 u8 status[0x4]; 4077 u8 reserved_at_4[0x2]; 4078 u8 dbr_umem_valid[0x1]; 4079 u8 apu_cq[0x1]; 4080 u8 cqe_sz[0x3]; 4081 u8 cc[0x1]; 4082 u8 reserved_at_c[0x1]; 4083 u8 scqe_break_moderation_en[0x1]; 4084 u8 oi[0x1]; 4085 u8 cq_period_mode[0x2]; 4086 u8 cqe_comp_en[0x1]; 4087 u8 mini_cqe_res_format[0x2]; 4088 u8 st[0x4]; 4089 u8 reserved_at_18[0x8]; 4090 4091 u8 reserved_at_20[0x20]; 4092 4093 u8 reserved_at_40[0x14]; 4094 u8 page_offset[0x6]; 4095 u8 reserved_at_5a[0x6]; 4096 4097 u8 reserved_at_60[0x3]; 4098 u8 log_cq_size[0x5]; 4099 u8 uar_page[0x18]; 4100 4101 u8 reserved_at_80[0x4]; 4102 u8 cq_period[0xc]; 4103 u8 cq_max_count[0x10]; 4104 4105 u8 c_eqn_or_apu_element[0x20]; 4106 4107 u8 reserved_at_c0[0x3]; 4108 u8 log_page_size[0x5]; 4109 u8 reserved_at_c8[0x18]; 4110 4111 u8 reserved_at_e0[0x20]; 4112 4113 u8 reserved_at_100[0x8]; 4114 u8 last_notified_index[0x18]; 4115 4116 u8 reserved_at_120[0x8]; 4117 u8 last_solicit_index[0x18]; 4118 4119 u8 reserved_at_140[0x8]; 4120 u8 consumer_counter[0x18]; 4121 4122 u8 reserved_at_160[0x8]; 4123 u8 producer_counter[0x18]; 4124 4125 u8 reserved_at_180[0x40]; 4126 4127 u8 dbr_addr[0x40]; 4128 }; 4129 4130 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4131 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4132 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4133 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4134 u8 reserved_at_0[0x800]; 4135 }; 4136 4137 struct mlx5_ifc_query_adapter_param_block_bits { 4138 u8 reserved_at_0[0xc0]; 4139 4140 u8 reserved_at_c0[0x8]; 4141 u8 ieee_vendor_id[0x18]; 4142 4143 u8 reserved_at_e0[0x10]; 4144 u8 vsd_vendor_id[0x10]; 4145 4146 u8 vsd[208][0x8]; 4147 4148 u8 vsd_contd_psid[16][0x8]; 4149 }; 4150 4151 enum { 4152 MLX5_XRQC_STATE_GOOD = 0x0, 4153 MLX5_XRQC_STATE_ERROR = 0x1, 4154 }; 4155 4156 enum { 4157 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4158 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4159 }; 4160 4161 enum { 4162 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4163 }; 4164 4165 struct mlx5_ifc_tag_matching_topology_context_bits { 4166 u8 log_matching_list_sz[0x4]; 4167 u8 reserved_at_4[0xc]; 4168 u8 append_next_index[0x10]; 4169 4170 u8 sw_phase_cnt[0x10]; 4171 u8 hw_phase_cnt[0x10]; 4172 4173 u8 reserved_at_40[0x40]; 4174 }; 4175 4176 struct mlx5_ifc_xrqc_bits { 4177 u8 state[0x4]; 4178 u8 rlkey[0x1]; 4179 u8 reserved_at_5[0xf]; 4180 u8 topology[0x4]; 4181 u8 reserved_at_18[0x4]; 4182 u8 offload[0x4]; 4183 4184 u8 reserved_at_20[0x8]; 4185 u8 user_index[0x18]; 4186 4187 u8 reserved_at_40[0x8]; 4188 u8 cqn[0x18]; 4189 4190 u8 reserved_at_60[0xa0]; 4191 4192 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4193 4194 u8 reserved_at_180[0x280]; 4195 4196 struct mlx5_ifc_wq_bits wq; 4197 }; 4198 4199 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4200 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4201 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4202 u8 reserved_at_0[0x20]; 4203 }; 4204 4205 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4206 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4207 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4208 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4209 u8 reserved_at_0[0x20]; 4210 }; 4211 4212 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4213 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4214 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4215 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4216 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4217 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4218 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4219 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4220 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4221 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4222 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4223 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4224 u8 reserved_at_0[0x7c0]; 4225 }; 4226 4227 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4228 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4229 u8 reserved_at_0[0x7c0]; 4230 }; 4231 4232 union mlx5_ifc_event_auto_bits { 4233 struct mlx5_ifc_comp_event_bits comp_event; 4234 struct mlx5_ifc_dct_events_bits dct_events; 4235 struct mlx5_ifc_qp_events_bits qp_events; 4236 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4237 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4238 struct mlx5_ifc_cq_error_bits cq_error; 4239 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4240 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4241 struct mlx5_ifc_gpio_event_bits gpio_event; 4242 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4243 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4244 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4245 u8 reserved_at_0[0xe0]; 4246 }; 4247 4248 struct mlx5_ifc_health_buffer_bits { 4249 u8 reserved_at_0[0x100]; 4250 4251 u8 assert_existptr[0x20]; 4252 4253 u8 assert_callra[0x20]; 4254 4255 u8 reserved_at_140[0x20]; 4256 4257 u8 time[0x20]; 4258 4259 u8 fw_version[0x20]; 4260 4261 u8 hw_id[0x20]; 4262 4263 u8 rfr[0x1]; 4264 u8 reserved_at_1c1[0x3]; 4265 u8 valid[0x1]; 4266 u8 severity[0x3]; 4267 u8 reserved_at_1c8[0x18]; 4268 4269 u8 irisc_index[0x8]; 4270 u8 synd[0x8]; 4271 u8 ext_synd[0x10]; 4272 }; 4273 4274 struct mlx5_ifc_register_loopback_control_bits { 4275 u8 no_lb[0x1]; 4276 u8 reserved_at_1[0x7]; 4277 u8 port[0x8]; 4278 u8 reserved_at_10[0x10]; 4279 4280 u8 reserved_at_20[0x60]; 4281 }; 4282 4283 struct mlx5_ifc_vport_tc_element_bits { 4284 u8 traffic_class[0x4]; 4285 u8 reserved_at_4[0xc]; 4286 u8 vport_number[0x10]; 4287 }; 4288 4289 struct mlx5_ifc_vport_element_bits { 4290 u8 reserved_at_0[0x10]; 4291 u8 vport_number[0x10]; 4292 }; 4293 4294 enum { 4295 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4296 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4297 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4298 }; 4299 4300 struct mlx5_ifc_tsar_element_bits { 4301 u8 reserved_at_0[0x8]; 4302 u8 tsar_type[0x8]; 4303 u8 reserved_at_10[0x10]; 4304 }; 4305 4306 enum { 4307 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4308 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4309 }; 4310 4311 struct mlx5_ifc_teardown_hca_out_bits { 4312 u8 status[0x8]; 4313 u8 reserved_at_8[0x18]; 4314 4315 u8 syndrome[0x20]; 4316 4317 u8 reserved_at_40[0x3f]; 4318 4319 u8 state[0x1]; 4320 }; 4321 4322 enum { 4323 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4324 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4325 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4326 }; 4327 4328 struct mlx5_ifc_teardown_hca_in_bits { 4329 u8 opcode[0x10]; 4330 u8 reserved_at_10[0x10]; 4331 4332 u8 reserved_at_20[0x10]; 4333 u8 op_mod[0x10]; 4334 4335 u8 reserved_at_40[0x10]; 4336 u8 profile[0x10]; 4337 4338 u8 reserved_at_60[0x20]; 4339 }; 4340 4341 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4342 u8 status[0x8]; 4343 u8 reserved_at_8[0x18]; 4344 4345 u8 syndrome[0x20]; 4346 4347 u8 reserved_at_40[0x40]; 4348 }; 4349 4350 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4351 u8 opcode[0x10]; 4352 u8 uid[0x10]; 4353 4354 u8 reserved_at_20[0x10]; 4355 u8 op_mod[0x10]; 4356 4357 u8 reserved_at_40[0x8]; 4358 u8 qpn[0x18]; 4359 4360 u8 reserved_at_60[0x20]; 4361 4362 u8 opt_param_mask[0x20]; 4363 4364 u8 reserved_at_a0[0x20]; 4365 4366 struct mlx5_ifc_qpc_bits qpc; 4367 4368 u8 reserved_at_800[0x80]; 4369 }; 4370 4371 struct mlx5_ifc_sqd2rts_qp_out_bits { 4372 u8 status[0x8]; 4373 u8 reserved_at_8[0x18]; 4374 4375 u8 syndrome[0x20]; 4376 4377 u8 reserved_at_40[0x40]; 4378 }; 4379 4380 struct mlx5_ifc_sqd2rts_qp_in_bits { 4381 u8 opcode[0x10]; 4382 u8 uid[0x10]; 4383 4384 u8 reserved_at_20[0x10]; 4385 u8 op_mod[0x10]; 4386 4387 u8 reserved_at_40[0x8]; 4388 u8 qpn[0x18]; 4389 4390 u8 reserved_at_60[0x20]; 4391 4392 u8 opt_param_mask[0x20]; 4393 4394 u8 reserved_at_a0[0x20]; 4395 4396 struct mlx5_ifc_qpc_bits qpc; 4397 4398 u8 reserved_at_800[0x80]; 4399 }; 4400 4401 struct mlx5_ifc_set_roce_address_out_bits { 4402 u8 status[0x8]; 4403 u8 reserved_at_8[0x18]; 4404 4405 u8 syndrome[0x20]; 4406 4407 u8 reserved_at_40[0x40]; 4408 }; 4409 4410 struct mlx5_ifc_set_roce_address_in_bits { 4411 u8 opcode[0x10]; 4412 u8 reserved_at_10[0x10]; 4413 4414 u8 reserved_at_20[0x10]; 4415 u8 op_mod[0x10]; 4416 4417 u8 roce_address_index[0x10]; 4418 u8 reserved_at_50[0xc]; 4419 u8 vhca_port_num[0x4]; 4420 4421 u8 reserved_at_60[0x20]; 4422 4423 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4424 }; 4425 4426 struct mlx5_ifc_set_mad_demux_out_bits { 4427 u8 status[0x8]; 4428 u8 reserved_at_8[0x18]; 4429 4430 u8 syndrome[0x20]; 4431 4432 u8 reserved_at_40[0x40]; 4433 }; 4434 4435 enum { 4436 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4437 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4438 }; 4439 4440 struct mlx5_ifc_set_mad_demux_in_bits { 4441 u8 opcode[0x10]; 4442 u8 reserved_at_10[0x10]; 4443 4444 u8 reserved_at_20[0x10]; 4445 u8 op_mod[0x10]; 4446 4447 u8 reserved_at_40[0x20]; 4448 4449 u8 reserved_at_60[0x6]; 4450 u8 demux_mode[0x2]; 4451 u8 reserved_at_68[0x18]; 4452 }; 4453 4454 struct mlx5_ifc_set_l2_table_entry_out_bits { 4455 u8 status[0x8]; 4456 u8 reserved_at_8[0x18]; 4457 4458 u8 syndrome[0x20]; 4459 4460 u8 reserved_at_40[0x40]; 4461 }; 4462 4463 struct mlx5_ifc_set_l2_table_entry_in_bits { 4464 u8 opcode[0x10]; 4465 u8 reserved_at_10[0x10]; 4466 4467 u8 reserved_at_20[0x10]; 4468 u8 op_mod[0x10]; 4469 4470 u8 reserved_at_40[0x60]; 4471 4472 u8 reserved_at_a0[0x8]; 4473 u8 table_index[0x18]; 4474 4475 u8 reserved_at_c0[0x20]; 4476 4477 u8 reserved_at_e0[0x13]; 4478 u8 vlan_valid[0x1]; 4479 u8 vlan[0xc]; 4480 4481 struct mlx5_ifc_mac_address_layout_bits mac_address; 4482 4483 u8 reserved_at_140[0xc0]; 4484 }; 4485 4486 struct mlx5_ifc_set_issi_out_bits { 4487 u8 status[0x8]; 4488 u8 reserved_at_8[0x18]; 4489 4490 u8 syndrome[0x20]; 4491 4492 u8 reserved_at_40[0x40]; 4493 }; 4494 4495 struct mlx5_ifc_set_issi_in_bits { 4496 u8 opcode[0x10]; 4497 u8 reserved_at_10[0x10]; 4498 4499 u8 reserved_at_20[0x10]; 4500 u8 op_mod[0x10]; 4501 4502 u8 reserved_at_40[0x10]; 4503 u8 current_issi[0x10]; 4504 4505 u8 reserved_at_60[0x20]; 4506 }; 4507 4508 struct mlx5_ifc_set_hca_cap_out_bits { 4509 u8 status[0x8]; 4510 u8 reserved_at_8[0x18]; 4511 4512 u8 syndrome[0x20]; 4513 4514 u8 reserved_at_40[0x40]; 4515 }; 4516 4517 struct mlx5_ifc_set_hca_cap_in_bits { 4518 u8 opcode[0x10]; 4519 u8 reserved_at_10[0x10]; 4520 4521 u8 reserved_at_20[0x10]; 4522 u8 op_mod[0x10]; 4523 4524 u8 other_function[0x1]; 4525 u8 reserved_at_41[0xf]; 4526 u8 function_id[0x10]; 4527 4528 u8 reserved_at_60[0x20]; 4529 4530 union mlx5_ifc_hca_cap_union_bits capability; 4531 }; 4532 4533 enum { 4534 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4535 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4536 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4537 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4538 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4539 }; 4540 4541 struct mlx5_ifc_set_fte_out_bits { 4542 u8 status[0x8]; 4543 u8 reserved_at_8[0x18]; 4544 4545 u8 syndrome[0x20]; 4546 4547 u8 reserved_at_40[0x40]; 4548 }; 4549 4550 struct mlx5_ifc_set_fte_in_bits { 4551 u8 opcode[0x10]; 4552 u8 reserved_at_10[0x10]; 4553 4554 u8 reserved_at_20[0x10]; 4555 u8 op_mod[0x10]; 4556 4557 u8 other_vport[0x1]; 4558 u8 reserved_at_41[0xf]; 4559 u8 vport_number[0x10]; 4560 4561 u8 reserved_at_60[0x20]; 4562 4563 u8 table_type[0x8]; 4564 u8 reserved_at_88[0x18]; 4565 4566 u8 reserved_at_a0[0x8]; 4567 u8 table_id[0x18]; 4568 4569 u8 ignore_flow_level[0x1]; 4570 u8 reserved_at_c1[0x17]; 4571 u8 modify_enable_mask[0x8]; 4572 4573 u8 reserved_at_e0[0x20]; 4574 4575 u8 flow_index[0x20]; 4576 4577 u8 reserved_at_120[0xe0]; 4578 4579 struct mlx5_ifc_flow_context_bits flow_context; 4580 }; 4581 4582 struct mlx5_ifc_rts2rts_qp_out_bits { 4583 u8 status[0x8]; 4584 u8 reserved_at_8[0x18]; 4585 4586 u8 syndrome[0x20]; 4587 4588 u8 reserved_at_40[0x20]; 4589 u8 ece[0x20]; 4590 }; 4591 4592 struct mlx5_ifc_rts2rts_qp_in_bits { 4593 u8 opcode[0x10]; 4594 u8 uid[0x10]; 4595 4596 u8 reserved_at_20[0x10]; 4597 u8 op_mod[0x10]; 4598 4599 u8 reserved_at_40[0x8]; 4600 u8 qpn[0x18]; 4601 4602 u8 reserved_at_60[0x20]; 4603 4604 u8 opt_param_mask[0x20]; 4605 4606 u8 ece[0x20]; 4607 4608 struct mlx5_ifc_qpc_bits qpc; 4609 4610 u8 reserved_at_800[0x80]; 4611 }; 4612 4613 struct mlx5_ifc_rtr2rts_qp_out_bits { 4614 u8 status[0x8]; 4615 u8 reserved_at_8[0x18]; 4616 4617 u8 syndrome[0x20]; 4618 4619 u8 reserved_at_40[0x20]; 4620 u8 ece[0x20]; 4621 }; 4622 4623 struct mlx5_ifc_rtr2rts_qp_in_bits { 4624 u8 opcode[0x10]; 4625 u8 uid[0x10]; 4626 4627 u8 reserved_at_20[0x10]; 4628 u8 op_mod[0x10]; 4629 4630 u8 reserved_at_40[0x8]; 4631 u8 qpn[0x18]; 4632 4633 u8 reserved_at_60[0x20]; 4634 4635 u8 opt_param_mask[0x20]; 4636 4637 u8 ece[0x20]; 4638 4639 struct mlx5_ifc_qpc_bits qpc; 4640 4641 u8 reserved_at_800[0x80]; 4642 }; 4643 4644 struct mlx5_ifc_rst2init_qp_out_bits { 4645 u8 status[0x8]; 4646 u8 reserved_at_8[0x18]; 4647 4648 u8 syndrome[0x20]; 4649 4650 u8 reserved_at_40[0x20]; 4651 u8 ece[0x20]; 4652 }; 4653 4654 struct mlx5_ifc_rst2init_qp_in_bits { 4655 u8 opcode[0x10]; 4656 u8 uid[0x10]; 4657 4658 u8 reserved_at_20[0x10]; 4659 u8 op_mod[0x10]; 4660 4661 u8 reserved_at_40[0x8]; 4662 u8 qpn[0x18]; 4663 4664 u8 reserved_at_60[0x20]; 4665 4666 u8 opt_param_mask[0x20]; 4667 4668 u8 ece[0x20]; 4669 4670 struct mlx5_ifc_qpc_bits qpc; 4671 4672 u8 reserved_at_800[0x80]; 4673 }; 4674 4675 struct mlx5_ifc_query_xrq_out_bits { 4676 u8 status[0x8]; 4677 u8 reserved_at_8[0x18]; 4678 4679 u8 syndrome[0x20]; 4680 4681 u8 reserved_at_40[0x40]; 4682 4683 struct mlx5_ifc_xrqc_bits xrq_context; 4684 }; 4685 4686 struct mlx5_ifc_query_xrq_in_bits { 4687 u8 opcode[0x10]; 4688 u8 reserved_at_10[0x10]; 4689 4690 u8 reserved_at_20[0x10]; 4691 u8 op_mod[0x10]; 4692 4693 u8 reserved_at_40[0x8]; 4694 u8 xrqn[0x18]; 4695 4696 u8 reserved_at_60[0x20]; 4697 }; 4698 4699 struct mlx5_ifc_query_xrc_srq_out_bits { 4700 u8 status[0x8]; 4701 u8 reserved_at_8[0x18]; 4702 4703 u8 syndrome[0x20]; 4704 4705 u8 reserved_at_40[0x40]; 4706 4707 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4708 4709 u8 reserved_at_280[0x600]; 4710 4711 u8 pas[][0x40]; 4712 }; 4713 4714 struct mlx5_ifc_query_xrc_srq_in_bits { 4715 u8 opcode[0x10]; 4716 u8 reserved_at_10[0x10]; 4717 4718 u8 reserved_at_20[0x10]; 4719 u8 op_mod[0x10]; 4720 4721 u8 reserved_at_40[0x8]; 4722 u8 xrc_srqn[0x18]; 4723 4724 u8 reserved_at_60[0x20]; 4725 }; 4726 4727 enum { 4728 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4729 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4730 }; 4731 4732 struct mlx5_ifc_query_vport_state_out_bits { 4733 u8 status[0x8]; 4734 u8 reserved_at_8[0x18]; 4735 4736 u8 syndrome[0x20]; 4737 4738 u8 reserved_at_40[0x20]; 4739 4740 u8 reserved_at_60[0x18]; 4741 u8 admin_state[0x4]; 4742 u8 state[0x4]; 4743 }; 4744 4745 enum { 4746 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4747 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4748 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4749 }; 4750 4751 struct mlx5_ifc_arm_monitor_counter_in_bits { 4752 u8 opcode[0x10]; 4753 u8 uid[0x10]; 4754 4755 u8 reserved_at_20[0x10]; 4756 u8 op_mod[0x10]; 4757 4758 u8 reserved_at_40[0x20]; 4759 4760 u8 reserved_at_60[0x20]; 4761 }; 4762 4763 struct mlx5_ifc_arm_monitor_counter_out_bits { 4764 u8 status[0x8]; 4765 u8 reserved_at_8[0x18]; 4766 4767 u8 syndrome[0x20]; 4768 4769 u8 reserved_at_40[0x40]; 4770 }; 4771 4772 enum { 4773 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4774 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4775 }; 4776 4777 enum mlx5_monitor_counter_ppcnt { 4778 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4779 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4780 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4781 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4782 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4783 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4784 }; 4785 4786 enum { 4787 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4788 }; 4789 4790 struct mlx5_ifc_monitor_counter_output_bits { 4791 u8 reserved_at_0[0x4]; 4792 u8 type[0x4]; 4793 u8 reserved_at_8[0x8]; 4794 u8 counter[0x10]; 4795 4796 u8 counter_group_id[0x20]; 4797 }; 4798 4799 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4800 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4801 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4802 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4803 4804 struct mlx5_ifc_set_monitor_counter_in_bits { 4805 u8 opcode[0x10]; 4806 u8 uid[0x10]; 4807 4808 u8 reserved_at_20[0x10]; 4809 u8 op_mod[0x10]; 4810 4811 u8 reserved_at_40[0x10]; 4812 u8 num_of_counters[0x10]; 4813 4814 u8 reserved_at_60[0x20]; 4815 4816 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4817 }; 4818 4819 struct mlx5_ifc_set_monitor_counter_out_bits { 4820 u8 status[0x8]; 4821 u8 reserved_at_8[0x18]; 4822 4823 u8 syndrome[0x20]; 4824 4825 u8 reserved_at_40[0x40]; 4826 }; 4827 4828 struct mlx5_ifc_query_vport_state_in_bits { 4829 u8 opcode[0x10]; 4830 u8 reserved_at_10[0x10]; 4831 4832 u8 reserved_at_20[0x10]; 4833 u8 op_mod[0x10]; 4834 4835 u8 other_vport[0x1]; 4836 u8 reserved_at_41[0xf]; 4837 u8 vport_number[0x10]; 4838 4839 u8 reserved_at_60[0x20]; 4840 }; 4841 4842 struct mlx5_ifc_query_vnic_env_out_bits { 4843 u8 status[0x8]; 4844 u8 reserved_at_8[0x18]; 4845 4846 u8 syndrome[0x20]; 4847 4848 u8 reserved_at_40[0x40]; 4849 4850 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4851 }; 4852 4853 enum { 4854 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4855 }; 4856 4857 struct mlx5_ifc_query_vnic_env_in_bits { 4858 u8 opcode[0x10]; 4859 u8 reserved_at_10[0x10]; 4860 4861 u8 reserved_at_20[0x10]; 4862 u8 op_mod[0x10]; 4863 4864 u8 other_vport[0x1]; 4865 u8 reserved_at_41[0xf]; 4866 u8 vport_number[0x10]; 4867 4868 u8 reserved_at_60[0x20]; 4869 }; 4870 4871 struct mlx5_ifc_query_vport_counter_out_bits { 4872 u8 status[0x8]; 4873 u8 reserved_at_8[0x18]; 4874 4875 u8 syndrome[0x20]; 4876 4877 u8 reserved_at_40[0x40]; 4878 4879 struct mlx5_ifc_traffic_counter_bits received_errors; 4880 4881 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4882 4883 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4884 4885 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4886 4887 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4888 4889 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4890 4891 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4892 4893 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4894 4895 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4896 4897 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4898 4899 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4900 4901 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4902 4903 u8 reserved_at_680[0xa00]; 4904 }; 4905 4906 enum { 4907 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4908 }; 4909 4910 struct mlx5_ifc_query_vport_counter_in_bits { 4911 u8 opcode[0x10]; 4912 u8 reserved_at_10[0x10]; 4913 4914 u8 reserved_at_20[0x10]; 4915 u8 op_mod[0x10]; 4916 4917 u8 other_vport[0x1]; 4918 u8 reserved_at_41[0xb]; 4919 u8 port_num[0x4]; 4920 u8 vport_number[0x10]; 4921 4922 u8 reserved_at_60[0x60]; 4923 4924 u8 clear[0x1]; 4925 u8 reserved_at_c1[0x1f]; 4926 4927 u8 reserved_at_e0[0x20]; 4928 }; 4929 4930 struct mlx5_ifc_query_tis_out_bits { 4931 u8 status[0x8]; 4932 u8 reserved_at_8[0x18]; 4933 4934 u8 syndrome[0x20]; 4935 4936 u8 reserved_at_40[0x40]; 4937 4938 struct mlx5_ifc_tisc_bits tis_context; 4939 }; 4940 4941 struct mlx5_ifc_query_tis_in_bits { 4942 u8 opcode[0x10]; 4943 u8 reserved_at_10[0x10]; 4944 4945 u8 reserved_at_20[0x10]; 4946 u8 op_mod[0x10]; 4947 4948 u8 reserved_at_40[0x8]; 4949 u8 tisn[0x18]; 4950 4951 u8 reserved_at_60[0x20]; 4952 }; 4953 4954 struct mlx5_ifc_query_tir_out_bits { 4955 u8 status[0x8]; 4956 u8 reserved_at_8[0x18]; 4957 4958 u8 syndrome[0x20]; 4959 4960 u8 reserved_at_40[0xc0]; 4961 4962 struct mlx5_ifc_tirc_bits tir_context; 4963 }; 4964 4965 struct mlx5_ifc_query_tir_in_bits { 4966 u8 opcode[0x10]; 4967 u8 reserved_at_10[0x10]; 4968 4969 u8 reserved_at_20[0x10]; 4970 u8 op_mod[0x10]; 4971 4972 u8 reserved_at_40[0x8]; 4973 u8 tirn[0x18]; 4974 4975 u8 reserved_at_60[0x20]; 4976 }; 4977 4978 struct mlx5_ifc_query_srq_out_bits { 4979 u8 status[0x8]; 4980 u8 reserved_at_8[0x18]; 4981 4982 u8 syndrome[0x20]; 4983 4984 u8 reserved_at_40[0x40]; 4985 4986 struct mlx5_ifc_srqc_bits srq_context_entry; 4987 4988 u8 reserved_at_280[0x600]; 4989 4990 u8 pas[][0x40]; 4991 }; 4992 4993 struct mlx5_ifc_query_srq_in_bits { 4994 u8 opcode[0x10]; 4995 u8 reserved_at_10[0x10]; 4996 4997 u8 reserved_at_20[0x10]; 4998 u8 op_mod[0x10]; 4999 5000 u8 reserved_at_40[0x8]; 5001 u8 srqn[0x18]; 5002 5003 u8 reserved_at_60[0x20]; 5004 }; 5005 5006 struct mlx5_ifc_query_sq_out_bits { 5007 u8 status[0x8]; 5008 u8 reserved_at_8[0x18]; 5009 5010 u8 syndrome[0x20]; 5011 5012 u8 reserved_at_40[0xc0]; 5013 5014 struct mlx5_ifc_sqc_bits sq_context; 5015 }; 5016 5017 struct mlx5_ifc_query_sq_in_bits { 5018 u8 opcode[0x10]; 5019 u8 reserved_at_10[0x10]; 5020 5021 u8 reserved_at_20[0x10]; 5022 u8 op_mod[0x10]; 5023 5024 u8 reserved_at_40[0x8]; 5025 u8 sqn[0x18]; 5026 5027 u8 reserved_at_60[0x20]; 5028 }; 5029 5030 struct mlx5_ifc_query_special_contexts_out_bits { 5031 u8 status[0x8]; 5032 u8 reserved_at_8[0x18]; 5033 5034 u8 syndrome[0x20]; 5035 5036 u8 dump_fill_mkey[0x20]; 5037 5038 u8 resd_lkey[0x20]; 5039 5040 u8 null_mkey[0x20]; 5041 5042 u8 reserved_at_a0[0x60]; 5043 }; 5044 5045 struct mlx5_ifc_query_special_contexts_in_bits { 5046 u8 opcode[0x10]; 5047 u8 reserved_at_10[0x10]; 5048 5049 u8 reserved_at_20[0x10]; 5050 u8 op_mod[0x10]; 5051 5052 u8 reserved_at_40[0x40]; 5053 }; 5054 5055 struct mlx5_ifc_query_scheduling_element_out_bits { 5056 u8 opcode[0x10]; 5057 u8 reserved_at_10[0x10]; 5058 5059 u8 reserved_at_20[0x10]; 5060 u8 op_mod[0x10]; 5061 5062 u8 reserved_at_40[0xc0]; 5063 5064 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5065 5066 u8 reserved_at_300[0x100]; 5067 }; 5068 5069 enum { 5070 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5071 SCHEDULING_HIERARCHY_NIC = 0x3, 5072 }; 5073 5074 struct mlx5_ifc_query_scheduling_element_in_bits { 5075 u8 opcode[0x10]; 5076 u8 reserved_at_10[0x10]; 5077 5078 u8 reserved_at_20[0x10]; 5079 u8 op_mod[0x10]; 5080 5081 u8 scheduling_hierarchy[0x8]; 5082 u8 reserved_at_48[0x18]; 5083 5084 u8 scheduling_element_id[0x20]; 5085 5086 u8 reserved_at_80[0x180]; 5087 }; 5088 5089 struct mlx5_ifc_query_rqt_out_bits { 5090 u8 status[0x8]; 5091 u8 reserved_at_8[0x18]; 5092 5093 u8 syndrome[0x20]; 5094 5095 u8 reserved_at_40[0xc0]; 5096 5097 struct mlx5_ifc_rqtc_bits rqt_context; 5098 }; 5099 5100 struct mlx5_ifc_query_rqt_in_bits { 5101 u8 opcode[0x10]; 5102 u8 reserved_at_10[0x10]; 5103 5104 u8 reserved_at_20[0x10]; 5105 u8 op_mod[0x10]; 5106 5107 u8 reserved_at_40[0x8]; 5108 u8 rqtn[0x18]; 5109 5110 u8 reserved_at_60[0x20]; 5111 }; 5112 5113 struct mlx5_ifc_query_rq_out_bits { 5114 u8 status[0x8]; 5115 u8 reserved_at_8[0x18]; 5116 5117 u8 syndrome[0x20]; 5118 5119 u8 reserved_at_40[0xc0]; 5120 5121 struct mlx5_ifc_rqc_bits rq_context; 5122 }; 5123 5124 struct mlx5_ifc_query_rq_in_bits { 5125 u8 opcode[0x10]; 5126 u8 reserved_at_10[0x10]; 5127 5128 u8 reserved_at_20[0x10]; 5129 u8 op_mod[0x10]; 5130 5131 u8 reserved_at_40[0x8]; 5132 u8 rqn[0x18]; 5133 5134 u8 reserved_at_60[0x20]; 5135 }; 5136 5137 struct mlx5_ifc_query_roce_address_out_bits { 5138 u8 status[0x8]; 5139 u8 reserved_at_8[0x18]; 5140 5141 u8 syndrome[0x20]; 5142 5143 u8 reserved_at_40[0x40]; 5144 5145 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5146 }; 5147 5148 struct mlx5_ifc_query_roce_address_in_bits { 5149 u8 opcode[0x10]; 5150 u8 reserved_at_10[0x10]; 5151 5152 u8 reserved_at_20[0x10]; 5153 u8 op_mod[0x10]; 5154 5155 u8 roce_address_index[0x10]; 5156 u8 reserved_at_50[0xc]; 5157 u8 vhca_port_num[0x4]; 5158 5159 u8 reserved_at_60[0x20]; 5160 }; 5161 5162 struct mlx5_ifc_query_rmp_out_bits { 5163 u8 status[0x8]; 5164 u8 reserved_at_8[0x18]; 5165 5166 u8 syndrome[0x20]; 5167 5168 u8 reserved_at_40[0xc0]; 5169 5170 struct mlx5_ifc_rmpc_bits rmp_context; 5171 }; 5172 5173 struct mlx5_ifc_query_rmp_in_bits { 5174 u8 opcode[0x10]; 5175 u8 reserved_at_10[0x10]; 5176 5177 u8 reserved_at_20[0x10]; 5178 u8 op_mod[0x10]; 5179 5180 u8 reserved_at_40[0x8]; 5181 u8 rmpn[0x18]; 5182 5183 u8 reserved_at_60[0x20]; 5184 }; 5185 5186 struct mlx5_ifc_query_qp_out_bits { 5187 u8 status[0x8]; 5188 u8 reserved_at_8[0x18]; 5189 5190 u8 syndrome[0x20]; 5191 5192 u8 reserved_at_40[0x40]; 5193 5194 u8 opt_param_mask[0x20]; 5195 5196 u8 ece[0x20]; 5197 5198 struct mlx5_ifc_qpc_bits qpc; 5199 5200 u8 reserved_at_800[0x80]; 5201 5202 u8 pas[][0x40]; 5203 }; 5204 5205 struct mlx5_ifc_query_qp_in_bits { 5206 u8 opcode[0x10]; 5207 u8 reserved_at_10[0x10]; 5208 5209 u8 reserved_at_20[0x10]; 5210 u8 op_mod[0x10]; 5211 5212 u8 reserved_at_40[0x8]; 5213 u8 qpn[0x18]; 5214 5215 u8 reserved_at_60[0x20]; 5216 }; 5217 5218 struct mlx5_ifc_query_q_counter_out_bits { 5219 u8 status[0x8]; 5220 u8 reserved_at_8[0x18]; 5221 5222 u8 syndrome[0x20]; 5223 5224 u8 reserved_at_40[0x40]; 5225 5226 u8 rx_write_requests[0x20]; 5227 5228 u8 reserved_at_a0[0x20]; 5229 5230 u8 rx_read_requests[0x20]; 5231 5232 u8 reserved_at_e0[0x20]; 5233 5234 u8 rx_atomic_requests[0x20]; 5235 5236 u8 reserved_at_120[0x20]; 5237 5238 u8 rx_dct_connect[0x20]; 5239 5240 u8 reserved_at_160[0x20]; 5241 5242 u8 out_of_buffer[0x20]; 5243 5244 u8 reserved_at_1a0[0x20]; 5245 5246 u8 out_of_sequence[0x20]; 5247 5248 u8 reserved_at_1e0[0x20]; 5249 5250 u8 duplicate_request[0x20]; 5251 5252 u8 reserved_at_220[0x20]; 5253 5254 u8 rnr_nak_retry_err[0x20]; 5255 5256 u8 reserved_at_260[0x20]; 5257 5258 u8 packet_seq_err[0x20]; 5259 5260 u8 reserved_at_2a0[0x20]; 5261 5262 u8 implied_nak_seq_err[0x20]; 5263 5264 u8 reserved_at_2e0[0x20]; 5265 5266 u8 local_ack_timeout_err[0x20]; 5267 5268 u8 reserved_at_320[0xa0]; 5269 5270 u8 resp_local_length_error[0x20]; 5271 5272 u8 req_local_length_error[0x20]; 5273 5274 u8 resp_local_qp_error[0x20]; 5275 5276 u8 local_operation_error[0x20]; 5277 5278 u8 resp_local_protection[0x20]; 5279 5280 u8 req_local_protection[0x20]; 5281 5282 u8 resp_cqe_error[0x20]; 5283 5284 u8 req_cqe_error[0x20]; 5285 5286 u8 req_mw_binding[0x20]; 5287 5288 u8 req_bad_response[0x20]; 5289 5290 u8 req_remote_invalid_request[0x20]; 5291 5292 u8 resp_remote_invalid_request[0x20]; 5293 5294 u8 req_remote_access_errors[0x20]; 5295 5296 u8 resp_remote_access_errors[0x20]; 5297 5298 u8 req_remote_operation_errors[0x20]; 5299 5300 u8 req_transport_retries_exceeded[0x20]; 5301 5302 u8 cq_overflow[0x20]; 5303 5304 u8 resp_cqe_flush_error[0x20]; 5305 5306 u8 req_cqe_flush_error[0x20]; 5307 5308 u8 reserved_at_620[0x20]; 5309 5310 u8 roce_adp_retrans[0x20]; 5311 5312 u8 roce_adp_retrans_to[0x20]; 5313 5314 u8 roce_slow_restart[0x20]; 5315 5316 u8 roce_slow_restart_cnps[0x20]; 5317 5318 u8 roce_slow_restart_trans[0x20]; 5319 5320 u8 reserved_at_6e0[0x120]; 5321 }; 5322 5323 struct mlx5_ifc_query_q_counter_in_bits { 5324 u8 opcode[0x10]; 5325 u8 reserved_at_10[0x10]; 5326 5327 u8 reserved_at_20[0x10]; 5328 u8 op_mod[0x10]; 5329 5330 u8 reserved_at_40[0x80]; 5331 5332 u8 clear[0x1]; 5333 u8 reserved_at_c1[0x1f]; 5334 5335 u8 reserved_at_e0[0x18]; 5336 u8 counter_set_id[0x8]; 5337 }; 5338 5339 struct mlx5_ifc_query_pages_out_bits { 5340 u8 status[0x8]; 5341 u8 reserved_at_8[0x18]; 5342 5343 u8 syndrome[0x20]; 5344 5345 u8 embedded_cpu_function[0x1]; 5346 u8 reserved_at_41[0xf]; 5347 u8 function_id[0x10]; 5348 5349 u8 num_pages[0x20]; 5350 }; 5351 5352 enum { 5353 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5354 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5355 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5356 }; 5357 5358 struct mlx5_ifc_query_pages_in_bits { 5359 u8 opcode[0x10]; 5360 u8 reserved_at_10[0x10]; 5361 5362 u8 reserved_at_20[0x10]; 5363 u8 op_mod[0x10]; 5364 5365 u8 embedded_cpu_function[0x1]; 5366 u8 reserved_at_41[0xf]; 5367 u8 function_id[0x10]; 5368 5369 u8 reserved_at_60[0x20]; 5370 }; 5371 5372 struct mlx5_ifc_query_nic_vport_context_out_bits { 5373 u8 status[0x8]; 5374 u8 reserved_at_8[0x18]; 5375 5376 u8 syndrome[0x20]; 5377 5378 u8 reserved_at_40[0x40]; 5379 5380 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5381 }; 5382 5383 struct mlx5_ifc_query_nic_vport_context_in_bits { 5384 u8 opcode[0x10]; 5385 u8 reserved_at_10[0x10]; 5386 5387 u8 reserved_at_20[0x10]; 5388 u8 op_mod[0x10]; 5389 5390 u8 other_vport[0x1]; 5391 u8 reserved_at_41[0xf]; 5392 u8 vport_number[0x10]; 5393 5394 u8 reserved_at_60[0x5]; 5395 u8 allowed_list_type[0x3]; 5396 u8 reserved_at_68[0x18]; 5397 }; 5398 5399 struct mlx5_ifc_query_mkey_out_bits { 5400 u8 status[0x8]; 5401 u8 reserved_at_8[0x18]; 5402 5403 u8 syndrome[0x20]; 5404 5405 u8 reserved_at_40[0x40]; 5406 5407 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5408 5409 u8 reserved_at_280[0x600]; 5410 5411 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5412 5413 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5414 }; 5415 5416 struct mlx5_ifc_query_mkey_in_bits { 5417 u8 opcode[0x10]; 5418 u8 reserved_at_10[0x10]; 5419 5420 u8 reserved_at_20[0x10]; 5421 u8 op_mod[0x10]; 5422 5423 u8 reserved_at_40[0x8]; 5424 u8 mkey_index[0x18]; 5425 5426 u8 pg_access[0x1]; 5427 u8 reserved_at_61[0x1f]; 5428 }; 5429 5430 struct mlx5_ifc_query_mad_demux_out_bits { 5431 u8 status[0x8]; 5432 u8 reserved_at_8[0x18]; 5433 5434 u8 syndrome[0x20]; 5435 5436 u8 reserved_at_40[0x40]; 5437 5438 u8 mad_dumux_parameters_block[0x20]; 5439 }; 5440 5441 struct mlx5_ifc_query_mad_demux_in_bits { 5442 u8 opcode[0x10]; 5443 u8 reserved_at_10[0x10]; 5444 5445 u8 reserved_at_20[0x10]; 5446 u8 op_mod[0x10]; 5447 5448 u8 reserved_at_40[0x40]; 5449 }; 5450 5451 struct mlx5_ifc_query_l2_table_entry_out_bits { 5452 u8 status[0x8]; 5453 u8 reserved_at_8[0x18]; 5454 5455 u8 syndrome[0x20]; 5456 5457 u8 reserved_at_40[0xa0]; 5458 5459 u8 reserved_at_e0[0x13]; 5460 u8 vlan_valid[0x1]; 5461 u8 vlan[0xc]; 5462 5463 struct mlx5_ifc_mac_address_layout_bits mac_address; 5464 5465 u8 reserved_at_140[0xc0]; 5466 }; 5467 5468 struct mlx5_ifc_query_l2_table_entry_in_bits { 5469 u8 opcode[0x10]; 5470 u8 reserved_at_10[0x10]; 5471 5472 u8 reserved_at_20[0x10]; 5473 u8 op_mod[0x10]; 5474 5475 u8 reserved_at_40[0x60]; 5476 5477 u8 reserved_at_a0[0x8]; 5478 u8 table_index[0x18]; 5479 5480 u8 reserved_at_c0[0x140]; 5481 }; 5482 5483 struct mlx5_ifc_query_issi_out_bits { 5484 u8 status[0x8]; 5485 u8 reserved_at_8[0x18]; 5486 5487 u8 syndrome[0x20]; 5488 5489 u8 reserved_at_40[0x10]; 5490 u8 current_issi[0x10]; 5491 5492 u8 reserved_at_60[0xa0]; 5493 5494 u8 reserved_at_100[76][0x8]; 5495 u8 supported_issi_dw0[0x20]; 5496 }; 5497 5498 struct mlx5_ifc_query_issi_in_bits { 5499 u8 opcode[0x10]; 5500 u8 reserved_at_10[0x10]; 5501 5502 u8 reserved_at_20[0x10]; 5503 u8 op_mod[0x10]; 5504 5505 u8 reserved_at_40[0x40]; 5506 }; 5507 5508 struct mlx5_ifc_set_driver_version_out_bits { 5509 u8 status[0x8]; 5510 u8 reserved_0[0x18]; 5511 5512 u8 syndrome[0x20]; 5513 u8 reserved_1[0x40]; 5514 }; 5515 5516 struct mlx5_ifc_set_driver_version_in_bits { 5517 u8 opcode[0x10]; 5518 u8 reserved_0[0x10]; 5519 5520 u8 reserved_1[0x10]; 5521 u8 op_mod[0x10]; 5522 5523 u8 reserved_2[0x40]; 5524 u8 driver_version[64][0x8]; 5525 }; 5526 5527 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5528 u8 status[0x8]; 5529 u8 reserved_at_8[0x18]; 5530 5531 u8 syndrome[0x20]; 5532 5533 u8 reserved_at_40[0x40]; 5534 5535 struct mlx5_ifc_pkey_bits pkey[]; 5536 }; 5537 5538 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5539 u8 opcode[0x10]; 5540 u8 reserved_at_10[0x10]; 5541 5542 u8 reserved_at_20[0x10]; 5543 u8 op_mod[0x10]; 5544 5545 u8 other_vport[0x1]; 5546 u8 reserved_at_41[0xb]; 5547 u8 port_num[0x4]; 5548 u8 vport_number[0x10]; 5549 5550 u8 reserved_at_60[0x10]; 5551 u8 pkey_index[0x10]; 5552 }; 5553 5554 enum { 5555 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5556 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5557 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5558 }; 5559 5560 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5561 u8 status[0x8]; 5562 u8 reserved_at_8[0x18]; 5563 5564 u8 syndrome[0x20]; 5565 5566 u8 reserved_at_40[0x20]; 5567 5568 u8 gids_num[0x10]; 5569 u8 reserved_at_70[0x10]; 5570 5571 struct mlx5_ifc_array128_auto_bits gid[]; 5572 }; 5573 5574 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5575 u8 opcode[0x10]; 5576 u8 reserved_at_10[0x10]; 5577 5578 u8 reserved_at_20[0x10]; 5579 u8 op_mod[0x10]; 5580 5581 u8 other_vport[0x1]; 5582 u8 reserved_at_41[0xb]; 5583 u8 port_num[0x4]; 5584 u8 vport_number[0x10]; 5585 5586 u8 reserved_at_60[0x10]; 5587 u8 gid_index[0x10]; 5588 }; 5589 5590 struct mlx5_ifc_query_hca_vport_context_out_bits { 5591 u8 status[0x8]; 5592 u8 reserved_at_8[0x18]; 5593 5594 u8 syndrome[0x20]; 5595 5596 u8 reserved_at_40[0x40]; 5597 5598 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5599 }; 5600 5601 struct mlx5_ifc_query_hca_vport_context_in_bits { 5602 u8 opcode[0x10]; 5603 u8 reserved_at_10[0x10]; 5604 5605 u8 reserved_at_20[0x10]; 5606 u8 op_mod[0x10]; 5607 5608 u8 other_vport[0x1]; 5609 u8 reserved_at_41[0xb]; 5610 u8 port_num[0x4]; 5611 u8 vport_number[0x10]; 5612 5613 u8 reserved_at_60[0x20]; 5614 }; 5615 5616 struct mlx5_ifc_query_hca_cap_out_bits { 5617 u8 status[0x8]; 5618 u8 reserved_at_8[0x18]; 5619 5620 u8 syndrome[0x20]; 5621 5622 u8 reserved_at_40[0x40]; 5623 5624 union mlx5_ifc_hca_cap_union_bits capability; 5625 }; 5626 5627 struct mlx5_ifc_query_hca_cap_in_bits { 5628 u8 opcode[0x10]; 5629 u8 reserved_at_10[0x10]; 5630 5631 u8 reserved_at_20[0x10]; 5632 u8 op_mod[0x10]; 5633 5634 u8 other_function[0x1]; 5635 u8 reserved_at_41[0xf]; 5636 u8 function_id[0x10]; 5637 5638 u8 reserved_at_60[0x20]; 5639 }; 5640 5641 struct mlx5_ifc_other_hca_cap_bits { 5642 u8 roce[0x1]; 5643 u8 reserved_at_1[0x27f]; 5644 }; 5645 5646 struct mlx5_ifc_query_other_hca_cap_out_bits { 5647 u8 status[0x8]; 5648 u8 reserved_at_8[0x18]; 5649 5650 u8 syndrome[0x20]; 5651 5652 u8 reserved_at_40[0x40]; 5653 5654 struct mlx5_ifc_other_hca_cap_bits other_capability; 5655 }; 5656 5657 struct mlx5_ifc_query_other_hca_cap_in_bits { 5658 u8 opcode[0x10]; 5659 u8 reserved_at_10[0x10]; 5660 5661 u8 reserved_at_20[0x10]; 5662 u8 op_mod[0x10]; 5663 5664 u8 reserved_at_40[0x10]; 5665 u8 function_id[0x10]; 5666 5667 u8 reserved_at_60[0x20]; 5668 }; 5669 5670 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5671 u8 status[0x8]; 5672 u8 reserved_at_8[0x18]; 5673 5674 u8 syndrome[0x20]; 5675 5676 u8 reserved_at_40[0x40]; 5677 }; 5678 5679 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5680 u8 opcode[0x10]; 5681 u8 reserved_at_10[0x10]; 5682 5683 u8 reserved_at_20[0x10]; 5684 u8 op_mod[0x10]; 5685 5686 u8 reserved_at_40[0x10]; 5687 u8 function_id[0x10]; 5688 u8 field_select[0x20]; 5689 5690 struct mlx5_ifc_other_hca_cap_bits other_capability; 5691 }; 5692 5693 struct mlx5_ifc_flow_table_context_bits { 5694 u8 reformat_en[0x1]; 5695 u8 decap_en[0x1]; 5696 u8 sw_owner[0x1]; 5697 u8 termination_table[0x1]; 5698 u8 table_miss_action[0x4]; 5699 u8 level[0x8]; 5700 u8 reserved_at_10[0x8]; 5701 u8 log_size[0x8]; 5702 5703 u8 reserved_at_20[0x8]; 5704 u8 table_miss_id[0x18]; 5705 5706 u8 reserved_at_40[0x8]; 5707 u8 lag_master_next_table_id[0x18]; 5708 5709 u8 reserved_at_60[0x60]; 5710 5711 u8 sw_owner_icm_root_1[0x40]; 5712 5713 u8 sw_owner_icm_root_0[0x40]; 5714 5715 }; 5716 5717 struct mlx5_ifc_query_flow_table_out_bits { 5718 u8 status[0x8]; 5719 u8 reserved_at_8[0x18]; 5720 5721 u8 syndrome[0x20]; 5722 5723 u8 reserved_at_40[0x80]; 5724 5725 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5726 }; 5727 5728 struct mlx5_ifc_query_flow_table_in_bits { 5729 u8 opcode[0x10]; 5730 u8 reserved_at_10[0x10]; 5731 5732 u8 reserved_at_20[0x10]; 5733 u8 op_mod[0x10]; 5734 5735 u8 reserved_at_40[0x40]; 5736 5737 u8 table_type[0x8]; 5738 u8 reserved_at_88[0x18]; 5739 5740 u8 reserved_at_a0[0x8]; 5741 u8 table_id[0x18]; 5742 5743 u8 reserved_at_c0[0x140]; 5744 }; 5745 5746 struct mlx5_ifc_query_fte_out_bits { 5747 u8 status[0x8]; 5748 u8 reserved_at_8[0x18]; 5749 5750 u8 syndrome[0x20]; 5751 5752 u8 reserved_at_40[0x1c0]; 5753 5754 struct mlx5_ifc_flow_context_bits flow_context; 5755 }; 5756 5757 struct mlx5_ifc_query_fte_in_bits { 5758 u8 opcode[0x10]; 5759 u8 reserved_at_10[0x10]; 5760 5761 u8 reserved_at_20[0x10]; 5762 u8 op_mod[0x10]; 5763 5764 u8 reserved_at_40[0x40]; 5765 5766 u8 table_type[0x8]; 5767 u8 reserved_at_88[0x18]; 5768 5769 u8 reserved_at_a0[0x8]; 5770 u8 table_id[0x18]; 5771 5772 u8 reserved_at_c0[0x40]; 5773 5774 u8 flow_index[0x20]; 5775 5776 u8 reserved_at_120[0xe0]; 5777 }; 5778 5779 struct mlx5_ifc_match_definer_format_0_bits { 5780 u8 reserved_at_0[0x100]; 5781 5782 u8 metadata_reg_c_0[0x20]; 5783 5784 u8 metadata_reg_c_1[0x20]; 5785 5786 u8 outer_dmac_47_16[0x20]; 5787 5788 u8 outer_dmac_15_0[0x10]; 5789 u8 outer_ethertype[0x10]; 5790 5791 u8 reserved_at_180[0x1]; 5792 u8 sx_sniffer[0x1]; 5793 u8 functional_lb[0x1]; 5794 u8 outer_ip_frag[0x1]; 5795 u8 outer_qp_type[0x2]; 5796 u8 outer_encap_type[0x2]; 5797 u8 port_number[0x2]; 5798 u8 outer_l3_type[0x2]; 5799 u8 outer_l4_type[0x2]; 5800 u8 outer_first_vlan_type[0x2]; 5801 u8 outer_first_vlan_prio[0x3]; 5802 u8 outer_first_vlan_cfi[0x1]; 5803 u8 outer_first_vlan_vid[0xc]; 5804 5805 u8 outer_l4_type_ext[0x4]; 5806 u8 reserved_at_1a4[0x2]; 5807 u8 outer_ipsec_layer[0x2]; 5808 u8 outer_l2_type[0x2]; 5809 u8 force_lb[0x1]; 5810 u8 outer_l2_ok[0x1]; 5811 u8 outer_l3_ok[0x1]; 5812 u8 outer_l4_ok[0x1]; 5813 u8 outer_second_vlan_type[0x2]; 5814 u8 outer_second_vlan_prio[0x3]; 5815 u8 outer_second_vlan_cfi[0x1]; 5816 u8 outer_second_vlan_vid[0xc]; 5817 5818 u8 outer_smac_47_16[0x20]; 5819 5820 u8 outer_smac_15_0[0x10]; 5821 u8 inner_ipv4_checksum_ok[0x1]; 5822 u8 inner_l4_checksum_ok[0x1]; 5823 u8 outer_ipv4_checksum_ok[0x1]; 5824 u8 outer_l4_checksum_ok[0x1]; 5825 u8 inner_l3_ok[0x1]; 5826 u8 inner_l4_ok[0x1]; 5827 u8 outer_l3_ok_duplicate[0x1]; 5828 u8 outer_l4_ok_duplicate[0x1]; 5829 u8 outer_tcp_cwr[0x1]; 5830 u8 outer_tcp_ece[0x1]; 5831 u8 outer_tcp_urg[0x1]; 5832 u8 outer_tcp_ack[0x1]; 5833 u8 outer_tcp_psh[0x1]; 5834 u8 outer_tcp_rst[0x1]; 5835 u8 outer_tcp_syn[0x1]; 5836 u8 outer_tcp_fin[0x1]; 5837 }; 5838 5839 struct mlx5_ifc_match_definer_format_22_bits { 5840 u8 reserved_at_0[0x100]; 5841 5842 u8 outer_ip_src_addr[0x20]; 5843 5844 u8 outer_ip_dest_addr[0x20]; 5845 5846 u8 outer_l4_sport[0x10]; 5847 u8 outer_l4_dport[0x10]; 5848 5849 u8 reserved_at_160[0x1]; 5850 u8 sx_sniffer[0x1]; 5851 u8 functional_lb[0x1]; 5852 u8 outer_ip_frag[0x1]; 5853 u8 outer_qp_type[0x2]; 5854 u8 outer_encap_type[0x2]; 5855 u8 port_number[0x2]; 5856 u8 outer_l3_type[0x2]; 5857 u8 outer_l4_type[0x2]; 5858 u8 outer_first_vlan_type[0x2]; 5859 u8 outer_first_vlan_prio[0x3]; 5860 u8 outer_first_vlan_cfi[0x1]; 5861 u8 outer_first_vlan_vid[0xc]; 5862 5863 u8 metadata_reg_c_0[0x20]; 5864 5865 u8 outer_dmac_47_16[0x20]; 5866 5867 u8 outer_smac_47_16[0x20]; 5868 5869 u8 outer_smac_15_0[0x10]; 5870 u8 outer_dmac_15_0[0x10]; 5871 }; 5872 5873 struct mlx5_ifc_match_definer_format_23_bits { 5874 u8 reserved_at_0[0x100]; 5875 5876 u8 inner_ip_src_addr[0x20]; 5877 5878 u8 inner_ip_dest_addr[0x20]; 5879 5880 u8 inner_l4_sport[0x10]; 5881 u8 inner_l4_dport[0x10]; 5882 5883 u8 reserved_at_160[0x1]; 5884 u8 sx_sniffer[0x1]; 5885 u8 functional_lb[0x1]; 5886 u8 inner_ip_frag[0x1]; 5887 u8 inner_qp_type[0x2]; 5888 u8 inner_encap_type[0x2]; 5889 u8 port_number[0x2]; 5890 u8 inner_l3_type[0x2]; 5891 u8 inner_l4_type[0x2]; 5892 u8 inner_first_vlan_type[0x2]; 5893 u8 inner_first_vlan_prio[0x3]; 5894 u8 inner_first_vlan_cfi[0x1]; 5895 u8 inner_first_vlan_vid[0xc]; 5896 5897 u8 tunnel_header_0[0x20]; 5898 5899 u8 inner_dmac_47_16[0x20]; 5900 5901 u8 inner_smac_47_16[0x20]; 5902 5903 u8 inner_smac_15_0[0x10]; 5904 u8 inner_dmac_15_0[0x10]; 5905 }; 5906 5907 struct mlx5_ifc_match_definer_format_29_bits { 5908 u8 reserved_at_0[0xc0]; 5909 5910 u8 outer_ip_dest_addr[0x80]; 5911 5912 u8 outer_ip_src_addr[0x80]; 5913 5914 u8 outer_l4_sport[0x10]; 5915 u8 outer_l4_dport[0x10]; 5916 5917 u8 reserved_at_1e0[0x20]; 5918 }; 5919 5920 struct mlx5_ifc_match_definer_format_30_bits { 5921 u8 reserved_at_0[0xa0]; 5922 5923 u8 outer_ip_dest_addr[0x80]; 5924 5925 u8 outer_ip_src_addr[0x80]; 5926 5927 u8 outer_dmac_47_16[0x20]; 5928 5929 u8 outer_smac_47_16[0x20]; 5930 5931 u8 outer_smac_15_0[0x10]; 5932 u8 outer_dmac_15_0[0x10]; 5933 }; 5934 5935 struct mlx5_ifc_match_definer_format_31_bits { 5936 u8 reserved_at_0[0xc0]; 5937 5938 u8 inner_ip_dest_addr[0x80]; 5939 5940 u8 inner_ip_src_addr[0x80]; 5941 5942 u8 inner_l4_sport[0x10]; 5943 u8 inner_l4_dport[0x10]; 5944 5945 u8 reserved_at_1e0[0x20]; 5946 }; 5947 5948 struct mlx5_ifc_match_definer_format_32_bits { 5949 u8 reserved_at_0[0xa0]; 5950 5951 u8 inner_ip_dest_addr[0x80]; 5952 5953 u8 inner_ip_src_addr[0x80]; 5954 5955 u8 inner_dmac_47_16[0x20]; 5956 5957 u8 inner_smac_47_16[0x20]; 5958 5959 u8 inner_smac_15_0[0x10]; 5960 u8 inner_dmac_15_0[0x10]; 5961 }; 5962 5963 struct mlx5_ifc_match_definer_bits { 5964 u8 modify_field_select[0x40]; 5965 5966 u8 reserved_at_40[0x40]; 5967 5968 u8 reserved_at_80[0x10]; 5969 u8 format_id[0x10]; 5970 5971 u8 reserved_at_a0[0x160]; 5972 5973 u8 match_mask[16][0x20]; 5974 }; 5975 5976 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 5977 u8 opcode[0x10]; 5978 u8 uid[0x10]; 5979 5980 u8 vhca_tunnel_id[0x10]; 5981 u8 obj_type[0x10]; 5982 5983 u8 obj_id[0x20]; 5984 5985 u8 reserved_at_60[0x20]; 5986 }; 5987 5988 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 5989 u8 status[0x8]; 5990 u8 reserved_at_8[0x18]; 5991 5992 u8 syndrome[0x20]; 5993 5994 u8 obj_id[0x20]; 5995 5996 u8 reserved_at_60[0x20]; 5997 }; 5998 5999 struct mlx5_ifc_create_match_definer_in_bits { 6000 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6001 6002 struct mlx5_ifc_match_definer_bits obj_context; 6003 }; 6004 6005 struct mlx5_ifc_create_match_definer_out_bits { 6006 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6007 }; 6008 6009 enum { 6010 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6011 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6012 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6013 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6014 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6015 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6016 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6017 }; 6018 6019 struct mlx5_ifc_query_flow_group_out_bits { 6020 u8 status[0x8]; 6021 u8 reserved_at_8[0x18]; 6022 6023 u8 syndrome[0x20]; 6024 6025 u8 reserved_at_40[0xa0]; 6026 6027 u8 start_flow_index[0x20]; 6028 6029 u8 reserved_at_100[0x20]; 6030 6031 u8 end_flow_index[0x20]; 6032 6033 u8 reserved_at_140[0xa0]; 6034 6035 u8 reserved_at_1e0[0x18]; 6036 u8 match_criteria_enable[0x8]; 6037 6038 struct mlx5_ifc_fte_match_param_bits match_criteria; 6039 6040 u8 reserved_at_1200[0xe00]; 6041 }; 6042 6043 struct mlx5_ifc_query_flow_group_in_bits { 6044 u8 opcode[0x10]; 6045 u8 reserved_at_10[0x10]; 6046 6047 u8 reserved_at_20[0x10]; 6048 u8 op_mod[0x10]; 6049 6050 u8 reserved_at_40[0x40]; 6051 6052 u8 table_type[0x8]; 6053 u8 reserved_at_88[0x18]; 6054 6055 u8 reserved_at_a0[0x8]; 6056 u8 table_id[0x18]; 6057 6058 u8 group_id[0x20]; 6059 6060 u8 reserved_at_e0[0x120]; 6061 }; 6062 6063 struct mlx5_ifc_query_flow_counter_out_bits { 6064 u8 status[0x8]; 6065 u8 reserved_at_8[0x18]; 6066 6067 u8 syndrome[0x20]; 6068 6069 u8 reserved_at_40[0x40]; 6070 6071 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6072 }; 6073 6074 struct mlx5_ifc_query_flow_counter_in_bits { 6075 u8 opcode[0x10]; 6076 u8 reserved_at_10[0x10]; 6077 6078 u8 reserved_at_20[0x10]; 6079 u8 op_mod[0x10]; 6080 6081 u8 reserved_at_40[0x80]; 6082 6083 u8 clear[0x1]; 6084 u8 reserved_at_c1[0xf]; 6085 u8 num_of_counters[0x10]; 6086 6087 u8 flow_counter_id[0x20]; 6088 }; 6089 6090 struct mlx5_ifc_query_esw_vport_context_out_bits { 6091 u8 status[0x8]; 6092 u8 reserved_at_8[0x18]; 6093 6094 u8 syndrome[0x20]; 6095 6096 u8 reserved_at_40[0x40]; 6097 6098 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6099 }; 6100 6101 struct mlx5_ifc_query_esw_vport_context_in_bits { 6102 u8 opcode[0x10]; 6103 u8 reserved_at_10[0x10]; 6104 6105 u8 reserved_at_20[0x10]; 6106 u8 op_mod[0x10]; 6107 6108 u8 other_vport[0x1]; 6109 u8 reserved_at_41[0xf]; 6110 u8 vport_number[0x10]; 6111 6112 u8 reserved_at_60[0x20]; 6113 }; 6114 6115 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6116 u8 status[0x8]; 6117 u8 reserved_at_8[0x18]; 6118 6119 u8 syndrome[0x20]; 6120 6121 u8 reserved_at_40[0x40]; 6122 }; 6123 6124 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6125 u8 reserved_at_0[0x1b]; 6126 u8 fdb_to_vport_reg_c_id[0x1]; 6127 u8 vport_cvlan_insert[0x1]; 6128 u8 vport_svlan_insert[0x1]; 6129 u8 vport_cvlan_strip[0x1]; 6130 u8 vport_svlan_strip[0x1]; 6131 }; 6132 6133 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6134 u8 opcode[0x10]; 6135 u8 reserved_at_10[0x10]; 6136 6137 u8 reserved_at_20[0x10]; 6138 u8 op_mod[0x10]; 6139 6140 u8 other_vport[0x1]; 6141 u8 reserved_at_41[0xf]; 6142 u8 vport_number[0x10]; 6143 6144 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6145 6146 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6147 }; 6148 6149 struct mlx5_ifc_query_eq_out_bits { 6150 u8 status[0x8]; 6151 u8 reserved_at_8[0x18]; 6152 6153 u8 syndrome[0x20]; 6154 6155 u8 reserved_at_40[0x40]; 6156 6157 struct mlx5_ifc_eqc_bits eq_context_entry; 6158 6159 u8 reserved_at_280[0x40]; 6160 6161 u8 event_bitmask[0x40]; 6162 6163 u8 reserved_at_300[0x580]; 6164 6165 u8 pas[][0x40]; 6166 }; 6167 6168 struct mlx5_ifc_query_eq_in_bits { 6169 u8 opcode[0x10]; 6170 u8 reserved_at_10[0x10]; 6171 6172 u8 reserved_at_20[0x10]; 6173 u8 op_mod[0x10]; 6174 6175 u8 reserved_at_40[0x18]; 6176 u8 eq_number[0x8]; 6177 6178 u8 reserved_at_60[0x20]; 6179 }; 6180 6181 struct mlx5_ifc_packet_reformat_context_in_bits { 6182 u8 reformat_type[0x8]; 6183 u8 reserved_at_8[0x4]; 6184 u8 reformat_param_0[0x4]; 6185 u8 reserved_at_10[0x6]; 6186 u8 reformat_data_size[0xa]; 6187 6188 u8 reformat_param_1[0x8]; 6189 u8 reserved_at_28[0x8]; 6190 u8 reformat_data[2][0x8]; 6191 6192 u8 more_reformat_data[][0x8]; 6193 }; 6194 6195 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6196 u8 status[0x8]; 6197 u8 reserved_at_8[0x18]; 6198 6199 u8 syndrome[0x20]; 6200 6201 u8 reserved_at_40[0xa0]; 6202 6203 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6204 }; 6205 6206 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6207 u8 opcode[0x10]; 6208 u8 reserved_at_10[0x10]; 6209 6210 u8 reserved_at_20[0x10]; 6211 u8 op_mod[0x10]; 6212 6213 u8 packet_reformat_id[0x20]; 6214 6215 u8 reserved_at_60[0xa0]; 6216 }; 6217 6218 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6219 u8 status[0x8]; 6220 u8 reserved_at_8[0x18]; 6221 6222 u8 syndrome[0x20]; 6223 6224 u8 packet_reformat_id[0x20]; 6225 6226 u8 reserved_at_60[0x20]; 6227 }; 6228 6229 enum { 6230 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6231 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6232 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6233 }; 6234 6235 enum mlx5_reformat_ctx_type { 6236 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6237 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6238 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6239 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6240 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6241 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6242 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6243 }; 6244 6245 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6246 u8 opcode[0x10]; 6247 u8 reserved_at_10[0x10]; 6248 6249 u8 reserved_at_20[0x10]; 6250 u8 op_mod[0x10]; 6251 6252 u8 reserved_at_40[0xa0]; 6253 6254 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6255 }; 6256 6257 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6258 u8 status[0x8]; 6259 u8 reserved_at_8[0x18]; 6260 6261 u8 syndrome[0x20]; 6262 6263 u8 reserved_at_40[0x40]; 6264 }; 6265 6266 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6267 u8 opcode[0x10]; 6268 u8 reserved_at_10[0x10]; 6269 6270 u8 reserved_20[0x10]; 6271 u8 op_mod[0x10]; 6272 6273 u8 packet_reformat_id[0x20]; 6274 6275 u8 reserved_60[0x20]; 6276 }; 6277 6278 struct mlx5_ifc_set_action_in_bits { 6279 u8 action_type[0x4]; 6280 u8 field[0xc]; 6281 u8 reserved_at_10[0x3]; 6282 u8 offset[0x5]; 6283 u8 reserved_at_18[0x3]; 6284 u8 length[0x5]; 6285 6286 u8 data[0x20]; 6287 }; 6288 6289 struct mlx5_ifc_add_action_in_bits { 6290 u8 action_type[0x4]; 6291 u8 field[0xc]; 6292 u8 reserved_at_10[0x10]; 6293 6294 u8 data[0x20]; 6295 }; 6296 6297 struct mlx5_ifc_copy_action_in_bits { 6298 u8 action_type[0x4]; 6299 u8 src_field[0xc]; 6300 u8 reserved_at_10[0x3]; 6301 u8 src_offset[0x5]; 6302 u8 reserved_at_18[0x3]; 6303 u8 length[0x5]; 6304 6305 u8 reserved_at_20[0x4]; 6306 u8 dst_field[0xc]; 6307 u8 reserved_at_30[0x3]; 6308 u8 dst_offset[0x5]; 6309 u8 reserved_at_38[0x8]; 6310 }; 6311 6312 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6313 struct mlx5_ifc_set_action_in_bits set_action_in; 6314 struct mlx5_ifc_add_action_in_bits add_action_in; 6315 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6316 u8 reserved_at_0[0x40]; 6317 }; 6318 6319 enum { 6320 MLX5_ACTION_TYPE_SET = 0x1, 6321 MLX5_ACTION_TYPE_ADD = 0x2, 6322 MLX5_ACTION_TYPE_COPY = 0x3, 6323 }; 6324 6325 enum { 6326 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6327 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6328 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6329 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6330 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6331 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6332 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6333 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6334 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6335 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6336 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6337 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6338 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6339 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6340 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6341 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6342 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6343 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6344 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6345 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6346 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6347 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6348 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6349 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6350 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6351 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6352 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6353 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6354 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6355 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6356 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6357 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6358 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6359 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6360 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6361 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6362 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6363 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6364 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6365 }; 6366 6367 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6368 u8 status[0x8]; 6369 u8 reserved_at_8[0x18]; 6370 6371 u8 syndrome[0x20]; 6372 6373 u8 modify_header_id[0x20]; 6374 6375 u8 reserved_at_60[0x20]; 6376 }; 6377 6378 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6379 u8 opcode[0x10]; 6380 u8 reserved_at_10[0x10]; 6381 6382 u8 reserved_at_20[0x10]; 6383 u8 op_mod[0x10]; 6384 6385 u8 reserved_at_40[0x20]; 6386 6387 u8 table_type[0x8]; 6388 u8 reserved_at_68[0x10]; 6389 u8 num_of_actions[0x8]; 6390 6391 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6392 }; 6393 6394 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6395 u8 status[0x8]; 6396 u8 reserved_at_8[0x18]; 6397 6398 u8 syndrome[0x20]; 6399 6400 u8 reserved_at_40[0x40]; 6401 }; 6402 6403 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6404 u8 opcode[0x10]; 6405 u8 reserved_at_10[0x10]; 6406 6407 u8 reserved_at_20[0x10]; 6408 u8 op_mod[0x10]; 6409 6410 u8 modify_header_id[0x20]; 6411 6412 u8 reserved_at_60[0x20]; 6413 }; 6414 6415 struct mlx5_ifc_query_modify_header_context_in_bits { 6416 u8 opcode[0x10]; 6417 u8 uid[0x10]; 6418 6419 u8 reserved_at_20[0x10]; 6420 u8 op_mod[0x10]; 6421 6422 u8 modify_header_id[0x20]; 6423 6424 u8 reserved_at_60[0xa0]; 6425 }; 6426 6427 struct mlx5_ifc_query_dct_out_bits { 6428 u8 status[0x8]; 6429 u8 reserved_at_8[0x18]; 6430 6431 u8 syndrome[0x20]; 6432 6433 u8 reserved_at_40[0x40]; 6434 6435 struct mlx5_ifc_dctc_bits dct_context_entry; 6436 6437 u8 reserved_at_280[0x180]; 6438 }; 6439 6440 struct mlx5_ifc_query_dct_in_bits { 6441 u8 opcode[0x10]; 6442 u8 reserved_at_10[0x10]; 6443 6444 u8 reserved_at_20[0x10]; 6445 u8 op_mod[0x10]; 6446 6447 u8 reserved_at_40[0x8]; 6448 u8 dctn[0x18]; 6449 6450 u8 reserved_at_60[0x20]; 6451 }; 6452 6453 struct mlx5_ifc_query_cq_out_bits { 6454 u8 status[0x8]; 6455 u8 reserved_at_8[0x18]; 6456 6457 u8 syndrome[0x20]; 6458 6459 u8 reserved_at_40[0x40]; 6460 6461 struct mlx5_ifc_cqc_bits cq_context; 6462 6463 u8 reserved_at_280[0x600]; 6464 6465 u8 pas[][0x40]; 6466 }; 6467 6468 struct mlx5_ifc_query_cq_in_bits { 6469 u8 opcode[0x10]; 6470 u8 reserved_at_10[0x10]; 6471 6472 u8 reserved_at_20[0x10]; 6473 u8 op_mod[0x10]; 6474 6475 u8 reserved_at_40[0x8]; 6476 u8 cqn[0x18]; 6477 6478 u8 reserved_at_60[0x20]; 6479 }; 6480 6481 struct mlx5_ifc_query_cong_status_out_bits { 6482 u8 status[0x8]; 6483 u8 reserved_at_8[0x18]; 6484 6485 u8 syndrome[0x20]; 6486 6487 u8 reserved_at_40[0x20]; 6488 6489 u8 enable[0x1]; 6490 u8 tag_enable[0x1]; 6491 u8 reserved_at_62[0x1e]; 6492 }; 6493 6494 struct mlx5_ifc_query_cong_status_in_bits { 6495 u8 opcode[0x10]; 6496 u8 reserved_at_10[0x10]; 6497 6498 u8 reserved_at_20[0x10]; 6499 u8 op_mod[0x10]; 6500 6501 u8 reserved_at_40[0x18]; 6502 u8 priority[0x4]; 6503 u8 cong_protocol[0x4]; 6504 6505 u8 reserved_at_60[0x20]; 6506 }; 6507 6508 struct mlx5_ifc_query_cong_statistics_out_bits { 6509 u8 status[0x8]; 6510 u8 reserved_at_8[0x18]; 6511 6512 u8 syndrome[0x20]; 6513 6514 u8 reserved_at_40[0x40]; 6515 6516 u8 rp_cur_flows[0x20]; 6517 6518 u8 sum_flows[0x20]; 6519 6520 u8 rp_cnp_ignored_high[0x20]; 6521 6522 u8 rp_cnp_ignored_low[0x20]; 6523 6524 u8 rp_cnp_handled_high[0x20]; 6525 6526 u8 rp_cnp_handled_low[0x20]; 6527 6528 u8 reserved_at_140[0x100]; 6529 6530 u8 time_stamp_high[0x20]; 6531 6532 u8 time_stamp_low[0x20]; 6533 6534 u8 accumulators_period[0x20]; 6535 6536 u8 np_ecn_marked_roce_packets_high[0x20]; 6537 6538 u8 np_ecn_marked_roce_packets_low[0x20]; 6539 6540 u8 np_cnp_sent_high[0x20]; 6541 6542 u8 np_cnp_sent_low[0x20]; 6543 6544 u8 reserved_at_320[0x560]; 6545 }; 6546 6547 struct mlx5_ifc_query_cong_statistics_in_bits { 6548 u8 opcode[0x10]; 6549 u8 reserved_at_10[0x10]; 6550 6551 u8 reserved_at_20[0x10]; 6552 u8 op_mod[0x10]; 6553 6554 u8 clear[0x1]; 6555 u8 reserved_at_41[0x1f]; 6556 6557 u8 reserved_at_60[0x20]; 6558 }; 6559 6560 struct mlx5_ifc_query_cong_params_out_bits { 6561 u8 status[0x8]; 6562 u8 reserved_at_8[0x18]; 6563 6564 u8 syndrome[0x20]; 6565 6566 u8 reserved_at_40[0x40]; 6567 6568 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6569 }; 6570 6571 struct mlx5_ifc_query_cong_params_in_bits { 6572 u8 opcode[0x10]; 6573 u8 reserved_at_10[0x10]; 6574 6575 u8 reserved_at_20[0x10]; 6576 u8 op_mod[0x10]; 6577 6578 u8 reserved_at_40[0x1c]; 6579 u8 cong_protocol[0x4]; 6580 6581 u8 reserved_at_60[0x20]; 6582 }; 6583 6584 struct mlx5_ifc_query_adapter_out_bits { 6585 u8 status[0x8]; 6586 u8 reserved_at_8[0x18]; 6587 6588 u8 syndrome[0x20]; 6589 6590 u8 reserved_at_40[0x40]; 6591 6592 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6593 }; 6594 6595 struct mlx5_ifc_query_adapter_in_bits { 6596 u8 opcode[0x10]; 6597 u8 reserved_at_10[0x10]; 6598 6599 u8 reserved_at_20[0x10]; 6600 u8 op_mod[0x10]; 6601 6602 u8 reserved_at_40[0x40]; 6603 }; 6604 6605 struct mlx5_ifc_qp_2rst_out_bits { 6606 u8 status[0x8]; 6607 u8 reserved_at_8[0x18]; 6608 6609 u8 syndrome[0x20]; 6610 6611 u8 reserved_at_40[0x40]; 6612 }; 6613 6614 struct mlx5_ifc_qp_2rst_in_bits { 6615 u8 opcode[0x10]; 6616 u8 uid[0x10]; 6617 6618 u8 reserved_at_20[0x10]; 6619 u8 op_mod[0x10]; 6620 6621 u8 reserved_at_40[0x8]; 6622 u8 qpn[0x18]; 6623 6624 u8 reserved_at_60[0x20]; 6625 }; 6626 6627 struct mlx5_ifc_qp_2err_out_bits { 6628 u8 status[0x8]; 6629 u8 reserved_at_8[0x18]; 6630 6631 u8 syndrome[0x20]; 6632 6633 u8 reserved_at_40[0x40]; 6634 }; 6635 6636 struct mlx5_ifc_qp_2err_in_bits { 6637 u8 opcode[0x10]; 6638 u8 uid[0x10]; 6639 6640 u8 reserved_at_20[0x10]; 6641 u8 op_mod[0x10]; 6642 6643 u8 reserved_at_40[0x8]; 6644 u8 qpn[0x18]; 6645 6646 u8 reserved_at_60[0x20]; 6647 }; 6648 6649 struct mlx5_ifc_page_fault_resume_out_bits { 6650 u8 status[0x8]; 6651 u8 reserved_at_8[0x18]; 6652 6653 u8 syndrome[0x20]; 6654 6655 u8 reserved_at_40[0x40]; 6656 }; 6657 6658 struct mlx5_ifc_page_fault_resume_in_bits { 6659 u8 opcode[0x10]; 6660 u8 reserved_at_10[0x10]; 6661 6662 u8 reserved_at_20[0x10]; 6663 u8 op_mod[0x10]; 6664 6665 u8 error[0x1]; 6666 u8 reserved_at_41[0x4]; 6667 u8 page_fault_type[0x3]; 6668 u8 wq_number[0x18]; 6669 6670 u8 reserved_at_60[0x8]; 6671 u8 token[0x18]; 6672 }; 6673 6674 struct mlx5_ifc_nop_out_bits { 6675 u8 status[0x8]; 6676 u8 reserved_at_8[0x18]; 6677 6678 u8 syndrome[0x20]; 6679 6680 u8 reserved_at_40[0x40]; 6681 }; 6682 6683 struct mlx5_ifc_nop_in_bits { 6684 u8 opcode[0x10]; 6685 u8 reserved_at_10[0x10]; 6686 6687 u8 reserved_at_20[0x10]; 6688 u8 op_mod[0x10]; 6689 6690 u8 reserved_at_40[0x40]; 6691 }; 6692 6693 struct mlx5_ifc_modify_vport_state_out_bits { 6694 u8 status[0x8]; 6695 u8 reserved_at_8[0x18]; 6696 6697 u8 syndrome[0x20]; 6698 6699 u8 reserved_at_40[0x40]; 6700 }; 6701 6702 struct mlx5_ifc_modify_vport_state_in_bits { 6703 u8 opcode[0x10]; 6704 u8 reserved_at_10[0x10]; 6705 6706 u8 reserved_at_20[0x10]; 6707 u8 op_mod[0x10]; 6708 6709 u8 other_vport[0x1]; 6710 u8 reserved_at_41[0xf]; 6711 u8 vport_number[0x10]; 6712 6713 u8 reserved_at_60[0x18]; 6714 u8 admin_state[0x4]; 6715 u8 reserved_at_7c[0x4]; 6716 }; 6717 6718 struct mlx5_ifc_modify_tis_out_bits { 6719 u8 status[0x8]; 6720 u8 reserved_at_8[0x18]; 6721 6722 u8 syndrome[0x20]; 6723 6724 u8 reserved_at_40[0x40]; 6725 }; 6726 6727 struct mlx5_ifc_modify_tis_bitmask_bits { 6728 u8 reserved_at_0[0x20]; 6729 6730 u8 reserved_at_20[0x1d]; 6731 u8 lag_tx_port_affinity[0x1]; 6732 u8 strict_lag_tx_port_affinity[0x1]; 6733 u8 prio[0x1]; 6734 }; 6735 6736 struct mlx5_ifc_modify_tis_in_bits { 6737 u8 opcode[0x10]; 6738 u8 uid[0x10]; 6739 6740 u8 reserved_at_20[0x10]; 6741 u8 op_mod[0x10]; 6742 6743 u8 reserved_at_40[0x8]; 6744 u8 tisn[0x18]; 6745 6746 u8 reserved_at_60[0x20]; 6747 6748 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6749 6750 u8 reserved_at_c0[0x40]; 6751 6752 struct mlx5_ifc_tisc_bits ctx; 6753 }; 6754 6755 struct mlx5_ifc_modify_tir_bitmask_bits { 6756 u8 reserved_at_0[0x20]; 6757 6758 u8 reserved_at_20[0x1b]; 6759 u8 self_lb_en[0x1]; 6760 u8 reserved_at_3c[0x1]; 6761 u8 hash[0x1]; 6762 u8 reserved_at_3e[0x1]; 6763 u8 packet_merge[0x1]; 6764 }; 6765 6766 struct mlx5_ifc_modify_tir_out_bits { 6767 u8 status[0x8]; 6768 u8 reserved_at_8[0x18]; 6769 6770 u8 syndrome[0x20]; 6771 6772 u8 reserved_at_40[0x40]; 6773 }; 6774 6775 struct mlx5_ifc_modify_tir_in_bits { 6776 u8 opcode[0x10]; 6777 u8 uid[0x10]; 6778 6779 u8 reserved_at_20[0x10]; 6780 u8 op_mod[0x10]; 6781 6782 u8 reserved_at_40[0x8]; 6783 u8 tirn[0x18]; 6784 6785 u8 reserved_at_60[0x20]; 6786 6787 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6788 6789 u8 reserved_at_c0[0x40]; 6790 6791 struct mlx5_ifc_tirc_bits ctx; 6792 }; 6793 6794 struct mlx5_ifc_modify_sq_out_bits { 6795 u8 status[0x8]; 6796 u8 reserved_at_8[0x18]; 6797 6798 u8 syndrome[0x20]; 6799 6800 u8 reserved_at_40[0x40]; 6801 }; 6802 6803 struct mlx5_ifc_modify_sq_in_bits { 6804 u8 opcode[0x10]; 6805 u8 uid[0x10]; 6806 6807 u8 reserved_at_20[0x10]; 6808 u8 op_mod[0x10]; 6809 6810 u8 sq_state[0x4]; 6811 u8 reserved_at_44[0x4]; 6812 u8 sqn[0x18]; 6813 6814 u8 reserved_at_60[0x20]; 6815 6816 u8 modify_bitmask[0x40]; 6817 6818 u8 reserved_at_c0[0x40]; 6819 6820 struct mlx5_ifc_sqc_bits ctx; 6821 }; 6822 6823 struct mlx5_ifc_modify_scheduling_element_out_bits { 6824 u8 status[0x8]; 6825 u8 reserved_at_8[0x18]; 6826 6827 u8 syndrome[0x20]; 6828 6829 u8 reserved_at_40[0x1c0]; 6830 }; 6831 6832 enum { 6833 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6834 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6835 }; 6836 6837 struct mlx5_ifc_modify_scheduling_element_in_bits { 6838 u8 opcode[0x10]; 6839 u8 reserved_at_10[0x10]; 6840 6841 u8 reserved_at_20[0x10]; 6842 u8 op_mod[0x10]; 6843 6844 u8 scheduling_hierarchy[0x8]; 6845 u8 reserved_at_48[0x18]; 6846 6847 u8 scheduling_element_id[0x20]; 6848 6849 u8 reserved_at_80[0x20]; 6850 6851 u8 modify_bitmask[0x20]; 6852 6853 u8 reserved_at_c0[0x40]; 6854 6855 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6856 6857 u8 reserved_at_300[0x100]; 6858 }; 6859 6860 struct mlx5_ifc_modify_rqt_out_bits { 6861 u8 status[0x8]; 6862 u8 reserved_at_8[0x18]; 6863 6864 u8 syndrome[0x20]; 6865 6866 u8 reserved_at_40[0x40]; 6867 }; 6868 6869 struct mlx5_ifc_rqt_bitmask_bits { 6870 u8 reserved_at_0[0x20]; 6871 6872 u8 reserved_at_20[0x1f]; 6873 u8 rqn_list[0x1]; 6874 }; 6875 6876 struct mlx5_ifc_modify_rqt_in_bits { 6877 u8 opcode[0x10]; 6878 u8 uid[0x10]; 6879 6880 u8 reserved_at_20[0x10]; 6881 u8 op_mod[0x10]; 6882 6883 u8 reserved_at_40[0x8]; 6884 u8 rqtn[0x18]; 6885 6886 u8 reserved_at_60[0x20]; 6887 6888 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6889 6890 u8 reserved_at_c0[0x40]; 6891 6892 struct mlx5_ifc_rqtc_bits ctx; 6893 }; 6894 6895 struct mlx5_ifc_modify_rq_out_bits { 6896 u8 status[0x8]; 6897 u8 reserved_at_8[0x18]; 6898 6899 u8 syndrome[0x20]; 6900 6901 u8 reserved_at_40[0x40]; 6902 }; 6903 6904 enum { 6905 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6906 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6907 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6908 }; 6909 6910 struct mlx5_ifc_modify_rq_in_bits { 6911 u8 opcode[0x10]; 6912 u8 uid[0x10]; 6913 6914 u8 reserved_at_20[0x10]; 6915 u8 op_mod[0x10]; 6916 6917 u8 rq_state[0x4]; 6918 u8 reserved_at_44[0x4]; 6919 u8 rqn[0x18]; 6920 6921 u8 reserved_at_60[0x20]; 6922 6923 u8 modify_bitmask[0x40]; 6924 6925 u8 reserved_at_c0[0x40]; 6926 6927 struct mlx5_ifc_rqc_bits ctx; 6928 }; 6929 6930 struct mlx5_ifc_modify_rmp_out_bits { 6931 u8 status[0x8]; 6932 u8 reserved_at_8[0x18]; 6933 6934 u8 syndrome[0x20]; 6935 6936 u8 reserved_at_40[0x40]; 6937 }; 6938 6939 struct mlx5_ifc_rmp_bitmask_bits { 6940 u8 reserved_at_0[0x20]; 6941 6942 u8 reserved_at_20[0x1f]; 6943 u8 lwm[0x1]; 6944 }; 6945 6946 struct mlx5_ifc_modify_rmp_in_bits { 6947 u8 opcode[0x10]; 6948 u8 uid[0x10]; 6949 6950 u8 reserved_at_20[0x10]; 6951 u8 op_mod[0x10]; 6952 6953 u8 rmp_state[0x4]; 6954 u8 reserved_at_44[0x4]; 6955 u8 rmpn[0x18]; 6956 6957 u8 reserved_at_60[0x20]; 6958 6959 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6960 6961 u8 reserved_at_c0[0x40]; 6962 6963 struct mlx5_ifc_rmpc_bits ctx; 6964 }; 6965 6966 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6967 u8 status[0x8]; 6968 u8 reserved_at_8[0x18]; 6969 6970 u8 syndrome[0x20]; 6971 6972 u8 reserved_at_40[0x40]; 6973 }; 6974 6975 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6976 u8 reserved_at_0[0x12]; 6977 u8 affiliation[0x1]; 6978 u8 reserved_at_13[0x1]; 6979 u8 disable_uc_local_lb[0x1]; 6980 u8 disable_mc_local_lb[0x1]; 6981 u8 node_guid[0x1]; 6982 u8 port_guid[0x1]; 6983 u8 min_inline[0x1]; 6984 u8 mtu[0x1]; 6985 u8 change_event[0x1]; 6986 u8 promisc[0x1]; 6987 u8 permanent_address[0x1]; 6988 u8 addresses_list[0x1]; 6989 u8 roce_en[0x1]; 6990 u8 reserved_at_1f[0x1]; 6991 }; 6992 6993 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6994 u8 opcode[0x10]; 6995 u8 reserved_at_10[0x10]; 6996 6997 u8 reserved_at_20[0x10]; 6998 u8 op_mod[0x10]; 6999 7000 u8 other_vport[0x1]; 7001 u8 reserved_at_41[0xf]; 7002 u8 vport_number[0x10]; 7003 7004 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7005 7006 u8 reserved_at_80[0x780]; 7007 7008 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7009 }; 7010 7011 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7012 u8 status[0x8]; 7013 u8 reserved_at_8[0x18]; 7014 7015 u8 syndrome[0x20]; 7016 7017 u8 reserved_at_40[0x40]; 7018 }; 7019 7020 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7021 u8 opcode[0x10]; 7022 u8 reserved_at_10[0x10]; 7023 7024 u8 reserved_at_20[0x10]; 7025 u8 op_mod[0x10]; 7026 7027 u8 other_vport[0x1]; 7028 u8 reserved_at_41[0xb]; 7029 u8 port_num[0x4]; 7030 u8 vport_number[0x10]; 7031 7032 u8 reserved_at_60[0x20]; 7033 7034 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7035 }; 7036 7037 struct mlx5_ifc_modify_cq_out_bits { 7038 u8 status[0x8]; 7039 u8 reserved_at_8[0x18]; 7040 7041 u8 syndrome[0x20]; 7042 7043 u8 reserved_at_40[0x40]; 7044 }; 7045 7046 enum { 7047 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7048 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7049 }; 7050 7051 struct mlx5_ifc_modify_cq_in_bits { 7052 u8 opcode[0x10]; 7053 u8 uid[0x10]; 7054 7055 u8 reserved_at_20[0x10]; 7056 u8 op_mod[0x10]; 7057 7058 u8 reserved_at_40[0x8]; 7059 u8 cqn[0x18]; 7060 7061 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7062 7063 struct mlx5_ifc_cqc_bits cq_context; 7064 7065 u8 reserved_at_280[0x60]; 7066 7067 u8 cq_umem_valid[0x1]; 7068 u8 reserved_at_2e1[0x1f]; 7069 7070 u8 reserved_at_300[0x580]; 7071 7072 u8 pas[][0x40]; 7073 }; 7074 7075 struct mlx5_ifc_modify_cong_status_out_bits { 7076 u8 status[0x8]; 7077 u8 reserved_at_8[0x18]; 7078 7079 u8 syndrome[0x20]; 7080 7081 u8 reserved_at_40[0x40]; 7082 }; 7083 7084 struct mlx5_ifc_modify_cong_status_in_bits { 7085 u8 opcode[0x10]; 7086 u8 reserved_at_10[0x10]; 7087 7088 u8 reserved_at_20[0x10]; 7089 u8 op_mod[0x10]; 7090 7091 u8 reserved_at_40[0x18]; 7092 u8 priority[0x4]; 7093 u8 cong_protocol[0x4]; 7094 7095 u8 enable[0x1]; 7096 u8 tag_enable[0x1]; 7097 u8 reserved_at_62[0x1e]; 7098 }; 7099 7100 struct mlx5_ifc_modify_cong_params_out_bits { 7101 u8 status[0x8]; 7102 u8 reserved_at_8[0x18]; 7103 7104 u8 syndrome[0x20]; 7105 7106 u8 reserved_at_40[0x40]; 7107 }; 7108 7109 struct mlx5_ifc_modify_cong_params_in_bits { 7110 u8 opcode[0x10]; 7111 u8 reserved_at_10[0x10]; 7112 7113 u8 reserved_at_20[0x10]; 7114 u8 op_mod[0x10]; 7115 7116 u8 reserved_at_40[0x1c]; 7117 u8 cong_protocol[0x4]; 7118 7119 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7120 7121 u8 reserved_at_80[0x80]; 7122 7123 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7124 }; 7125 7126 struct mlx5_ifc_manage_pages_out_bits { 7127 u8 status[0x8]; 7128 u8 reserved_at_8[0x18]; 7129 7130 u8 syndrome[0x20]; 7131 7132 u8 output_num_entries[0x20]; 7133 7134 u8 reserved_at_60[0x20]; 7135 7136 u8 pas[][0x40]; 7137 }; 7138 7139 enum { 7140 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7141 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7142 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7143 }; 7144 7145 struct mlx5_ifc_manage_pages_in_bits { 7146 u8 opcode[0x10]; 7147 u8 reserved_at_10[0x10]; 7148 7149 u8 reserved_at_20[0x10]; 7150 u8 op_mod[0x10]; 7151 7152 u8 embedded_cpu_function[0x1]; 7153 u8 reserved_at_41[0xf]; 7154 u8 function_id[0x10]; 7155 7156 u8 input_num_entries[0x20]; 7157 7158 u8 pas[][0x40]; 7159 }; 7160 7161 struct mlx5_ifc_mad_ifc_out_bits { 7162 u8 status[0x8]; 7163 u8 reserved_at_8[0x18]; 7164 7165 u8 syndrome[0x20]; 7166 7167 u8 reserved_at_40[0x40]; 7168 7169 u8 response_mad_packet[256][0x8]; 7170 }; 7171 7172 struct mlx5_ifc_mad_ifc_in_bits { 7173 u8 opcode[0x10]; 7174 u8 reserved_at_10[0x10]; 7175 7176 u8 reserved_at_20[0x10]; 7177 u8 op_mod[0x10]; 7178 7179 u8 remote_lid[0x10]; 7180 u8 reserved_at_50[0x8]; 7181 u8 port[0x8]; 7182 7183 u8 reserved_at_60[0x20]; 7184 7185 u8 mad[256][0x8]; 7186 }; 7187 7188 struct mlx5_ifc_init_hca_out_bits { 7189 u8 status[0x8]; 7190 u8 reserved_at_8[0x18]; 7191 7192 u8 syndrome[0x20]; 7193 7194 u8 reserved_at_40[0x40]; 7195 }; 7196 7197 struct mlx5_ifc_init_hca_in_bits { 7198 u8 opcode[0x10]; 7199 u8 reserved_at_10[0x10]; 7200 7201 u8 reserved_at_20[0x10]; 7202 u8 op_mod[0x10]; 7203 7204 u8 reserved_at_40[0x20]; 7205 7206 u8 reserved_at_60[0x2]; 7207 u8 sw_vhca_id[0xe]; 7208 u8 reserved_at_70[0x10]; 7209 7210 u8 sw_owner_id[4][0x20]; 7211 }; 7212 7213 struct mlx5_ifc_init2rtr_qp_out_bits { 7214 u8 status[0x8]; 7215 u8 reserved_at_8[0x18]; 7216 7217 u8 syndrome[0x20]; 7218 7219 u8 reserved_at_40[0x20]; 7220 u8 ece[0x20]; 7221 }; 7222 7223 struct mlx5_ifc_init2rtr_qp_in_bits { 7224 u8 opcode[0x10]; 7225 u8 uid[0x10]; 7226 7227 u8 reserved_at_20[0x10]; 7228 u8 op_mod[0x10]; 7229 7230 u8 reserved_at_40[0x8]; 7231 u8 qpn[0x18]; 7232 7233 u8 reserved_at_60[0x20]; 7234 7235 u8 opt_param_mask[0x20]; 7236 7237 u8 ece[0x20]; 7238 7239 struct mlx5_ifc_qpc_bits qpc; 7240 7241 u8 reserved_at_800[0x80]; 7242 }; 7243 7244 struct mlx5_ifc_init2init_qp_out_bits { 7245 u8 status[0x8]; 7246 u8 reserved_at_8[0x18]; 7247 7248 u8 syndrome[0x20]; 7249 7250 u8 reserved_at_40[0x20]; 7251 u8 ece[0x20]; 7252 }; 7253 7254 struct mlx5_ifc_init2init_qp_in_bits { 7255 u8 opcode[0x10]; 7256 u8 uid[0x10]; 7257 7258 u8 reserved_at_20[0x10]; 7259 u8 op_mod[0x10]; 7260 7261 u8 reserved_at_40[0x8]; 7262 u8 qpn[0x18]; 7263 7264 u8 reserved_at_60[0x20]; 7265 7266 u8 opt_param_mask[0x20]; 7267 7268 u8 ece[0x20]; 7269 7270 struct mlx5_ifc_qpc_bits qpc; 7271 7272 u8 reserved_at_800[0x80]; 7273 }; 7274 7275 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7276 u8 status[0x8]; 7277 u8 reserved_at_8[0x18]; 7278 7279 u8 syndrome[0x20]; 7280 7281 u8 reserved_at_40[0x40]; 7282 7283 u8 packet_headers_log[128][0x8]; 7284 7285 u8 packet_syndrome[64][0x8]; 7286 }; 7287 7288 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7289 u8 opcode[0x10]; 7290 u8 reserved_at_10[0x10]; 7291 7292 u8 reserved_at_20[0x10]; 7293 u8 op_mod[0x10]; 7294 7295 u8 reserved_at_40[0x40]; 7296 }; 7297 7298 struct mlx5_ifc_gen_eqe_in_bits { 7299 u8 opcode[0x10]; 7300 u8 reserved_at_10[0x10]; 7301 7302 u8 reserved_at_20[0x10]; 7303 u8 op_mod[0x10]; 7304 7305 u8 reserved_at_40[0x18]; 7306 u8 eq_number[0x8]; 7307 7308 u8 reserved_at_60[0x20]; 7309 7310 u8 eqe[64][0x8]; 7311 }; 7312 7313 struct mlx5_ifc_gen_eq_out_bits { 7314 u8 status[0x8]; 7315 u8 reserved_at_8[0x18]; 7316 7317 u8 syndrome[0x20]; 7318 7319 u8 reserved_at_40[0x40]; 7320 }; 7321 7322 struct mlx5_ifc_enable_hca_out_bits { 7323 u8 status[0x8]; 7324 u8 reserved_at_8[0x18]; 7325 7326 u8 syndrome[0x20]; 7327 7328 u8 reserved_at_40[0x20]; 7329 }; 7330 7331 struct mlx5_ifc_enable_hca_in_bits { 7332 u8 opcode[0x10]; 7333 u8 reserved_at_10[0x10]; 7334 7335 u8 reserved_at_20[0x10]; 7336 u8 op_mod[0x10]; 7337 7338 u8 embedded_cpu_function[0x1]; 7339 u8 reserved_at_41[0xf]; 7340 u8 function_id[0x10]; 7341 7342 u8 reserved_at_60[0x20]; 7343 }; 7344 7345 struct mlx5_ifc_drain_dct_out_bits { 7346 u8 status[0x8]; 7347 u8 reserved_at_8[0x18]; 7348 7349 u8 syndrome[0x20]; 7350 7351 u8 reserved_at_40[0x40]; 7352 }; 7353 7354 struct mlx5_ifc_drain_dct_in_bits { 7355 u8 opcode[0x10]; 7356 u8 uid[0x10]; 7357 7358 u8 reserved_at_20[0x10]; 7359 u8 op_mod[0x10]; 7360 7361 u8 reserved_at_40[0x8]; 7362 u8 dctn[0x18]; 7363 7364 u8 reserved_at_60[0x20]; 7365 }; 7366 7367 struct mlx5_ifc_disable_hca_out_bits { 7368 u8 status[0x8]; 7369 u8 reserved_at_8[0x18]; 7370 7371 u8 syndrome[0x20]; 7372 7373 u8 reserved_at_40[0x20]; 7374 }; 7375 7376 struct mlx5_ifc_disable_hca_in_bits { 7377 u8 opcode[0x10]; 7378 u8 reserved_at_10[0x10]; 7379 7380 u8 reserved_at_20[0x10]; 7381 u8 op_mod[0x10]; 7382 7383 u8 embedded_cpu_function[0x1]; 7384 u8 reserved_at_41[0xf]; 7385 u8 function_id[0x10]; 7386 7387 u8 reserved_at_60[0x20]; 7388 }; 7389 7390 struct mlx5_ifc_detach_from_mcg_out_bits { 7391 u8 status[0x8]; 7392 u8 reserved_at_8[0x18]; 7393 7394 u8 syndrome[0x20]; 7395 7396 u8 reserved_at_40[0x40]; 7397 }; 7398 7399 struct mlx5_ifc_detach_from_mcg_in_bits { 7400 u8 opcode[0x10]; 7401 u8 uid[0x10]; 7402 7403 u8 reserved_at_20[0x10]; 7404 u8 op_mod[0x10]; 7405 7406 u8 reserved_at_40[0x8]; 7407 u8 qpn[0x18]; 7408 7409 u8 reserved_at_60[0x20]; 7410 7411 u8 multicast_gid[16][0x8]; 7412 }; 7413 7414 struct mlx5_ifc_destroy_xrq_out_bits { 7415 u8 status[0x8]; 7416 u8 reserved_at_8[0x18]; 7417 7418 u8 syndrome[0x20]; 7419 7420 u8 reserved_at_40[0x40]; 7421 }; 7422 7423 struct mlx5_ifc_destroy_xrq_in_bits { 7424 u8 opcode[0x10]; 7425 u8 uid[0x10]; 7426 7427 u8 reserved_at_20[0x10]; 7428 u8 op_mod[0x10]; 7429 7430 u8 reserved_at_40[0x8]; 7431 u8 xrqn[0x18]; 7432 7433 u8 reserved_at_60[0x20]; 7434 }; 7435 7436 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7437 u8 status[0x8]; 7438 u8 reserved_at_8[0x18]; 7439 7440 u8 syndrome[0x20]; 7441 7442 u8 reserved_at_40[0x40]; 7443 }; 7444 7445 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7446 u8 opcode[0x10]; 7447 u8 uid[0x10]; 7448 7449 u8 reserved_at_20[0x10]; 7450 u8 op_mod[0x10]; 7451 7452 u8 reserved_at_40[0x8]; 7453 u8 xrc_srqn[0x18]; 7454 7455 u8 reserved_at_60[0x20]; 7456 }; 7457 7458 struct mlx5_ifc_destroy_tis_out_bits { 7459 u8 status[0x8]; 7460 u8 reserved_at_8[0x18]; 7461 7462 u8 syndrome[0x20]; 7463 7464 u8 reserved_at_40[0x40]; 7465 }; 7466 7467 struct mlx5_ifc_destroy_tis_in_bits { 7468 u8 opcode[0x10]; 7469 u8 uid[0x10]; 7470 7471 u8 reserved_at_20[0x10]; 7472 u8 op_mod[0x10]; 7473 7474 u8 reserved_at_40[0x8]; 7475 u8 tisn[0x18]; 7476 7477 u8 reserved_at_60[0x20]; 7478 }; 7479 7480 struct mlx5_ifc_destroy_tir_out_bits { 7481 u8 status[0x8]; 7482 u8 reserved_at_8[0x18]; 7483 7484 u8 syndrome[0x20]; 7485 7486 u8 reserved_at_40[0x40]; 7487 }; 7488 7489 struct mlx5_ifc_destroy_tir_in_bits { 7490 u8 opcode[0x10]; 7491 u8 uid[0x10]; 7492 7493 u8 reserved_at_20[0x10]; 7494 u8 op_mod[0x10]; 7495 7496 u8 reserved_at_40[0x8]; 7497 u8 tirn[0x18]; 7498 7499 u8 reserved_at_60[0x20]; 7500 }; 7501 7502 struct mlx5_ifc_destroy_srq_out_bits { 7503 u8 status[0x8]; 7504 u8 reserved_at_8[0x18]; 7505 7506 u8 syndrome[0x20]; 7507 7508 u8 reserved_at_40[0x40]; 7509 }; 7510 7511 struct mlx5_ifc_destroy_srq_in_bits { 7512 u8 opcode[0x10]; 7513 u8 uid[0x10]; 7514 7515 u8 reserved_at_20[0x10]; 7516 u8 op_mod[0x10]; 7517 7518 u8 reserved_at_40[0x8]; 7519 u8 srqn[0x18]; 7520 7521 u8 reserved_at_60[0x20]; 7522 }; 7523 7524 struct mlx5_ifc_destroy_sq_out_bits { 7525 u8 status[0x8]; 7526 u8 reserved_at_8[0x18]; 7527 7528 u8 syndrome[0x20]; 7529 7530 u8 reserved_at_40[0x40]; 7531 }; 7532 7533 struct mlx5_ifc_destroy_sq_in_bits { 7534 u8 opcode[0x10]; 7535 u8 uid[0x10]; 7536 7537 u8 reserved_at_20[0x10]; 7538 u8 op_mod[0x10]; 7539 7540 u8 reserved_at_40[0x8]; 7541 u8 sqn[0x18]; 7542 7543 u8 reserved_at_60[0x20]; 7544 }; 7545 7546 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7547 u8 status[0x8]; 7548 u8 reserved_at_8[0x18]; 7549 7550 u8 syndrome[0x20]; 7551 7552 u8 reserved_at_40[0x1c0]; 7553 }; 7554 7555 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7556 u8 opcode[0x10]; 7557 u8 reserved_at_10[0x10]; 7558 7559 u8 reserved_at_20[0x10]; 7560 u8 op_mod[0x10]; 7561 7562 u8 scheduling_hierarchy[0x8]; 7563 u8 reserved_at_48[0x18]; 7564 7565 u8 scheduling_element_id[0x20]; 7566 7567 u8 reserved_at_80[0x180]; 7568 }; 7569 7570 struct mlx5_ifc_destroy_rqt_out_bits { 7571 u8 status[0x8]; 7572 u8 reserved_at_8[0x18]; 7573 7574 u8 syndrome[0x20]; 7575 7576 u8 reserved_at_40[0x40]; 7577 }; 7578 7579 struct mlx5_ifc_destroy_rqt_in_bits { 7580 u8 opcode[0x10]; 7581 u8 uid[0x10]; 7582 7583 u8 reserved_at_20[0x10]; 7584 u8 op_mod[0x10]; 7585 7586 u8 reserved_at_40[0x8]; 7587 u8 rqtn[0x18]; 7588 7589 u8 reserved_at_60[0x20]; 7590 }; 7591 7592 struct mlx5_ifc_destroy_rq_out_bits { 7593 u8 status[0x8]; 7594 u8 reserved_at_8[0x18]; 7595 7596 u8 syndrome[0x20]; 7597 7598 u8 reserved_at_40[0x40]; 7599 }; 7600 7601 struct mlx5_ifc_destroy_rq_in_bits { 7602 u8 opcode[0x10]; 7603 u8 uid[0x10]; 7604 7605 u8 reserved_at_20[0x10]; 7606 u8 op_mod[0x10]; 7607 7608 u8 reserved_at_40[0x8]; 7609 u8 rqn[0x18]; 7610 7611 u8 reserved_at_60[0x20]; 7612 }; 7613 7614 struct mlx5_ifc_set_delay_drop_params_in_bits { 7615 u8 opcode[0x10]; 7616 u8 reserved_at_10[0x10]; 7617 7618 u8 reserved_at_20[0x10]; 7619 u8 op_mod[0x10]; 7620 7621 u8 reserved_at_40[0x20]; 7622 7623 u8 reserved_at_60[0x10]; 7624 u8 delay_drop_timeout[0x10]; 7625 }; 7626 7627 struct mlx5_ifc_set_delay_drop_params_out_bits { 7628 u8 status[0x8]; 7629 u8 reserved_at_8[0x18]; 7630 7631 u8 syndrome[0x20]; 7632 7633 u8 reserved_at_40[0x40]; 7634 }; 7635 7636 struct mlx5_ifc_destroy_rmp_out_bits { 7637 u8 status[0x8]; 7638 u8 reserved_at_8[0x18]; 7639 7640 u8 syndrome[0x20]; 7641 7642 u8 reserved_at_40[0x40]; 7643 }; 7644 7645 struct mlx5_ifc_destroy_rmp_in_bits { 7646 u8 opcode[0x10]; 7647 u8 uid[0x10]; 7648 7649 u8 reserved_at_20[0x10]; 7650 u8 op_mod[0x10]; 7651 7652 u8 reserved_at_40[0x8]; 7653 u8 rmpn[0x18]; 7654 7655 u8 reserved_at_60[0x20]; 7656 }; 7657 7658 struct mlx5_ifc_destroy_qp_out_bits { 7659 u8 status[0x8]; 7660 u8 reserved_at_8[0x18]; 7661 7662 u8 syndrome[0x20]; 7663 7664 u8 reserved_at_40[0x40]; 7665 }; 7666 7667 struct mlx5_ifc_destroy_qp_in_bits { 7668 u8 opcode[0x10]; 7669 u8 uid[0x10]; 7670 7671 u8 reserved_at_20[0x10]; 7672 u8 op_mod[0x10]; 7673 7674 u8 reserved_at_40[0x8]; 7675 u8 qpn[0x18]; 7676 7677 u8 reserved_at_60[0x20]; 7678 }; 7679 7680 struct mlx5_ifc_destroy_psv_out_bits { 7681 u8 status[0x8]; 7682 u8 reserved_at_8[0x18]; 7683 7684 u8 syndrome[0x20]; 7685 7686 u8 reserved_at_40[0x40]; 7687 }; 7688 7689 struct mlx5_ifc_destroy_psv_in_bits { 7690 u8 opcode[0x10]; 7691 u8 reserved_at_10[0x10]; 7692 7693 u8 reserved_at_20[0x10]; 7694 u8 op_mod[0x10]; 7695 7696 u8 reserved_at_40[0x8]; 7697 u8 psvn[0x18]; 7698 7699 u8 reserved_at_60[0x20]; 7700 }; 7701 7702 struct mlx5_ifc_destroy_mkey_out_bits { 7703 u8 status[0x8]; 7704 u8 reserved_at_8[0x18]; 7705 7706 u8 syndrome[0x20]; 7707 7708 u8 reserved_at_40[0x40]; 7709 }; 7710 7711 struct mlx5_ifc_destroy_mkey_in_bits { 7712 u8 opcode[0x10]; 7713 u8 uid[0x10]; 7714 7715 u8 reserved_at_20[0x10]; 7716 u8 op_mod[0x10]; 7717 7718 u8 reserved_at_40[0x8]; 7719 u8 mkey_index[0x18]; 7720 7721 u8 reserved_at_60[0x20]; 7722 }; 7723 7724 struct mlx5_ifc_destroy_flow_table_out_bits { 7725 u8 status[0x8]; 7726 u8 reserved_at_8[0x18]; 7727 7728 u8 syndrome[0x20]; 7729 7730 u8 reserved_at_40[0x40]; 7731 }; 7732 7733 struct mlx5_ifc_destroy_flow_table_in_bits { 7734 u8 opcode[0x10]; 7735 u8 reserved_at_10[0x10]; 7736 7737 u8 reserved_at_20[0x10]; 7738 u8 op_mod[0x10]; 7739 7740 u8 other_vport[0x1]; 7741 u8 reserved_at_41[0xf]; 7742 u8 vport_number[0x10]; 7743 7744 u8 reserved_at_60[0x20]; 7745 7746 u8 table_type[0x8]; 7747 u8 reserved_at_88[0x18]; 7748 7749 u8 reserved_at_a0[0x8]; 7750 u8 table_id[0x18]; 7751 7752 u8 reserved_at_c0[0x140]; 7753 }; 7754 7755 struct mlx5_ifc_destroy_flow_group_out_bits { 7756 u8 status[0x8]; 7757 u8 reserved_at_8[0x18]; 7758 7759 u8 syndrome[0x20]; 7760 7761 u8 reserved_at_40[0x40]; 7762 }; 7763 7764 struct mlx5_ifc_destroy_flow_group_in_bits { 7765 u8 opcode[0x10]; 7766 u8 reserved_at_10[0x10]; 7767 7768 u8 reserved_at_20[0x10]; 7769 u8 op_mod[0x10]; 7770 7771 u8 other_vport[0x1]; 7772 u8 reserved_at_41[0xf]; 7773 u8 vport_number[0x10]; 7774 7775 u8 reserved_at_60[0x20]; 7776 7777 u8 table_type[0x8]; 7778 u8 reserved_at_88[0x18]; 7779 7780 u8 reserved_at_a0[0x8]; 7781 u8 table_id[0x18]; 7782 7783 u8 group_id[0x20]; 7784 7785 u8 reserved_at_e0[0x120]; 7786 }; 7787 7788 struct mlx5_ifc_destroy_eq_out_bits { 7789 u8 status[0x8]; 7790 u8 reserved_at_8[0x18]; 7791 7792 u8 syndrome[0x20]; 7793 7794 u8 reserved_at_40[0x40]; 7795 }; 7796 7797 struct mlx5_ifc_destroy_eq_in_bits { 7798 u8 opcode[0x10]; 7799 u8 reserved_at_10[0x10]; 7800 7801 u8 reserved_at_20[0x10]; 7802 u8 op_mod[0x10]; 7803 7804 u8 reserved_at_40[0x18]; 7805 u8 eq_number[0x8]; 7806 7807 u8 reserved_at_60[0x20]; 7808 }; 7809 7810 struct mlx5_ifc_destroy_dct_out_bits { 7811 u8 status[0x8]; 7812 u8 reserved_at_8[0x18]; 7813 7814 u8 syndrome[0x20]; 7815 7816 u8 reserved_at_40[0x40]; 7817 }; 7818 7819 struct mlx5_ifc_destroy_dct_in_bits { 7820 u8 opcode[0x10]; 7821 u8 uid[0x10]; 7822 7823 u8 reserved_at_20[0x10]; 7824 u8 op_mod[0x10]; 7825 7826 u8 reserved_at_40[0x8]; 7827 u8 dctn[0x18]; 7828 7829 u8 reserved_at_60[0x20]; 7830 }; 7831 7832 struct mlx5_ifc_destroy_cq_out_bits { 7833 u8 status[0x8]; 7834 u8 reserved_at_8[0x18]; 7835 7836 u8 syndrome[0x20]; 7837 7838 u8 reserved_at_40[0x40]; 7839 }; 7840 7841 struct mlx5_ifc_destroy_cq_in_bits { 7842 u8 opcode[0x10]; 7843 u8 uid[0x10]; 7844 7845 u8 reserved_at_20[0x10]; 7846 u8 op_mod[0x10]; 7847 7848 u8 reserved_at_40[0x8]; 7849 u8 cqn[0x18]; 7850 7851 u8 reserved_at_60[0x20]; 7852 }; 7853 7854 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7855 u8 status[0x8]; 7856 u8 reserved_at_8[0x18]; 7857 7858 u8 syndrome[0x20]; 7859 7860 u8 reserved_at_40[0x40]; 7861 }; 7862 7863 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7864 u8 opcode[0x10]; 7865 u8 reserved_at_10[0x10]; 7866 7867 u8 reserved_at_20[0x10]; 7868 u8 op_mod[0x10]; 7869 7870 u8 reserved_at_40[0x20]; 7871 7872 u8 reserved_at_60[0x10]; 7873 u8 vxlan_udp_port[0x10]; 7874 }; 7875 7876 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7877 u8 status[0x8]; 7878 u8 reserved_at_8[0x18]; 7879 7880 u8 syndrome[0x20]; 7881 7882 u8 reserved_at_40[0x40]; 7883 }; 7884 7885 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7886 u8 opcode[0x10]; 7887 u8 reserved_at_10[0x10]; 7888 7889 u8 reserved_at_20[0x10]; 7890 u8 op_mod[0x10]; 7891 7892 u8 reserved_at_40[0x60]; 7893 7894 u8 reserved_at_a0[0x8]; 7895 u8 table_index[0x18]; 7896 7897 u8 reserved_at_c0[0x140]; 7898 }; 7899 7900 struct mlx5_ifc_delete_fte_out_bits { 7901 u8 status[0x8]; 7902 u8 reserved_at_8[0x18]; 7903 7904 u8 syndrome[0x20]; 7905 7906 u8 reserved_at_40[0x40]; 7907 }; 7908 7909 struct mlx5_ifc_delete_fte_in_bits { 7910 u8 opcode[0x10]; 7911 u8 reserved_at_10[0x10]; 7912 7913 u8 reserved_at_20[0x10]; 7914 u8 op_mod[0x10]; 7915 7916 u8 other_vport[0x1]; 7917 u8 reserved_at_41[0xf]; 7918 u8 vport_number[0x10]; 7919 7920 u8 reserved_at_60[0x20]; 7921 7922 u8 table_type[0x8]; 7923 u8 reserved_at_88[0x18]; 7924 7925 u8 reserved_at_a0[0x8]; 7926 u8 table_id[0x18]; 7927 7928 u8 reserved_at_c0[0x40]; 7929 7930 u8 flow_index[0x20]; 7931 7932 u8 reserved_at_120[0xe0]; 7933 }; 7934 7935 struct mlx5_ifc_dealloc_xrcd_out_bits { 7936 u8 status[0x8]; 7937 u8 reserved_at_8[0x18]; 7938 7939 u8 syndrome[0x20]; 7940 7941 u8 reserved_at_40[0x40]; 7942 }; 7943 7944 struct mlx5_ifc_dealloc_xrcd_in_bits { 7945 u8 opcode[0x10]; 7946 u8 uid[0x10]; 7947 7948 u8 reserved_at_20[0x10]; 7949 u8 op_mod[0x10]; 7950 7951 u8 reserved_at_40[0x8]; 7952 u8 xrcd[0x18]; 7953 7954 u8 reserved_at_60[0x20]; 7955 }; 7956 7957 struct mlx5_ifc_dealloc_uar_out_bits { 7958 u8 status[0x8]; 7959 u8 reserved_at_8[0x18]; 7960 7961 u8 syndrome[0x20]; 7962 7963 u8 reserved_at_40[0x40]; 7964 }; 7965 7966 struct mlx5_ifc_dealloc_uar_in_bits { 7967 u8 opcode[0x10]; 7968 u8 uid[0x10]; 7969 7970 u8 reserved_at_20[0x10]; 7971 u8 op_mod[0x10]; 7972 7973 u8 reserved_at_40[0x8]; 7974 u8 uar[0x18]; 7975 7976 u8 reserved_at_60[0x20]; 7977 }; 7978 7979 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7980 u8 status[0x8]; 7981 u8 reserved_at_8[0x18]; 7982 7983 u8 syndrome[0x20]; 7984 7985 u8 reserved_at_40[0x40]; 7986 }; 7987 7988 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7989 u8 opcode[0x10]; 7990 u8 uid[0x10]; 7991 7992 u8 reserved_at_20[0x10]; 7993 u8 op_mod[0x10]; 7994 7995 u8 reserved_at_40[0x8]; 7996 u8 transport_domain[0x18]; 7997 7998 u8 reserved_at_60[0x20]; 7999 }; 8000 8001 struct mlx5_ifc_dealloc_q_counter_out_bits { 8002 u8 status[0x8]; 8003 u8 reserved_at_8[0x18]; 8004 8005 u8 syndrome[0x20]; 8006 8007 u8 reserved_at_40[0x40]; 8008 }; 8009 8010 struct mlx5_ifc_dealloc_q_counter_in_bits { 8011 u8 opcode[0x10]; 8012 u8 reserved_at_10[0x10]; 8013 8014 u8 reserved_at_20[0x10]; 8015 u8 op_mod[0x10]; 8016 8017 u8 reserved_at_40[0x18]; 8018 u8 counter_set_id[0x8]; 8019 8020 u8 reserved_at_60[0x20]; 8021 }; 8022 8023 struct mlx5_ifc_dealloc_pd_out_bits { 8024 u8 status[0x8]; 8025 u8 reserved_at_8[0x18]; 8026 8027 u8 syndrome[0x20]; 8028 8029 u8 reserved_at_40[0x40]; 8030 }; 8031 8032 struct mlx5_ifc_dealloc_pd_in_bits { 8033 u8 opcode[0x10]; 8034 u8 uid[0x10]; 8035 8036 u8 reserved_at_20[0x10]; 8037 u8 op_mod[0x10]; 8038 8039 u8 reserved_at_40[0x8]; 8040 u8 pd[0x18]; 8041 8042 u8 reserved_at_60[0x20]; 8043 }; 8044 8045 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8046 u8 status[0x8]; 8047 u8 reserved_at_8[0x18]; 8048 8049 u8 syndrome[0x20]; 8050 8051 u8 reserved_at_40[0x40]; 8052 }; 8053 8054 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8055 u8 opcode[0x10]; 8056 u8 reserved_at_10[0x10]; 8057 8058 u8 reserved_at_20[0x10]; 8059 u8 op_mod[0x10]; 8060 8061 u8 flow_counter_id[0x20]; 8062 8063 u8 reserved_at_60[0x20]; 8064 }; 8065 8066 struct mlx5_ifc_create_xrq_out_bits { 8067 u8 status[0x8]; 8068 u8 reserved_at_8[0x18]; 8069 8070 u8 syndrome[0x20]; 8071 8072 u8 reserved_at_40[0x8]; 8073 u8 xrqn[0x18]; 8074 8075 u8 reserved_at_60[0x20]; 8076 }; 8077 8078 struct mlx5_ifc_create_xrq_in_bits { 8079 u8 opcode[0x10]; 8080 u8 uid[0x10]; 8081 8082 u8 reserved_at_20[0x10]; 8083 u8 op_mod[0x10]; 8084 8085 u8 reserved_at_40[0x40]; 8086 8087 struct mlx5_ifc_xrqc_bits xrq_context; 8088 }; 8089 8090 struct mlx5_ifc_create_xrc_srq_out_bits { 8091 u8 status[0x8]; 8092 u8 reserved_at_8[0x18]; 8093 8094 u8 syndrome[0x20]; 8095 8096 u8 reserved_at_40[0x8]; 8097 u8 xrc_srqn[0x18]; 8098 8099 u8 reserved_at_60[0x20]; 8100 }; 8101 8102 struct mlx5_ifc_create_xrc_srq_in_bits { 8103 u8 opcode[0x10]; 8104 u8 uid[0x10]; 8105 8106 u8 reserved_at_20[0x10]; 8107 u8 op_mod[0x10]; 8108 8109 u8 reserved_at_40[0x40]; 8110 8111 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8112 8113 u8 reserved_at_280[0x60]; 8114 8115 u8 xrc_srq_umem_valid[0x1]; 8116 u8 reserved_at_2e1[0x1f]; 8117 8118 u8 reserved_at_300[0x580]; 8119 8120 u8 pas[][0x40]; 8121 }; 8122 8123 struct mlx5_ifc_create_tis_out_bits { 8124 u8 status[0x8]; 8125 u8 reserved_at_8[0x18]; 8126 8127 u8 syndrome[0x20]; 8128 8129 u8 reserved_at_40[0x8]; 8130 u8 tisn[0x18]; 8131 8132 u8 reserved_at_60[0x20]; 8133 }; 8134 8135 struct mlx5_ifc_create_tis_in_bits { 8136 u8 opcode[0x10]; 8137 u8 uid[0x10]; 8138 8139 u8 reserved_at_20[0x10]; 8140 u8 op_mod[0x10]; 8141 8142 u8 reserved_at_40[0xc0]; 8143 8144 struct mlx5_ifc_tisc_bits ctx; 8145 }; 8146 8147 struct mlx5_ifc_create_tir_out_bits { 8148 u8 status[0x8]; 8149 u8 icm_address_63_40[0x18]; 8150 8151 u8 syndrome[0x20]; 8152 8153 u8 icm_address_39_32[0x8]; 8154 u8 tirn[0x18]; 8155 8156 u8 icm_address_31_0[0x20]; 8157 }; 8158 8159 struct mlx5_ifc_create_tir_in_bits { 8160 u8 opcode[0x10]; 8161 u8 uid[0x10]; 8162 8163 u8 reserved_at_20[0x10]; 8164 u8 op_mod[0x10]; 8165 8166 u8 reserved_at_40[0xc0]; 8167 8168 struct mlx5_ifc_tirc_bits ctx; 8169 }; 8170 8171 struct mlx5_ifc_create_srq_out_bits { 8172 u8 status[0x8]; 8173 u8 reserved_at_8[0x18]; 8174 8175 u8 syndrome[0x20]; 8176 8177 u8 reserved_at_40[0x8]; 8178 u8 srqn[0x18]; 8179 8180 u8 reserved_at_60[0x20]; 8181 }; 8182 8183 struct mlx5_ifc_create_srq_in_bits { 8184 u8 opcode[0x10]; 8185 u8 uid[0x10]; 8186 8187 u8 reserved_at_20[0x10]; 8188 u8 op_mod[0x10]; 8189 8190 u8 reserved_at_40[0x40]; 8191 8192 struct mlx5_ifc_srqc_bits srq_context_entry; 8193 8194 u8 reserved_at_280[0x600]; 8195 8196 u8 pas[][0x40]; 8197 }; 8198 8199 struct mlx5_ifc_create_sq_out_bits { 8200 u8 status[0x8]; 8201 u8 reserved_at_8[0x18]; 8202 8203 u8 syndrome[0x20]; 8204 8205 u8 reserved_at_40[0x8]; 8206 u8 sqn[0x18]; 8207 8208 u8 reserved_at_60[0x20]; 8209 }; 8210 8211 struct mlx5_ifc_create_sq_in_bits { 8212 u8 opcode[0x10]; 8213 u8 uid[0x10]; 8214 8215 u8 reserved_at_20[0x10]; 8216 u8 op_mod[0x10]; 8217 8218 u8 reserved_at_40[0xc0]; 8219 8220 struct mlx5_ifc_sqc_bits ctx; 8221 }; 8222 8223 struct mlx5_ifc_create_scheduling_element_out_bits { 8224 u8 status[0x8]; 8225 u8 reserved_at_8[0x18]; 8226 8227 u8 syndrome[0x20]; 8228 8229 u8 reserved_at_40[0x40]; 8230 8231 u8 scheduling_element_id[0x20]; 8232 8233 u8 reserved_at_a0[0x160]; 8234 }; 8235 8236 struct mlx5_ifc_create_scheduling_element_in_bits { 8237 u8 opcode[0x10]; 8238 u8 reserved_at_10[0x10]; 8239 8240 u8 reserved_at_20[0x10]; 8241 u8 op_mod[0x10]; 8242 8243 u8 scheduling_hierarchy[0x8]; 8244 u8 reserved_at_48[0x18]; 8245 8246 u8 reserved_at_60[0xa0]; 8247 8248 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8249 8250 u8 reserved_at_300[0x100]; 8251 }; 8252 8253 struct mlx5_ifc_create_rqt_out_bits { 8254 u8 status[0x8]; 8255 u8 reserved_at_8[0x18]; 8256 8257 u8 syndrome[0x20]; 8258 8259 u8 reserved_at_40[0x8]; 8260 u8 rqtn[0x18]; 8261 8262 u8 reserved_at_60[0x20]; 8263 }; 8264 8265 struct mlx5_ifc_create_rqt_in_bits { 8266 u8 opcode[0x10]; 8267 u8 uid[0x10]; 8268 8269 u8 reserved_at_20[0x10]; 8270 u8 op_mod[0x10]; 8271 8272 u8 reserved_at_40[0xc0]; 8273 8274 struct mlx5_ifc_rqtc_bits rqt_context; 8275 }; 8276 8277 struct mlx5_ifc_create_rq_out_bits { 8278 u8 status[0x8]; 8279 u8 reserved_at_8[0x18]; 8280 8281 u8 syndrome[0x20]; 8282 8283 u8 reserved_at_40[0x8]; 8284 u8 rqn[0x18]; 8285 8286 u8 reserved_at_60[0x20]; 8287 }; 8288 8289 struct mlx5_ifc_create_rq_in_bits { 8290 u8 opcode[0x10]; 8291 u8 uid[0x10]; 8292 8293 u8 reserved_at_20[0x10]; 8294 u8 op_mod[0x10]; 8295 8296 u8 reserved_at_40[0xc0]; 8297 8298 struct mlx5_ifc_rqc_bits ctx; 8299 }; 8300 8301 struct mlx5_ifc_create_rmp_out_bits { 8302 u8 status[0x8]; 8303 u8 reserved_at_8[0x18]; 8304 8305 u8 syndrome[0x20]; 8306 8307 u8 reserved_at_40[0x8]; 8308 u8 rmpn[0x18]; 8309 8310 u8 reserved_at_60[0x20]; 8311 }; 8312 8313 struct mlx5_ifc_create_rmp_in_bits { 8314 u8 opcode[0x10]; 8315 u8 uid[0x10]; 8316 8317 u8 reserved_at_20[0x10]; 8318 u8 op_mod[0x10]; 8319 8320 u8 reserved_at_40[0xc0]; 8321 8322 struct mlx5_ifc_rmpc_bits ctx; 8323 }; 8324 8325 struct mlx5_ifc_create_qp_out_bits { 8326 u8 status[0x8]; 8327 u8 reserved_at_8[0x18]; 8328 8329 u8 syndrome[0x20]; 8330 8331 u8 reserved_at_40[0x8]; 8332 u8 qpn[0x18]; 8333 8334 u8 ece[0x20]; 8335 }; 8336 8337 struct mlx5_ifc_create_qp_in_bits { 8338 u8 opcode[0x10]; 8339 u8 uid[0x10]; 8340 8341 u8 reserved_at_20[0x10]; 8342 u8 op_mod[0x10]; 8343 8344 u8 reserved_at_40[0x8]; 8345 u8 input_qpn[0x18]; 8346 8347 u8 reserved_at_60[0x20]; 8348 u8 opt_param_mask[0x20]; 8349 8350 u8 ece[0x20]; 8351 8352 struct mlx5_ifc_qpc_bits qpc; 8353 8354 u8 reserved_at_800[0x60]; 8355 8356 u8 wq_umem_valid[0x1]; 8357 u8 reserved_at_861[0x1f]; 8358 8359 u8 pas[][0x40]; 8360 }; 8361 8362 struct mlx5_ifc_create_psv_out_bits { 8363 u8 status[0x8]; 8364 u8 reserved_at_8[0x18]; 8365 8366 u8 syndrome[0x20]; 8367 8368 u8 reserved_at_40[0x40]; 8369 8370 u8 reserved_at_80[0x8]; 8371 u8 psv0_index[0x18]; 8372 8373 u8 reserved_at_a0[0x8]; 8374 u8 psv1_index[0x18]; 8375 8376 u8 reserved_at_c0[0x8]; 8377 u8 psv2_index[0x18]; 8378 8379 u8 reserved_at_e0[0x8]; 8380 u8 psv3_index[0x18]; 8381 }; 8382 8383 struct mlx5_ifc_create_psv_in_bits { 8384 u8 opcode[0x10]; 8385 u8 reserved_at_10[0x10]; 8386 8387 u8 reserved_at_20[0x10]; 8388 u8 op_mod[0x10]; 8389 8390 u8 num_psv[0x4]; 8391 u8 reserved_at_44[0x4]; 8392 u8 pd[0x18]; 8393 8394 u8 reserved_at_60[0x20]; 8395 }; 8396 8397 struct mlx5_ifc_create_mkey_out_bits { 8398 u8 status[0x8]; 8399 u8 reserved_at_8[0x18]; 8400 8401 u8 syndrome[0x20]; 8402 8403 u8 reserved_at_40[0x8]; 8404 u8 mkey_index[0x18]; 8405 8406 u8 reserved_at_60[0x20]; 8407 }; 8408 8409 struct mlx5_ifc_create_mkey_in_bits { 8410 u8 opcode[0x10]; 8411 u8 uid[0x10]; 8412 8413 u8 reserved_at_20[0x10]; 8414 u8 op_mod[0x10]; 8415 8416 u8 reserved_at_40[0x20]; 8417 8418 u8 pg_access[0x1]; 8419 u8 mkey_umem_valid[0x1]; 8420 u8 reserved_at_62[0x1e]; 8421 8422 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8423 8424 u8 reserved_at_280[0x80]; 8425 8426 u8 translations_octword_actual_size[0x20]; 8427 8428 u8 reserved_at_320[0x560]; 8429 8430 u8 klm_pas_mtt[][0x20]; 8431 }; 8432 8433 enum { 8434 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8435 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8436 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8437 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8438 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8439 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8440 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8441 }; 8442 8443 struct mlx5_ifc_create_flow_table_out_bits { 8444 u8 status[0x8]; 8445 u8 icm_address_63_40[0x18]; 8446 8447 u8 syndrome[0x20]; 8448 8449 u8 icm_address_39_32[0x8]; 8450 u8 table_id[0x18]; 8451 8452 u8 icm_address_31_0[0x20]; 8453 }; 8454 8455 struct mlx5_ifc_create_flow_table_in_bits { 8456 u8 opcode[0x10]; 8457 u8 reserved_at_10[0x10]; 8458 8459 u8 reserved_at_20[0x10]; 8460 u8 op_mod[0x10]; 8461 8462 u8 other_vport[0x1]; 8463 u8 reserved_at_41[0xf]; 8464 u8 vport_number[0x10]; 8465 8466 u8 reserved_at_60[0x20]; 8467 8468 u8 table_type[0x8]; 8469 u8 reserved_at_88[0x18]; 8470 8471 u8 reserved_at_a0[0x20]; 8472 8473 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8474 }; 8475 8476 struct mlx5_ifc_create_flow_group_out_bits { 8477 u8 status[0x8]; 8478 u8 reserved_at_8[0x18]; 8479 8480 u8 syndrome[0x20]; 8481 8482 u8 reserved_at_40[0x8]; 8483 u8 group_id[0x18]; 8484 8485 u8 reserved_at_60[0x20]; 8486 }; 8487 8488 enum { 8489 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8490 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8491 }; 8492 8493 enum { 8494 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8495 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8496 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8497 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8498 }; 8499 8500 struct mlx5_ifc_create_flow_group_in_bits { 8501 u8 opcode[0x10]; 8502 u8 reserved_at_10[0x10]; 8503 8504 u8 reserved_at_20[0x10]; 8505 u8 op_mod[0x10]; 8506 8507 u8 other_vport[0x1]; 8508 u8 reserved_at_41[0xf]; 8509 u8 vport_number[0x10]; 8510 8511 u8 reserved_at_60[0x20]; 8512 8513 u8 table_type[0x8]; 8514 u8 reserved_at_88[0x4]; 8515 u8 group_type[0x4]; 8516 u8 reserved_at_90[0x10]; 8517 8518 u8 reserved_at_a0[0x8]; 8519 u8 table_id[0x18]; 8520 8521 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8522 8523 u8 reserved_at_c1[0x1f]; 8524 8525 u8 start_flow_index[0x20]; 8526 8527 u8 reserved_at_100[0x20]; 8528 8529 u8 end_flow_index[0x20]; 8530 8531 u8 reserved_at_140[0x10]; 8532 u8 match_definer_id[0x10]; 8533 8534 u8 reserved_at_160[0x80]; 8535 8536 u8 reserved_at_1e0[0x18]; 8537 u8 match_criteria_enable[0x8]; 8538 8539 struct mlx5_ifc_fte_match_param_bits match_criteria; 8540 8541 u8 reserved_at_1200[0xe00]; 8542 }; 8543 8544 struct mlx5_ifc_create_eq_out_bits { 8545 u8 status[0x8]; 8546 u8 reserved_at_8[0x18]; 8547 8548 u8 syndrome[0x20]; 8549 8550 u8 reserved_at_40[0x18]; 8551 u8 eq_number[0x8]; 8552 8553 u8 reserved_at_60[0x20]; 8554 }; 8555 8556 struct mlx5_ifc_create_eq_in_bits { 8557 u8 opcode[0x10]; 8558 u8 uid[0x10]; 8559 8560 u8 reserved_at_20[0x10]; 8561 u8 op_mod[0x10]; 8562 8563 u8 reserved_at_40[0x40]; 8564 8565 struct mlx5_ifc_eqc_bits eq_context_entry; 8566 8567 u8 reserved_at_280[0x40]; 8568 8569 u8 event_bitmask[4][0x40]; 8570 8571 u8 reserved_at_3c0[0x4c0]; 8572 8573 u8 pas[][0x40]; 8574 }; 8575 8576 struct mlx5_ifc_create_dct_out_bits { 8577 u8 status[0x8]; 8578 u8 reserved_at_8[0x18]; 8579 8580 u8 syndrome[0x20]; 8581 8582 u8 reserved_at_40[0x8]; 8583 u8 dctn[0x18]; 8584 8585 u8 ece[0x20]; 8586 }; 8587 8588 struct mlx5_ifc_create_dct_in_bits { 8589 u8 opcode[0x10]; 8590 u8 uid[0x10]; 8591 8592 u8 reserved_at_20[0x10]; 8593 u8 op_mod[0x10]; 8594 8595 u8 reserved_at_40[0x40]; 8596 8597 struct mlx5_ifc_dctc_bits dct_context_entry; 8598 8599 u8 reserved_at_280[0x180]; 8600 }; 8601 8602 struct mlx5_ifc_create_cq_out_bits { 8603 u8 status[0x8]; 8604 u8 reserved_at_8[0x18]; 8605 8606 u8 syndrome[0x20]; 8607 8608 u8 reserved_at_40[0x8]; 8609 u8 cqn[0x18]; 8610 8611 u8 reserved_at_60[0x20]; 8612 }; 8613 8614 struct mlx5_ifc_create_cq_in_bits { 8615 u8 opcode[0x10]; 8616 u8 uid[0x10]; 8617 8618 u8 reserved_at_20[0x10]; 8619 u8 op_mod[0x10]; 8620 8621 u8 reserved_at_40[0x40]; 8622 8623 struct mlx5_ifc_cqc_bits cq_context; 8624 8625 u8 reserved_at_280[0x60]; 8626 8627 u8 cq_umem_valid[0x1]; 8628 u8 reserved_at_2e1[0x59f]; 8629 8630 u8 pas[][0x40]; 8631 }; 8632 8633 struct mlx5_ifc_config_int_moderation_out_bits { 8634 u8 status[0x8]; 8635 u8 reserved_at_8[0x18]; 8636 8637 u8 syndrome[0x20]; 8638 8639 u8 reserved_at_40[0x4]; 8640 u8 min_delay[0xc]; 8641 u8 int_vector[0x10]; 8642 8643 u8 reserved_at_60[0x20]; 8644 }; 8645 8646 enum { 8647 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8648 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8649 }; 8650 8651 struct mlx5_ifc_config_int_moderation_in_bits { 8652 u8 opcode[0x10]; 8653 u8 reserved_at_10[0x10]; 8654 8655 u8 reserved_at_20[0x10]; 8656 u8 op_mod[0x10]; 8657 8658 u8 reserved_at_40[0x4]; 8659 u8 min_delay[0xc]; 8660 u8 int_vector[0x10]; 8661 8662 u8 reserved_at_60[0x20]; 8663 }; 8664 8665 struct mlx5_ifc_attach_to_mcg_out_bits { 8666 u8 status[0x8]; 8667 u8 reserved_at_8[0x18]; 8668 8669 u8 syndrome[0x20]; 8670 8671 u8 reserved_at_40[0x40]; 8672 }; 8673 8674 struct mlx5_ifc_attach_to_mcg_in_bits { 8675 u8 opcode[0x10]; 8676 u8 uid[0x10]; 8677 8678 u8 reserved_at_20[0x10]; 8679 u8 op_mod[0x10]; 8680 8681 u8 reserved_at_40[0x8]; 8682 u8 qpn[0x18]; 8683 8684 u8 reserved_at_60[0x20]; 8685 8686 u8 multicast_gid[16][0x8]; 8687 }; 8688 8689 struct mlx5_ifc_arm_xrq_out_bits { 8690 u8 status[0x8]; 8691 u8 reserved_at_8[0x18]; 8692 8693 u8 syndrome[0x20]; 8694 8695 u8 reserved_at_40[0x40]; 8696 }; 8697 8698 struct mlx5_ifc_arm_xrq_in_bits { 8699 u8 opcode[0x10]; 8700 u8 reserved_at_10[0x10]; 8701 8702 u8 reserved_at_20[0x10]; 8703 u8 op_mod[0x10]; 8704 8705 u8 reserved_at_40[0x8]; 8706 u8 xrqn[0x18]; 8707 8708 u8 reserved_at_60[0x10]; 8709 u8 lwm[0x10]; 8710 }; 8711 8712 struct mlx5_ifc_arm_xrc_srq_out_bits { 8713 u8 status[0x8]; 8714 u8 reserved_at_8[0x18]; 8715 8716 u8 syndrome[0x20]; 8717 8718 u8 reserved_at_40[0x40]; 8719 }; 8720 8721 enum { 8722 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8723 }; 8724 8725 struct mlx5_ifc_arm_xrc_srq_in_bits { 8726 u8 opcode[0x10]; 8727 u8 uid[0x10]; 8728 8729 u8 reserved_at_20[0x10]; 8730 u8 op_mod[0x10]; 8731 8732 u8 reserved_at_40[0x8]; 8733 u8 xrc_srqn[0x18]; 8734 8735 u8 reserved_at_60[0x10]; 8736 u8 lwm[0x10]; 8737 }; 8738 8739 struct mlx5_ifc_arm_rq_out_bits { 8740 u8 status[0x8]; 8741 u8 reserved_at_8[0x18]; 8742 8743 u8 syndrome[0x20]; 8744 8745 u8 reserved_at_40[0x40]; 8746 }; 8747 8748 enum { 8749 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8750 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8751 }; 8752 8753 struct mlx5_ifc_arm_rq_in_bits { 8754 u8 opcode[0x10]; 8755 u8 uid[0x10]; 8756 8757 u8 reserved_at_20[0x10]; 8758 u8 op_mod[0x10]; 8759 8760 u8 reserved_at_40[0x8]; 8761 u8 srq_number[0x18]; 8762 8763 u8 reserved_at_60[0x10]; 8764 u8 lwm[0x10]; 8765 }; 8766 8767 struct mlx5_ifc_arm_dct_out_bits { 8768 u8 status[0x8]; 8769 u8 reserved_at_8[0x18]; 8770 8771 u8 syndrome[0x20]; 8772 8773 u8 reserved_at_40[0x40]; 8774 }; 8775 8776 struct mlx5_ifc_arm_dct_in_bits { 8777 u8 opcode[0x10]; 8778 u8 reserved_at_10[0x10]; 8779 8780 u8 reserved_at_20[0x10]; 8781 u8 op_mod[0x10]; 8782 8783 u8 reserved_at_40[0x8]; 8784 u8 dct_number[0x18]; 8785 8786 u8 reserved_at_60[0x20]; 8787 }; 8788 8789 struct mlx5_ifc_alloc_xrcd_out_bits { 8790 u8 status[0x8]; 8791 u8 reserved_at_8[0x18]; 8792 8793 u8 syndrome[0x20]; 8794 8795 u8 reserved_at_40[0x8]; 8796 u8 xrcd[0x18]; 8797 8798 u8 reserved_at_60[0x20]; 8799 }; 8800 8801 struct mlx5_ifc_alloc_xrcd_in_bits { 8802 u8 opcode[0x10]; 8803 u8 uid[0x10]; 8804 8805 u8 reserved_at_20[0x10]; 8806 u8 op_mod[0x10]; 8807 8808 u8 reserved_at_40[0x40]; 8809 }; 8810 8811 struct mlx5_ifc_alloc_uar_out_bits { 8812 u8 status[0x8]; 8813 u8 reserved_at_8[0x18]; 8814 8815 u8 syndrome[0x20]; 8816 8817 u8 reserved_at_40[0x8]; 8818 u8 uar[0x18]; 8819 8820 u8 reserved_at_60[0x20]; 8821 }; 8822 8823 struct mlx5_ifc_alloc_uar_in_bits { 8824 u8 opcode[0x10]; 8825 u8 uid[0x10]; 8826 8827 u8 reserved_at_20[0x10]; 8828 u8 op_mod[0x10]; 8829 8830 u8 reserved_at_40[0x40]; 8831 }; 8832 8833 struct mlx5_ifc_alloc_transport_domain_out_bits { 8834 u8 status[0x8]; 8835 u8 reserved_at_8[0x18]; 8836 8837 u8 syndrome[0x20]; 8838 8839 u8 reserved_at_40[0x8]; 8840 u8 transport_domain[0x18]; 8841 8842 u8 reserved_at_60[0x20]; 8843 }; 8844 8845 struct mlx5_ifc_alloc_transport_domain_in_bits { 8846 u8 opcode[0x10]; 8847 u8 uid[0x10]; 8848 8849 u8 reserved_at_20[0x10]; 8850 u8 op_mod[0x10]; 8851 8852 u8 reserved_at_40[0x40]; 8853 }; 8854 8855 struct mlx5_ifc_alloc_q_counter_out_bits { 8856 u8 status[0x8]; 8857 u8 reserved_at_8[0x18]; 8858 8859 u8 syndrome[0x20]; 8860 8861 u8 reserved_at_40[0x18]; 8862 u8 counter_set_id[0x8]; 8863 8864 u8 reserved_at_60[0x20]; 8865 }; 8866 8867 struct mlx5_ifc_alloc_q_counter_in_bits { 8868 u8 opcode[0x10]; 8869 u8 uid[0x10]; 8870 8871 u8 reserved_at_20[0x10]; 8872 u8 op_mod[0x10]; 8873 8874 u8 reserved_at_40[0x40]; 8875 }; 8876 8877 struct mlx5_ifc_alloc_pd_out_bits { 8878 u8 status[0x8]; 8879 u8 reserved_at_8[0x18]; 8880 8881 u8 syndrome[0x20]; 8882 8883 u8 reserved_at_40[0x8]; 8884 u8 pd[0x18]; 8885 8886 u8 reserved_at_60[0x20]; 8887 }; 8888 8889 struct mlx5_ifc_alloc_pd_in_bits { 8890 u8 opcode[0x10]; 8891 u8 uid[0x10]; 8892 8893 u8 reserved_at_20[0x10]; 8894 u8 op_mod[0x10]; 8895 8896 u8 reserved_at_40[0x40]; 8897 }; 8898 8899 struct mlx5_ifc_alloc_flow_counter_out_bits { 8900 u8 status[0x8]; 8901 u8 reserved_at_8[0x18]; 8902 8903 u8 syndrome[0x20]; 8904 8905 u8 flow_counter_id[0x20]; 8906 8907 u8 reserved_at_60[0x20]; 8908 }; 8909 8910 struct mlx5_ifc_alloc_flow_counter_in_bits { 8911 u8 opcode[0x10]; 8912 u8 reserved_at_10[0x10]; 8913 8914 u8 reserved_at_20[0x10]; 8915 u8 op_mod[0x10]; 8916 8917 u8 reserved_at_40[0x38]; 8918 u8 flow_counter_bulk[0x8]; 8919 }; 8920 8921 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8922 u8 status[0x8]; 8923 u8 reserved_at_8[0x18]; 8924 8925 u8 syndrome[0x20]; 8926 8927 u8 reserved_at_40[0x40]; 8928 }; 8929 8930 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8931 u8 opcode[0x10]; 8932 u8 reserved_at_10[0x10]; 8933 8934 u8 reserved_at_20[0x10]; 8935 u8 op_mod[0x10]; 8936 8937 u8 reserved_at_40[0x20]; 8938 8939 u8 reserved_at_60[0x10]; 8940 u8 vxlan_udp_port[0x10]; 8941 }; 8942 8943 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8944 u8 status[0x8]; 8945 u8 reserved_at_8[0x18]; 8946 8947 u8 syndrome[0x20]; 8948 8949 u8 reserved_at_40[0x40]; 8950 }; 8951 8952 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8953 u8 rate_limit[0x20]; 8954 8955 u8 burst_upper_bound[0x20]; 8956 8957 u8 reserved_at_40[0x10]; 8958 u8 typical_packet_size[0x10]; 8959 8960 u8 reserved_at_60[0x120]; 8961 }; 8962 8963 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8964 u8 opcode[0x10]; 8965 u8 uid[0x10]; 8966 8967 u8 reserved_at_20[0x10]; 8968 u8 op_mod[0x10]; 8969 8970 u8 reserved_at_40[0x10]; 8971 u8 rate_limit_index[0x10]; 8972 8973 u8 reserved_at_60[0x20]; 8974 8975 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8976 }; 8977 8978 struct mlx5_ifc_access_register_out_bits { 8979 u8 status[0x8]; 8980 u8 reserved_at_8[0x18]; 8981 8982 u8 syndrome[0x20]; 8983 8984 u8 reserved_at_40[0x40]; 8985 8986 u8 register_data[][0x20]; 8987 }; 8988 8989 enum { 8990 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8991 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8992 }; 8993 8994 struct mlx5_ifc_access_register_in_bits { 8995 u8 opcode[0x10]; 8996 u8 reserved_at_10[0x10]; 8997 8998 u8 reserved_at_20[0x10]; 8999 u8 op_mod[0x10]; 9000 9001 u8 reserved_at_40[0x10]; 9002 u8 register_id[0x10]; 9003 9004 u8 argument[0x20]; 9005 9006 u8 register_data[][0x20]; 9007 }; 9008 9009 struct mlx5_ifc_sltp_reg_bits { 9010 u8 status[0x4]; 9011 u8 version[0x4]; 9012 u8 local_port[0x8]; 9013 u8 pnat[0x2]; 9014 u8 reserved_at_12[0x2]; 9015 u8 lane[0x4]; 9016 u8 reserved_at_18[0x8]; 9017 9018 u8 reserved_at_20[0x20]; 9019 9020 u8 reserved_at_40[0x7]; 9021 u8 polarity[0x1]; 9022 u8 ob_tap0[0x8]; 9023 u8 ob_tap1[0x8]; 9024 u8 ob_tap2[0x8]; 9025 9026 u8 reserved_at_60[0xc]; 9027 u8 ob_preemp_mode[0x4]; 9028 u8 ob_reg[0x8]; 9029 u8 ob_bias[0x8]; 9030 9031 u8 reserved_at_80[0x20]; 9032 }; 9033 9034 struct mlx5_ifc_slrg_reg_bits { 9035 u8 status[0x4]; 9036 u8 version[0x4]; 9037 u8 local_port[0x8]; 9038 u8 pnat[0x2]; 9039 u8 reserved_at_12[0x2]; 9040 u8 lane[0x4]; 9041 u8 reserved_at_18[0x8]; 9042 9043 u8 time_to_link_up[0x10]; 9044 u8 reserved_at_30[0xc]; 9045 u8 grade_lane_speed[0x4]; 9046 9047 u8 grade_version[0x8]; 9048 u8 grade[0x18]; 9049 9050 u8 reserved_at_60[0x4]; 9051 u8 height_grade_type[0x4]; 9052 u8 height_grade[0x18]; 9053 9054 u8 height_dz[0x10]; 9055 u8 height_dv[0x10]; 9056 9057 u8 reserved_at_a0[0x10]; 9058 u8 height_sigma[0x10]; 9059 9060 u8 reserved_at_c0[0x20]; 9061 9062 u8 reserved_at_e0[0x4]; 9063 u8 phase_grade_type[0x4]; 9064 u8 phase_grade[0x18]; 9065 9066 u8 reserved_at_100[0x8]; 9067 u8 phase_eo_pos[0x8]; 9068 u8 reserved_at_110[0x8]; 9069 u8 phase_eo_neg[0x8]; 9070 9071 u8 ffe_set_tested[0x10]; 9072 u8 test_errors_per_lane[0x10]; 9073 }; 9074 9075 struct mlx5_ifc_pvlc_reg_bits { 9076 u8 reserved_at_0[0x8]; 9077 u8 local_port[0x8]; 9078 u8 reserved_at_10[0x10]; 9079 9080 u8 reserved_at_20[0x1c]; 9081 u8 vl_hw_cap[0x4]; 9082 9083 u8 reserved_at_40[0x1c]; 9084 u8 vl_admin[0x4]; 9085 9086 u8 reserved_at_60[0x1c]; 9087 u8 vl_operational[0x4]; 9088 }; 9089 9090 struct mlx5_ifc_pude_reg_bits { 9091 u8 swid[0x8]; 9092 u8 local_port[0x8]; 9093 u8 reserved_at_10[0x4]; 9094 u8 admin_status[0x4]; 9095 u8 reserved_at_18[0x4]; 9096 u8 oper_status[0x4]; 9097 9098 u8 reserved_at_20[0x60]; 9099 }; 9100 9101 struct mlx5_ifc_ptys_reg_bits { 9102 u8 reserved_at_0[0x1]; 9103 u8 an_disable_admin[0x1]; 9104 u8 an_disable_cap[0x1]; 9105 u8 reserved_at_3[0x5]; 9106 u8 local_port[0x8]; 9107 u8 reserved_at_10[0xd]; 9108 u8 proto_mask[0x3]; 9109 9110 u8 an_status[0x4]; 9111 u8 reserved_at_24[0xc]; 9112 u8 data_rate_oper[0x10]; 9113 9114 u8 ext_eth_proto_capability[0x20]; 9115 9116 u8 eth_proto_capability[0x20]; 9117 9118 u8 ib_link_width_capability[0x10]; 9119 u8 ib_proto_capability[0x10]; 9120 9121 u8 ext_eth_proto_admin[0x20]; 9122 9123 u8 eth_proto_admin[0x20]; 9124 9125 u8 ib_link_width_admin[0x10]; 9126 u8 ib_proto_admin[0x10]; 9127 9128 u8 ext_eth_proto_oper[0x20]; 9129 9130 u8 eth_proto_oper[0x20]; 9131 9132 u8 ib_link_width_oper[0x10]; 9133 u8 ib_proto_oper[0x10]; 9134 9135 u8 reserved_at_160[0x1c]; 9136 u8 connector_type[0x4]; 9137 9138 u8 eth_proto_lp_advertise[0x20]; 9139 9140 u8 reserved_at_1a0[0x60]; 9141 }; 9142 9143 struct mlx5_ifc_mlcr_reg_bits { 9144 u8 reserved_at_0[0x8]; 9145 u8 local_port[0x8]; 9146 u8 reserved_at_10[0x20]; 9147 9148 u8 beacon_duration[0x10]; 9149 u8 reserved_at_40[0x10]; 9150 9151 u8 beacon_remain[0x10]; 9152 }; 9153 9154 struct mlx5_ifc_ptas_reg_bits { 9155 u8 reserved_at_0[0x20]; 9156 9157 u8 algorithm_options[0x10]; 9158 u8 reserved_at_30[0x4]; 9159 u8 repetitions_mode[0x4]; 9160 u8 num_of_repetitions[0x8]; 9161 9162 u8 grade_version[0x8]; 9163 u8 height_grade_type[0x4]; 9164 u8 phase_grade_type[0x4]; 9165 u8 height_grade_weight[0x8]; 9166 u8 phase_grade_weight[0x8]; 9167 9168 u8 gisim_measure_bits[0x10]; 9169 u8 adaptive_tap_measure_bits[0x10]; 9170 9171 u8 ber_bath_high_error_threshold[0x10]; 9172 u8 ber_bath_mid_error_threshold[0x10]; 9173 9174 u8 ber_bath_low_error_threshold[0x10]; 9175 u8 one_ratio_high_threshold[0x10]; 9176 9177 u8 one_ratio_high_mid_threshold[0x10]; 9178 u8 one_ratio_low_mid_threshold[0x10]; 9179 9180 u8 one_ratio_low_threshold[0x10]; 9181 u8 ndeo_error_threshold[0x10]; 9182 9183 u8 mixer_offset_step_size[0x10]; 9184 u8 reserved_at_110[0x8]; 9185 u8 mix90_phase_for_voltage_bath[0x8]; 9186 9187 u8 mixer_offset_start[0x10]; 9188 u8 mixer_offset_end[0x10]; 9189 9190 u8 reserved_at_140[0x15]; 9191 u8 ber_test_time[0xb]; 9192 }; 9193 9194 struct mlx5_ifc_pspa_reg_bits { 9195 u8 swid[0x8]; 9196 u8 local_port[0x8]; 9197 u8 sub_port[0x8]; 9198 u8 reserved_at_18[0x8]; 9199 9200 u8 reserved_at_20[0x20]; 9201 }; 9202 9203 struct mlx5_ifc_pqdr_reg_bits { 9204 u8 reserved_at_0[0x8]; 9205 u8 local_port[0x8]; 9206 u8 reserved_at_10[0x5]; 9207 u8 prio[0x3]; 9208 u8 reserved_at_18[0x6]; 9209 u8 mode[0x2]; 9210 9211 u8 reserved_at_20[0x20]; 9212 9213 u8 reserved_at_40[0x10]; 9214 u8 min_threshold[0x10]; 9215 9216 u8 reserved_at_60[0x10]; 9217 u8 max_threshold[0x10]; 9218 9219 u8 reserved_at_80[0x10]; 9220 u8 mark_probability_denominator[0x10]; 9221 9222 u8 reserved_at_a0[0x60]; 9223 }; 9224 9225 struct mlx5_ifc_ppsc_reg_bits { 9226 u8 reserved_at_0[0x8]; 9227 u8 local_port[0x8]; 9228 u8 reserved_at_10[0x10]; 9229 9230 u8 reserved_at_20[0x60]; 9231 9232 u8 reserved_at_80[0x1c]; 9233 u8 wrps_admin[0x4]; 9234 9235 u8 reserved_at_a0[0x1c]; 9236 u8 wrps_status[0x4]; 9237 9238 u8 reserved_at_c0[0x8]; 9239 u8 up_threshold[0x8]; 9240 u8 reserved_at_d0[0x8]; 9241 u8 down_threshold[0x8]; 9242 9243 u8 reserved_at_e0[0x20]; 9244 9245 u8 reserved_at_100[0x1c]; 9246 u8 srps_admin[0x4]; 9247 9248 u8 reserved_at_120[0x1c]; 9249 u8 srps_status[0x4]; 9250 9251 u8 reserved_at_140[0x40]; 9252 }; 9253 9254 struct mlx5_ifc_pplr_reg_bits { 9255 u8 reserved_at_0[0x8]; 9256 u8 local_port[0x8]; 9257 u8 reserved_at_10[0x10]; 9258 9259 u8 reserved_at_20[0x8]; 9260 u8 lb_cap[0x8]; 9261 u8 reserved_at_30[0x8]; 9262 u8 lb_en[0x8]; 9263 }; 9264 9265 struct mlx5_ifc_pplm_reg_bits { 9266 u8 reserved_at_0[0x8]; 9267 u8 local_port[0x8]; 9268 u8 reserved_at_10[0x10]; 9269 9270 u8 reserved_at_20[0x20]; 9271 9272 u8 port_profile_mode[0x8]; 9273 u8 static_port_profile[0x8]; 9274 u8 active_port_profile[0x8]; 9275 u8 reserved_at_58[0x8]; 9276 9277 u8 retransmission_active[0x8]; 9278 u8 fec_mode_active[0x18]; 9279 9280 u8 rs_fec_correction_bypass_cap[0x4]; 9281 u8 reserved_at_84[0x8]; 9282 u8 fec_override_cap_56g[0x4]; 9283 u8 fec_override_cap_100g[0x4]; 9284 u8 fec_override_cap_50g[0x4]; 9285 u8 fec_override_cap_25g[0x4]; 9286 u8 fec_override_cap_10g_40g[0x4]; 9287 9288 u8 rs_fec_correction_bypass_admin[0x4]; 9289 u8 reserved_at_a4[0x8]; 9290 u8 fec_override_admin_56g[0x4]; 9291 u8 fec_override_admin_100g[0x4]; 9292 u8 fec_override_admin_50g[0x4]; 9293 u8 fec_override_admin_25g[0x4]; 9294 u8 fec_override_admin_10g_40g[0x4]; 9295 9296 u8 fec_override_cap_400g_8x[0x10]; 9297 u8 fec_override_cap_200g_4x[0x10]; 9298 9299 u8 fec_override_cap_100g_2x[0x10]; 9300 u8 fec_override_cap_50g_1x[0x10]; 9301 9302 u8 fec_override_admin_400g_8x[0x10]; 9303 u8 fec_override_admin_200g_4x[0x10]; 9304 9305 u8 fec_override_admin_100g_2x[0x10]; 9306 u8 fec_override_admin_50g_1x[0x10]; 9307 9308 u8 reserved_at_140[0x140]; 9309 }; 9310 9311 struct mlx5_ifc_ppcnt_reg_bits { 9312 u8 swid[0x8]; 9313 u8 local_port[0x8]; 9314 u8 pnat[0x2]; 9315 u8 reserved_at_12[0x8]; 9316 u8 grp[0x6]; 9317 9318 u8 clr[0x1]; 9319 u8 reserved_at_21[0x1c]; 9320 u8 prio_tc[0x3]; 9321 9322 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9323 }; 9324 9325 struct mlx5_ifc_mpein_reg_bits { 9326 u8 reserved_at_0[0x2]; 9327 u8 depth[0x6]; 9328 u8 pcie_index[0x8]; 9329 u8 node[0x8]; 9330 u8 reserved_at_18[0x8]; 9331 9332 u8 capability_mask[0x20]; 9333 9334 u8 reserved_at_40[0x8]; 9335 u8 link_width_enabled[0x8]; 9336 u8 link_speed_enabled[0x10]; 9337 9338 u8 lane0_physical_position[0x8]; 9339 u8 link_width_active[0x8]; 9340 u8 link_speed_active[0x10]; 9341 9342 u8 num_of_pfs[0x10]; 9343 u8 num_of_vfs[0x10]; 9344 9345 u8 bdf0[0x10]; 9346 u8 reserved_at_b0[0x10]; 9347 9348 u8 max_read_request_size[0x4]; 9349 u8 max_payload_size[0x4]; 9350 u8 reserved_at_c8[0x5]; 9351 u8 pwr_status[0x3]; 9352 u8 port_type[0x4]; 9353 u8 reserved_at_d4[0xb]; 9354 u8 lane_reversal[0x1]; 9355 9356 u8 reserved_at_e0[0x14]; 9357 u8 pci_power[0xc]; 9358 9359 u8 reserved_at_100[0x20]; 9360 9361 u8 device_status[0x10]; 9362 u8 port_state[0x8]; 9363 u8 reserved_at_138[0x8]; 9364 9365 u8 reserved_at_140[0x10]; 9366 u8 receiver_detect_result[0x10]; 9367 9368 u8 reserved_at_160[0x20]; 9369 }; 9370 9371 struct mlx5_ifc_mpcnt_reg_bits { 9372 u8 reserved_at_0[0x8]; 9373 u8 pcie_index[0x8]; 9374 u8 reserved_at_10[0xa]; 9375 u8 grp[0x6]; 9376 9377 u8 clr[0x1]; 9378 u8 reserved_at_21[0x1f]; 9379 9380 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9381 }; 9382 9383 struct mlx5_ifc_ppad_reg_bits { 9384 u8 reserved_at_0[0x3]; 9385 u8 single_mac[0x1]; 9386 u8 reserved_at_4[0x4]; 9387 u8 local_port[0x8]; 9388 u8 mac_47_32[0x10]; 9389 9390 u8 mac_31_0[0x20]; 9391 9392 u8 reserved_at_40[0x40]; 9393 }; 9394 9395 struct mlx5_ifc_pmtu_reg_bits { 9396 u8 reserved_at_0[0x8]; 9397 u8 local_port[0x8]; 9398 u8 reserved_at_10[0x10]; 9399 9400 u8 max_mtu[0x10]; 9401 u8 reserved_at_30[0x10]; 9402 9403 u8 admin_mtu[0x10]; 9404 u8 reserved_at_50[0x10]; 9405 9406 u8 oper_mtu[0x10]; 9407 u8 reserved_at_70[0x10]; 9408 }; 9409 9410 struct mlx5_ifc_pmpr_reg_bits { 9411 u8 reserved_at_0[0x8]; 9412 u8 module[0x8]; 9413 u8 reserved_at_10[0x10]; 9414 9415 u8 reserved_at_20[0x18]; 9416 u8 attenuation_5g[0x8]; 9417 9418 u8 reserved_at_40[0x18]; 9419 u8 attenuation_7g[0x8]; 9420 9421 u8 reserved_at_60[0x18]; 9422 u8 attenuation_12g[0x8]; 9423 }; 9424 9425 struct mlx5_ifc_pmpe_reg_bits { 9426 u8 reserved_at_0[0x8]; 9427 u8 module[0x8]; 9428 u8 reserved_at_10[0xc]; 9429 u8 module_status[0x4]; 9430 9431 u8 reserved_at_20[0x60]; 9432 }; 9433 9434 struct mlx5_ifc_pmpc_reg_bits { 9435 u8 module_state_updated[32][0x8]; 9436 }; 9437 9438 struct mlx5_ifc_pmlpn_reg_bits { 9439 u8 reserved_at_0[0x4]; 9440 u8 mlpn_status[0x4]; 9441 u8 local_port[0x8]; 9442 u8 reserved_at_10[0x10]; 9443 9444 u8 e[0x1]; 9445 u8 reserved_at_21[0x1f]; 9446 }; 9447 9448 struct mlx5_ifc_pmlp_reg_bits { 9449 u8 rxtx[0x1]; 9450 u8 reserved_at_1[0x7]; 9451 u8 local_port[0x8]; 9452 u8 reserved_at_10[0x8]; 9453 u8 width[0x8]; 9454 9455 u8 lane0_module_mapping[0x20]; 9456 9457 u8 lane1_module_mapping[0x20]; 9458 9459 u8 lane2_module_mapping[0x20]; 9460 9461 u8 lane3_module_mapping[0x20]; 9462 9463 u8 reserved_at_a0[0x160]; 9464 }; 9465 9466 struct mlx5_ifc_pmaos_reg_bits { 9467 u8 reserved_at_0[0x8]; 9468 u8 module[0x8]; 9469 u8 reserved_at_10[0x4]; 9470 u8 admin_status[0x4]; 9471 u8 reserved_at_18[0x4]; 9472 u8 oper_status[0x4]; 9473 9474 u8 ase[0x1]; 9475 u8 ee[0x1]; 9476 u8 reserved_at_22[0x1c]; 9477 u8 e[0x2]; 9478 9479 u8 reserved_at_40[0x40]; 9480 }; 9481 9482 struct mlx5_ifc_plpc_reg_bits { 9483 u8 reserved_at_0[0x4]; 9484 u8 profile_id[0xc]; 9485 u8 reserved_at_10[0x4]; 9486 u8 proto_mask[0x4]; 9487 u8 reserved_at_18[0x8]; 9488 9489 u8 reserved_at_20[0x10]; 9490 u8 lane_speed[0x10]; 9491 9492 u8 reserved_at_40[0x17]; 9493 u8 lpbf[0x1]; 9494 u8 fec_mode_policy[0x8]; 9495 9496 u8 retransmission_capability[0x8]; 9497 u8 fec_mode_capability[0x18]; 9498 9499 u8 retransmission_support_admin[0x8]; 9500 u8 fec_mode_support_admin[0x18]; 9501 9502 u8 retransmission_request_admin[0x8]; 9503 u8 fec_mode_request_admin[0x18]; 9504 9505 u8 reserved_at_c0[0x80]; 9506 }; 9507 9508 struct mlx5_ifc_plib_reg_bits { 9509 u8 reserved_at_0[0x8]; 9510 u8 local_port[0x8]; 9511 u8 reserved_at_10[0x8]; 9512 u8 ib_port[0x8]; 9513 9514 u8 reserved_at_20[0x60]; 9515 }; 9516 9517 struct mlx5_ifc_plbf_reg_bits { 9518 u8 reserved_at_0[0x8]; 9519 u8 local_port[0x8]; 9520 u8 reserved_at_10[0xd]; 9521 u8 lbf_mode[0x3]; 9522 9523 u8 reserved_at_20[0x20]; 9524 }; 9525 9526 struct mlx5_ifc_pipg_reg_bits { 9527 u8 reserved_at_0[0x8]; 9528 u8 local_port[0x8]; 9529 u8 reserved_at_10[0x10]; 9530 9531 u8 dic[0x1]; 9532 u8 reserved_at_21[0x19]; 9533 u8 ipg[0x4]; 9534 u8 reserved_at_3e[0x2]; 9535 }; 9536 9537 struct mlx5_ifc_pifr_reg_bits { 9538 u8 reserved_at_0[0x8]; 9539 u8 local_port[0x8]; 9540 u8 reserved_at_10[0x10]; 9541 9542 u8 reserved_at_20[0xe0]; 9543 9544 u8 port_filter[8][0x20]; 9545 9546 u8 port_filter_update_en[8][0x20]; 9547 }; 9548 9549 struct mlx5_ifc_pfcc_reg_bits { 9550 u8 reserved_at_0[0x8]; 9551 u8 local_port[0x8]; 9552 u8 reserved_at_10[0xb]; 9553 u8 ppan_mask_n[0x1]; 9554 u8 minor_stall_mask[0x1]; 9555 u8 critical_stall_mask[0x1]; 9556 u8 reserved_at_1e[0x2]; 9557 9558 u8 ppan[0x4]; 9559 u8 reserved_at_24[0x4]; 9560 u8 prio_mask_tx[0x8]; 9561 u8 reserved_at_30[0x8]; 9562 u8 prio_mask_rx[0x8]; 9563 9564 u8 pptx[0x1]; 9565 u8 aptx[0x1]; 9566 u8 pptx_mask_n[0x1]; 9567 u8 reserved_at_43[0x5]; 9568 u8 pfctx[0x8]; 9569 u8 reserved_at_50[0x10]; 9570 9571 u8 pprx[0x1]; 9572 u8 aprx[0x1]; 9573 u8 pprx_mask_n[0x1]; 9574 u8 reserved_at_63[0x5]; 9575 u8 pfcrx[0x8]; 9576 u8 reserved_at_70[0x10]; 9577 9578 u8 device_stall_minor_watermark[0x10]; 9579 u8 device_stall_critical_watermark[0x10]; 9580 9581 u8 reserved_at_a0[0x60]; 9582 }; 9583 9584 struct mlx5_ifc_pelc_reg_bits { 9585 u8 op[0x4]; 9586 u8 reserved_at_4[0x4]; 9587 u8 local_port[0x8]; 9588 u8 reserved_at_10[0x10]; 9589 9590 u8 op_admin[0x8]; 9591 u8 op_capability[0x8]; 9592 u8 op_request[0x8]; 9593 u8 op_active[0x8]; 9594 9595 u8 admin[0x40]; 9596 9597 u8 capability[0x40]; 9598 9599 u8 request[0x40]; 9600 9601 u8 active[0x40]; 9602 9603 u8 reserved_at_140[0x80]; 9604 }; 9605 9606 struct mlx5_ifc_peir_reg_bits { 9607 u8 reserved_at_0[0x8]; 9608 u8 local_port[0x8]; 9609 u8 reserved_at_10[0x10]; 9610 9611 u8 reserved_at_20[0xc]; 9612 u8 error_count[0x4]; 9613 u8 reserved_at_30[0x10]; 9614 9615 u8 reserved_at_40[0xc]; 9616 u8 lane[0x4]; 9617 u8 reserved_at_50[0x8]; 9618 u8 error_type[0x8]; 9619 }; 9620 9621 struct mlx5_ifc_mpegc_reg_bits { 9622 u8 reserved_at_0[0x30]; 9623 u8 field_select[0x10]; 9624 9625 u8 tx_overflow_sense[0x1]; 9626 u8 mark_cqe[0x1]; 9627 u8 mark_cnp[0x1]; 9628 u8 reserved_at_43[0x1b]; 9629 u8 tx_lossy_overflow_oper[0x2]; 9630 9631 u8 reserved_at_60[0x100]; 9632 }; 9633 9634 enum { 9635 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9636 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9637 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9638 }; 9639 9640 struct mlx5_ifc_mtutc_reg_bits { 9641 u8 reserved_at_0[0x1c]; 9642 u8 operation[0x4]; 9643 9644 u8 freq_adjustment[0x20]; 9645 9646 u8 reserved_at_40[0x40]; 9647 9648 u8 utc_sec[0x20]; 9649 9650 u8 reserved_at_a0[0x2]; 9651 u8 utc_nsec[0x1e]; 9652 9653 u8 time_adjustment[0x20]; 9654 }; 9655 9656 struct mlx5_ifc_pcam_enhanced_features_bits { 9657 u8 reserved_at_0[0x68]; 9658 u8 fec_50G_per_lane_in_pplm[0x1]; 9659 u8 reserved_at_69[0x4]; 9660 u8 rx_icrc_encapsulated_counter[0x1]; 9661 u8 reserved_at_6e[0x4]; 9662 u8 ptys_extended_ethernet[0x1]; 9663 u8 reserved_at_73[0x3]; 9664 u8 pfcc_mask[0x1]; 9665 u8 reserved_at_77[0x3]; 9666 u8 per_lane_error_counters[0x1]; 9667 u8 rx_buffer_fullness_counters[0x1]; 9668 u8 ptys_connector_type[0x1]; 9669 u8 reserved_at_7d[0x1]; 9670 u8 ppcnt_discard_group[0x1]; 9671 u8 ppcnt_statistical_group[0x1]; 9672 }; 9673 9674 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9675 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9676 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9677 9678 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9679 u8 pplm[0x1]; 9680 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9681 9682 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9683 u8 pbmc[0x1]; 9684 u8 pptb[0x1]; 9685 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9686 u8 ppcnt[0x1]; 9687 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9688 }; 9689 9690 struct mlx5_ifc_pcam_reg_bits { 9691 u8 reserved_at_0[0x8]; 9692 u8 feature_group[0x8]; 9693 u8 reserved_at_10[0x8]; 9694 u8 access_reg_group[0x8]; 9695 9696 u8 reserved_at_20[0x20]; 9697 9698 union { 9699 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9700 u8 reserved_at_0[0x80]; 9701 } port_access_reg_cap_mask; 9702 9703 u8 reserved_at_c0[0x80]; 9704 9705 union { 9706 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9707 u8 reserved_at_0[0x80]; 9708 } feature_cap_mask; 9709 9710 u8 reserved_at_1c0[0xc0]; 9711 }; 9712 9713 struct mlx5_ifc_mcam_enhanced_features_bits { 9714 u8 reserved_at_0[0x5d]; 9715 u8 mcia_32dwords[0x1]; 9716 u8 reserved_at_5e[0xc]; 9717 u8 reset_state[0x1]; 9718 u8 ptpcyc2realtime_modify[0x1]; 9719 u8 reserved_at_6c[0x2]; 9720 u8 pci_status_and_power[0x1]; 9721 u8 reserved_at_6f[0x5]; 9722 u8 mark_tx_action_cnp[0x1]; 9723 u8 mark_tx_action_cqe[0x1]; 9724 u8 dynamic_tx_overflow[0x1]; 9725 u8 reserved_at_77[0x4]; 9726 u8 pcie_outbound_stalled[0x1]; 9727 u8 tx_overflow_buffer_pkt[0x1]; 9728 u8 mtpps_enh_out_per_adj[0x1]; 9729 u8 mtpps_fs[0x1]; 9730 u8 pcie_performance_group[0x1]; 9731 }; 9732 9733 struct mlx5_ifc_mcam_access_reg_bits { 9734 u8 reserved_at_0[0x1c]; 9735 u8 mcda[0x1]; 9736 u8 mcc[0x1]; 9737 u8 mcqi[0x1]; 9738 u8 mcqs[0x1]; 9739 9740 u8 regs_95_to_87[0x9]; 9741 u8 mpegc[0x1]; 9742 u8 mtutc[0x1]; 9743 u8 regs_84_to_68[0x11]; 9744 u8 tracer_registers[0x4]; 9745 9746 u8 regs_63_to_46[0x12]; 9747 u8 mrtc[0x1]; 9748 u8 regs_44_to_32[0xd]; 9749 9750 u8 regs_31_to_0[0x20]; 9751 }; 9752 9753 struct mlx5_ifc_mcam_access_reg_bits1 { 9754 u8 regs_127_to_96[0x20]; 9755 9756 u8 regs_95_to_64[0x20]; 9757 9758 u8 regs_63_to_32[0x20]; 9759 9760 u8 regs_31_to_0[0x20]; 9761 }; 9762 9763 struct mlx5_ifc_mcam_access_reg_bits2 { 9764 u8 regs_127_to_99[0x1d]; 9765 u8 mirc[0x1]; 9766 u8 regs_97_to_96[0x2]; 9767 9768 u8 regs_95_to_64[0x20]; 9769 9770 u8 regs_63_to_32[0x20]; 9771 9772 u8 regs_31_to_0[0x20]; 9773 }; 9774 9775 struct mlx5_ifc_mcam_reg_bits { 9776 u8 reserved_at_0[0x8]; 9777 u8 feature_group[0x8]; 9778 u8 reserved_at_10[0x8]; 9779 u8 access_reg_group[0x8]; 9780 9781 u8 reserved_at_20[0x20]; 9782 9783 union { 9784 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9785 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9786 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9787 u8 reserved_at_0[0x80]; 9788 } mng_access_reg_cap_mask; 9789 9790 u8 reserved_at_c0[0x80]; 9791 9792 union { 9793 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9794 u8 reserved_at_0[0x80]; 9795 } mng_feature_cap_mask; 9796 9797 u8 reserved_at_1c0[0x80]; 9798 }; 9799 9800 struct mlx5_ifc_qcam_access_reg_cap_mask { 9801 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9802 u8 qpdpm[0x1]; 9803 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9804 u8 qdpm[0x1]; 9805 u8 qpts[0x1]; 9806 u8 qcap[0x1]; 9807 u8 qcam_access_reg_cap_mask_0[0x1]; 9808 }; 9809 9810 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9811 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9812 u8 qpts_trust_both[0x1]; 9813 }; 9814 9815 struct mlx5_ifc_qcam_reg_bits { 9816 u8 reserved_at_0[0x8]; 9817 u8 feature_group[0x8]; 9818 u8 reserved_at_10[0x8]; 9819 u8 access_reg_group[0x8]; 9820 u8 reserved_at_20[0x20]; 9821 9822 union { 9823 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9824 u8 reserved_at_0[0x80]; 9825 } qos_access_reg_cap_mask; 9826 9827 u8 reserved_at_c0[0x80]; 9828 9829 union { 9830 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9831 u8 reserved_at_0[0x80]; 9832 } qos_feature_cap_mask; 9833 9834 u8 reserved_at_1c0[0x80]; 9835 }; 9836 9837 struct mlx5_ifc_core_dump_reg_bits { 9838 u8 reserved_at_0[0x18]; 9839 u8 core_dump_type[0x8]; 9840 9841 u8 reserved_at_20[0x30]; 9842 u8 vhca_id[0x10]; 9843 9844 u8 reserved_at_60[0x8]; 9845 u8 qpn[0x18]; 9846 u8 reserved_at_80[0x180]; 9847 }; 9848 9849 struct mlx5_ifc_pcap_reg_bits { 9850 u8 reserved_at_0[0x8]; 9851 u8 local_port[0x8]; 9852 u8 reserved_at_10[0x10]; 9853 9854 u8 port_capability_mask[4][0x20]; 9855 }; 9856 9857 struct mlx5_ifc_paos_reg_bits { 9858 u8 swid[0x8]; 9859 u8 local_port[0x8]; 9860 u8 reserved_at_10[0x4]; 9861 u8 admin_status[0x4]; 9862 u8 reserved_at_18[0x4]; 9863 u8 oper_status[0x4]; 9864 9865 u8 ase[0x1]; 9866 u8 ee[0x1]; 9867 u8 reserved_at_22[0x1c]; 9868 u8 e[0x2]; 9869 9870 u8 reserved_at_40[0x40]; 9871 }; 9872 9873 struct mlx5_ifc_pamp_reg_bits { 9874 u8 reserved_at_0[0x8]; 9875 u8 opamp_group[0x8]; 9876 u8 reserved_at_10[0xc]; 9877 u8 opamp_group_type[0x4]; 9878 9879 u8 start_index[0x10]; 9880 u8 reserved_at_30[0x4]; 9881 u8 num_of_indices[0xc]; 9882 9883 u8 index_data[18][0x10]; 9884 }; 9885 9886 struct mlx5_ifc_pcmr_reg_bits { 9887 u8 reserved_at_0[0x8]; 9888 u8 local_port[0x8]; 9889 u8 reserved_at_10[0x10]; 9890 9891 u8 entropy_force_cap[0x1]; 9892 u8 entropy_calc_cap[0x1]; 9893 u8 entropy_gre_calc_cap[0x1]; 9894 u8 reserved_at_23[0xf]; 9895 u8 rx_ts_over_crc_cap[0x1]; 9896 u8 reserved_at_33[0xb]; 9897 u8 fcs_cap[0x1]; 9898 u8 reserved_at_3f[0x1]; 9899 9900 u8 entropy_force[0x1]; 9901 u8 entropy_calc[0x1]; 9902 u8 entropy_gre_calc[0x1]; 9903 u8 reserved_at_43[0xf]; 9904 u8 rx_ts_over_crc[0x1]; 9905 u8 reserved_at_53[0xb]; 9906 u8 fcs_chk[0x1]; 9907 u8 reserved_at_5f[0x1]; 9908 }; 9909 9910 struct mlx5_ifc_lane_2_module_mapping_bits { 9911 u8 reserved_at_0[0x4]; 9912 u8 rx_lane[0x4]; 9913 u8 reserved_at_8[0x4]; 9914 u8 tx_lane[0x4]; 9915 u8 reserved_at_10[0x8]; 9916 u8 module[0x8]; 9917 }; 9918 9919 struct mlx5_ifc_bufferx_reg_bits { 9920 u8 reserved_at_0[0x6]; 9921 u8 lossy[0x1]; 9922 u8 epsb[0x1]; 9923 u8 reserved_at_8[0x8]; 9924 u8 size[0x10]; 9925 9926 u8 xoff_threshold[0x10]; 9927 u8 xon_threshold[0x10]; 9928 }; 9929 9930 struct mlx5_ifc_set_node_in_bits { 9931 u8 node_description[64][0x8]; 9932 }; 9933 9934 struct mlx5_ifc_register_power_settings_bits { 9935 u8 reserved_at_0[0x18]; 9936 u8 power_settings_level[0x8]; 9937 9938 u8 reserved_at_20[0x60]; 9939 }; 9940 9941 struct mlx5_ifc_register_host_endianness_bits { 9942 u8 he[0x1]; 9943 u8 reserved_at_1[0x1f]; 9944 9945 u8 reserved_at_20[0x60]; 9946 }; 9947 9948 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9949 u8 reserved_at_0[0x20]; 9950 9951 u8 mkey[0x20]; 9952 9953 u8 addressh_63_32[0x20]; 9954 9955 u8 addressl_31_0[0x20]; 9956 }; 9957 9958 struct mlx5_ifc_ud_adrs_vector_bits { 9959 u8 dc_key[0x40]; 9960 9961 u8 ext[0x1]; 9962 u8 reserved_at_41[0x7]; 9963 u8 destination_qp_dct[0x18]; 9964 9965 u8 static_rate[0x4]; 9966 u8 sl_eth_prio[0x4]; 9967 u8 fl[0x1]; 9968 u8 mlid[0x7]; 9969 u8 rlid_udp_sport[0x10]; 9970 9971 u8 reserved_at_80[0x20]; 9972 9973 u8 rmac_47_16[0x20]; 9974 9975 u8 rmac_15_0[0x10]; 9976 u8 tclass[0x8]; 9977 u8 hop_limit[0x8]; 9978 9979 u8 reserved_at_e0[0x1]; 9980 u8 grh[0x1]; 9981 u8 reserved_at_e2[0x2]; 9982 u8 src_addr_index[0x8]; 9983 u8 flow_label[0x14]; 9984 9985 u8 rgid_rip[16][0x8]; 9986 }; 9987 9988 struct mlx5_ifc_pages_req_event_bits { 9989 u8 reserved_at_0[0x10]; 9990 u8 function_id[0x10]; 9991 9992 u8 num_pages[0x20]; 9993 9994 u8 reserved_at_40[0xa0]; 9995 }; 9996 9997 struct mlx5_ifc_eqe_bits { 9998 u8 reserved_at_0[0x8]; 9999 u8 event_type[0x8]; 10000 u8 reserved_at_10[0x8]; 10001 u8 event_sub_type[0x8]; 10002 10003 u8 reserved_at_20[0xe0]; 10004 10005 union mlx5_ifc_event_auto_bits event_data; 10006 10007 u8 reserved_at_1e0[0x10]; 10008 u8 signature[0x8]; 10009 u8 reserved_at_1f8[0x7]; 10010 u8 owner[0x1]; 10011 }; 10012 10013 enum { 10014 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10015 }; 10016 10017 struct mlx5_ifc_cmd_queue_entry_bits { 10018 u8 type[0x8]; 10019 u8 reserved_at_8[0x18]; 10020 10021 u8 input_length[0x20]; 10022 10023 u8 input_mailbox_pointer_63_32[0x20]; 10024 10025 u8 input_mailbox_pointer_31_9[0x17]; 10026 u8 reserved_at_77[0x9]; 10027 10028 u8 command_input_inline_data[16][0x8]; 10029 10030 u8 command_output_inline_data[16][0x8]; 10031 10032 u8 output_mailbox_pointer_63_32[0x20]; 10033 10034 u8 output_mailbox_pointer_31_9[0x17]; 10035 u8 reserved_at_1b7[0x9]; 10036 10037 u8 output_length[0x20]; 10038 10039 u8 token[0x8]; 10040 u8 signature[0x8]; 10041 u8 reserved_at_1f0[0x8]; 10042 u8 status[0x7]; 10043 u8 ownership[0x1]; 10044 }; 10045 10046 struct mlx5_ifc_cmd_out_bits { 10047 u8 status[0x8]; 10048 u8 reserved_at_8[0x18]; 10049 10050 u8 syndrome[0x20]; 10051 10052 u8 command_output[0x20]; 10053 }; 10054 10055 struct mlx5_ifc_cmd_in_bits { 10056 u8 opcode[0x10]; 10057 u8 reserved_at_10[0x10]; 10058 10059 u8 reserved_at_20[0x10]; 10060 u8 op_mod[0x10]; 10061 10062 u8 command[][0x20]; 10063 }; 10064 10065 struct mlx5_ifc_cmd_if_box_bits { 10066 u8 mailbox_data[512][0x8]; 10067 10068 u8 reserved_at_1000[0x180]; 10069 10070 u8 next_pointer_63_32[0x20]; 10071 10072 u8 next_pointer_31_10[0x16]; 10073 u8 reserved_at_11b6[0xa]; 10074 10075 u8 block_number[0x20]; 10076 10077 u8 reserved_at_11e0[0x8]; 10078 u8 token[0x8]; 10079 u8 ctrl_signature[0x8]; 10080 u8 signature[0x8]; 10081 }; 10082 10083 struct mlx5_ifc_mtt_bits { 10084 u8 ptag_63_32[0x20]; 10085 10086 u8 ptag_31_8[0x18]; 10087 u8 reserved_at_38[0x6]; 10088 u8 wr_en[0x1]; 10089 u8 rd_en[0x1]; 10090 }; 10091 10092 struct mlx5_ifc_query_wol_rol_out_bits { 10093 u8 status[0x8]; 10094 u8 reserved_at_8[0x18]; 10095 10096 u8 syndrome[0x20]; 10097 10098 u8 reserved_at_40[0x10]; 10099 u8 rol_mode[0x8]; 10100 u8 wol_mode[0x8]; 10101 10102 u8 reserved_at_60[0x20]; 10103 }; 10104 10105 struct mlx5_ifc_query_wol_rol_in_bits { 10106 u8 opcode[0x10]; 10107 u8 reserved_at_10[0x10]; 10108 10109 u8 reserved_at_20[0x10]; 10110 u8 op_mod[0x10]; 10111 10112 u8 reserved_at_40[0x40]; 10113 }; 10114 10115 struct mlx5_ifc_set_wol_rol_out_bits { 10116 u8 status[0x8]; 10117 u8 reserved_at_8[0x18]; 10118 10119 u8 syndrome[0x20]; 10120 10121 u8 reserved_at_40[0x40]; 10122 }; 10123 10124 struct mlx5_ifc_set_wol_rol_in_bits { 10125 u8 opcode[0x10]; 10126 u8 reserved_at_10[0x10]; 10127 10128 u8 reserved_at_20[0x10]; 10129 u8 op_mod[0x10]; 10130 10131 u8 rol_mode_valid[0x1]; 10132 u8 wol_mode_valid[0x1]; 10133 u8 reserved_at_42[0xe]; 10134 u8 rol_mode[0x8]; 10135 u8 wol_mode[0x8]; 10136 10137 u8 reserved_at_60[0x20]; 10138 }; 10139 10140 enum { 10141 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10142 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10143 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10144 }; 10145 10146 enum { 10147 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10148 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10149 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10150 }; 10151 10152 enum { 10153 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10154 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10155 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10156 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10157 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10158 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10159 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10160 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10161 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10162 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10163 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10164 }; 10165 10166 struct mlx5_ifc_initial_seg_bits { 10167 u8 fw_rev_minor[0x10]; 10168 u8 fw_rev_major[0x10]; 10169 10170 u8 cmd_interface_rev[0x10]; 10171 u8 fw_rev_subminor[0x10]; 10172 10173 u8 reserved_at_40[0x40]; 10174 10175 u8 cmdq_phy_addr_63_32[0x20]; 10176 10177 u8 cmdq_phy_addr_31_12[0x14]; 10178 u8 reserved_at_b4[0x2]; 10179 u8 nic_interface[0x2]; 10180 u8 log_cmdq_size[0x4]; 10181 u8 log_cmdq_stride[0x4]; 10182 10183 u8 command_doorbell_vector[0x20]; 10184 10185 u8 reserved_at_e0[0xf00]; 10186 10187 u8 initializing[0x1]; 10188 u8 reserved_at_fe1[0x4]; 10189 u8 nic_interface_supported[0x3]; 10190 u8 embedded_cpu[0x1]; 10191 u8 reserved_at_fe9[0x17]; 10192 10193 struct mlx5_ifc_health_buffer_bits health_buffer; 10194 10195 u8 no_dram_nic_offset[0x20]; 10196 10197 u8 reserved_at_1220[0x6e40]; 10198 10199 u8 reserved_at_8060[0x1f]; 10200 u8 clear_int[0x1]; 10201 10202 u8 health_syndrome[0x8]; 10203 u8 health_counter[0x18]; 10204 10205 u8 reserved_at_80a0[0x17fc0]; 10206 }; 10207 10208 struct mlx5_ifc_mtpps_reg_bits { 10209 u8 reserved_at_0[0xc]; 10210 u8 cap_number_of_pps_pins[0x4]; 10211 u8 reserved_at_10[0x4]; 10212 u8 cap_max_num_of_pps_in_pins[0x4]; 10213 u8 reserved_at_18[0x4]; 10214 u8 cap_max_num_of_pps_out_pins[0x4]; 10215 10216 u8 reserved_at_20[0x24]; 10217 u8 cap_pin_3_mode[0x4]; 10218 u8 reserved_at_48[0x4]; 10219 u8 cap_pin_2_mode[0x4]; 10220 u8 reserved_at_50[0x4]; 10221 u8 cap_pin_1_mode[0x4]; 10222 u8 reserved_at_58[0x4]; 10223 u8 cap_pin_0_mode[0x4]; 10224 10225 u8 reserved_at_60[0x4]; 10226 u8 cap_pin_7_mode[0x4]; 10227 u8 reserved_at_68[0x4]; 10228 u8 cap_pin_6_mode[0x4]; 10229 u8 reserved_at_70[0x4]; 10230 u8 cap_pin_5_mode[0x4]; 10231 u8 reserved_at_78[0x4]; 10232 u8 cap_pin_4_mode[0x4]; 10233 10234 u8 field_select[0x20]; 10235 u8 reserved_at_a0[0x60]; 10236 10237 u8 enable[0x1]; 10238 u8 reserved_at_101[0xb]; 10239 u8 pattern[0x4]; 10240 u8 reserved_at_110[0x4]; 10241 u8 pin_mode[0x4]; 10242 u8 pin[0x8]; 10243 10244 u8 reserved_at_120[0x20]; 10245 10246 u8 time_stamp[0x40]; 10247 10248 u8 out_pulse_duration[0x10]; 10249 u8 out_periodic_adjustment[0x10]; 10250 u8 enhanced_out_periodic_adjustment[0x20]; 10251 10252 u8 reserved_at_1c0[0x20]; 10253 }; 10254 10255 struct mlx5_ifc_mtppse_reg_bits { 10256 u8 reserved_at_0[0x18]; 10257 u8 pin[0x8]; 10258 u8 event_arm[0x1]; 10259 u8 reserved_at_21[0x1b]; 10260 u8 event_generation_mode[0x4]; 10261 u8 reserved_at_40[0x40]; 10262 }; 10263 10264 struct mlx5_ifc_mcqs_reg_bits { 10265 u8 last_index_flag[0x1]; 10266 u8 reserved_at_1[0x7]; 10267 u8 fw_device[0x8]; 10268 u8 component_index[0x10]; 10269 10270 u8 reserved_at_20[0x10]; 10271 u8 identifier[0x10]; 10272 10273 u8 reserved_at_40[0x17]; 10274 u8 component_status[0x5]; 10275 u8 component_update_state[0x4]; 10276 10277 u8 last_update_state_changer_type[0x4]; 10278 u8 last_update_state_changer_host_id[0x4]; 10279 u8 reserved_at_68[0x18]; 10280 }; 10281 10282 struct mlx5_ifc_mcqi_cap_bits { 10283 u8 supported_info_bitmask[0x20]; 10284 10285 u8 component_size[0x20]; 10286 10287 u8 max_component_size[0x20]; 10288 10289 u8 log_mcda_word_size[0x4]; 10290 u8 reserved_at_64[0xc]; 10291 u8 mcda_max_write_size[0x10]; 10292 10293 u8 rd_en[0x1]; 10294 u8 reserved_at_81[0x1]; 10295 u8 match_chip_id[0x1]; 10296 u8 match_psid[0x1]; 10297 u8 check_user_timestamp[0x1]; 10298 u8 match_base_guid_mac[0x1]; 10299 u8 reserved_at_86[0x1a]; 10300 }; 10301 10302 struct mlx5_ifc_mcqi_version_bits { 10303 u8 reserved_at_0[0x2]; 10304 u8 build_time_valid[0x1]; 10305 u8 user_defined_time_valid[0x1]; 10306 u8 reserved_at_4[0x14]; 10307 u8 version_string_length[0x8]; 10308 10309 u8 version[0x20]; 10310 10311 u8 build_time[0x40]; 10312 10313 u8 user_defined_time[0x40]; 10314 10315 u8 build_tool_version[0x20]; 10316 10317 u8 reserved_at_e0[0x20]; 10318 10319 u8 version_string[92][0x8]; 10320 }; 10321 10322 struct mlx5_ifc_mcqi_activation_method_bits { 10323 u8 pending_server_ac_power_cycle[0x1]; 10324 u8 pending_server_dc_power_cycle[0x1]; 10325 u8 pending_server_reboot[0x1]; 10326 u8 pending_fw_reset[0x1]; 10327 u8 auto_activate[0x1]; 10328 u8 all_hosts_sync[0x1]; 10329 u8 device_hw_reset[0x1]; 10330 u8 reserved_at_7[0x19]; 10331 }; 10332 10333 union mlx5_ifc_mcqi_reg_data_bits { 10334 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10335 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10336 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10337 }; 10338 10339 struct mlx5_ifc_mcqi_reg_bits { 10340 u8 read_pending_component[0x1]; 10341 u8 reserved_at_1[0xf]; 10342 u8 component_index[0x10]; 10343 10344 u8 reserved_at_20[0x20]; 10345 10346 u8 reserved_at_40[0x1b]; 10347 u8 info_type[0x5]; 10348 10349 u8 info_size[0x20]; 10350 10351 u8 offset[0x20]; 10352 10353 u8 reserved_at_a0[0x10]; 10354 u8 data_size[0x10]; 10355 10356 union mlx5_ifc_mcqi_reg_data_bits data[]; 10357 }; 10358 10359 struct mlx5_ifc_mcc_reg_bits { 10360 u8 reserved_at_0[0x4]; 10361 u8 time_elapsed_since_last_cmd[0xc]; 10362 u8 reserved_at_10[0x8]; 10363 u8 instruction[0x8]; 10364 10365 u8 reserved_at_20[0x10]; 10366 u8 component_index[0x10]; 10367 10368 u8 reserved_at_40[0x8]; 10369 u8 update_handle[0x18]; 10370 10371 u8 handle_owner_type[0x4]; 10372 u8 handle_owner_host_id[0x4]; 10373 u8 reserved_at_68[0x1]; 10374 u8 control_progress[0x7]; 10375 u8 error_code[0x8]; 10376 u8 reserved_at_78[0x4]; 10377 u8 control_state[0x4]; 10378 10379 u8 component_size[0x20]; 10380 10381 u8 reserved_at_a0[0x60]; 10382 }; 10383 10384 struct mlx5_ifc_mcda_reg_bits { 10385 u8 reserved_at_0[0x8]; 10386 u8 update_handle[0x18]; 10387 10388 u8 offset[0x20]; 10389 10390 u8 reserved_at_40[0x10]; 10391 u8 size[0x10]; 10392 10393 u8 reserved_at_60[0x20]; 10394 10395 u8 data[][0x20]; 10396 }; 10397 10398 enum { 10399 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10400 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10401 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10402 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10403 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10404 }; 10405 10406 enum { 10407 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10408 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10409 }; 10410 10411 enum { 10412 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10413 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10414 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10415 }; 10416 10417 struct mlx5_ifc_mfrl_reg_bits { 10418 u8 reserved_at_0[0x20]; 10419 10420 u8 reserved_at_20[0x2]; 10421 u8 pci_sync_for_fw_update_start[0x1]; 10422 u8 pci_sync_for_fw_update_resp[0x2]; 10423 u8 rst_type_sel[0x3]; 10424 u8 reserved_at_28[0x4]; 10425 u8 reset_state[0x4]; 10426 u8 reset_type[0x8]; 10427 u8 reset_level[0x8]; 10428 }; 10429 10430 struct mlx5_ifc_mirc_reg_bits { 10431 u8 reserved_at_0[0x18]; 10432 u8 status_code[0x8]; 10433 10434 u8 reserved_at_20[0x20]; 10435 }; 10436 10437 struct mlx5_ifc_pddr_monitor_opcode_bits { 10438 u8 reserved_at_0[0x10]; 10439 u8 monitor_opcode[0x10]; 10440 }; 10441 10442 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10443 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10444 u8 reserved_at_0[0x20]; 10445 }; 10446 10447 enum { 10448 /* Monitor opcodes */ 10449 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10450 }; 10451 10452 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10453 u8 reserved_at_0[0x10]; 10454 u8 group_opcode[0x10]; 10455 10456 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10457 10458 u8 reserved_at_40[0x20]; 10459 10460 u8 status_message[59][0x20]; 10461 }; 10462 10463 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10464 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10465 u8 reserved_at_0[0x7c0]; 10466 }; 10467 10468 enum { 10469 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10470 }; 10471 10472 struct mlx5_ifc_pddr_reg_bits { 10473 u8 reserved_at_0[0x8]; 10474 u8 local_port[0x8]; 10475 u8 pnat[0x2]; 10476 u8 reserved_at_12[0xe]; 10477 10478 u8 reserved_at_20[0x18]; 10479 u8 page_select[0x8]; 10480 10481 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10482 }; 10483 10484 struct mlx5_ifc_mrtc_reg_bits { 10485 u8 time_synced[0x1]; 10486 u8 reserved_at_1[0x1f]; 10487 10488 u8 reserved_at_20[0x20]; 10489 10490 u8 time_h[0x20]; 10491 10492 u8 time_l[0x20]; 10493 }; 10494 10495 union mlx5_ifc_ports_control_registers_document_bits { 10496 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10497 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10498 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10499 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10500 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10501 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10502 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10503 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10504 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10505 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10506 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10507 struct mlx5_ifc_paos_reg_bits paos_reg; 10508 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10509 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10510 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10511 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10512 struct mlx5_ifc_peir_reg_bits peir_reg; 10513 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10514 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10515 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10516 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10517 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10518 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10519 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10520 struct mlx5_ifc_plib_reg_bits plib_reg; 10521 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10522 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10523 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10524 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10525 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10526 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10527 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10528 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10529 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10530 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10531 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10532 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10533 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10534 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10535 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10536 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10537 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10538 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10539 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10540 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10541 struct mlx5_ifc_pude_reg_bits pude_reg; 10542 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10543 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10544 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10545 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10546 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10547 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10548 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10549 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10550 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10551 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10552 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10553 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10554 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10555 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10556 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10557 u8 reserved_at_0[0x60e0]; 10558 }; 10559 10560 union mlx5_ifc_debug_enhancements_document_bits { 10561 struct mlx5_ifc_health_buffer_bits health_buffer; 10562 u8 reserved_at_0[0x200]; 10563 }; 10564 10565 union mlx5_ifc_uplink_pci_interface_document_bits { 10566 struct mlx5_ifc_initial_seg_bits initial_seg; 10567 u8 reserved_at_0[0x20060]; 10568 }; 10569 10570 struct mlx5_ifc_set_flow_table_root_out_bits { 10571 u8 status[0x8]; 10572 u8 reserved_at_8[0x18]; 10573 10574 u8 syndrome[0x20]; 10575 10576 u8 reserved_at_40[0x40]; 10577 }; 10578 10579 struct mlx5_ifc_set_flow_table_root_in_bits { 10580 u8 opcode[0x10]; 10581 u8 reserved_at_10[0x10]; 10582 10583 u8 reserved_at_20[0x10]; 10584 u8 op_mod[0x10]; 10585 10586 u8 other_vport[0x1]; 10587 u8 reserved_at_41[0xf]; 10588 u8 vport_number[0x10]; 10589 10590 u8 reserved_at_60[0x20]; 10591 10592 u8 table_type[0x8]; 10593 u8 reserved_at_88[0x7]; 10594 u8 table_of_other_vport[0x1]; 10595 u8 table_vport_number[0x10]; 10596 10597 u8 reserved_at_a0[0x8]; 10598 u8 table_id[0x18]; 10599 10600 u8 reserved_at_c0[0x8]; 10601 u8 underlay_qpn[0x18]; 10602 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10603 u8 reserved_at_e1[0xf]; 10604 u8 table_eswitch_owner_vhca_id[0x10]; 10605 u8 reserved_at_100[0x100]; 10606 }; 10607 10608 enum { 10609 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10610 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10611 }; 10612 10613 struct mlx5_ifc_modify_flow_table_out_bits { 10614 u8 status[0x8]; 10615 u8 reserved_at_8[0x18]; 10616 10617 u8 syndrome[0x20]; 10618 10619 u8 reserved_at_40[0x40]; 10620 }; 10621 10622 struct mlx5_ifc_modify_flow_table_in_bits { 10623 u8 opcode[0x10]; 10624 u8 reserved_at_10[0x10]; 10625 10626 u8 reserved_at_20[0x10]; 10627 u8 op_mod[0x10]; 10628 10629 u8 other_vport[0x1]; 10630 u8 reserved_at_41[0xf]; 10631 u8 vport_number[0x10]; 10632 10633 u8 reserved_at_60[0x10]; 10634 u8 modify_field_select[0x10]; 10635 10636 u8 table_type[0x8]; 10637 u8 reserved_at_88[0x18]; 10638 10639 u8 reserved_at_a0[0x8]; 10640 u8 table_id[0x18]; 10641 10642 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10643 }; 10644 10645 struct mlx5_ifc_ets_tcn_config_reg_bits { 10646 u8 g[0x1]; 10647 u8 b[0x1]; 10648 u8 r[0x1]; 10649 u8 reserved_at_3[0x9]; 10650 u8 group[0x4]; 10651 u8 reserved_at_10[0x9]; 10652 u8 bw_allocation[0x7]; 10653 10654 u8 reserved_at_20[0xc]; 10655 u8 max_bw_units[0x4]; 10656 u8 reserved_at_30[0x8]; 10657 u8 max_bw_value[0x8]; 10658 }; 10659 10660 struct mlx5_ifc_ets_global_config_reg_bits { 10661 u8 reserved_at_0[0x2]; 10662 u8 r[0x1]; 10663 u8 reserved_at_3[0x1d]; 10664 10665 u8 reserved_at_20[0xc]; 10666 u8 max_bw_units[0x4]; 10667 u8 reserved_at_30[0x8]; 10668 u8 max_bw_value[0x8]; 10669 }; 10670 10671 struct mlx5_ifc_qetc_reg_bits { 10672 u8 reserved_at_0[0x8]; 10673 u8 port_number[0x8]; 10674 u8 reserved_at_10[0x30]; 10675 10676 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10677 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10678 }; 10679 10680 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10681 u8 e[0x1]; 10682 u8 reserved_at_01[0x0b]; 10683 u8 prio[0x04]; 10684 }; 10685 10686 struct mlx5_ifc_qpdpm_reg_bits { 10687 u8 reserved_at_0[0x8]; 10688 u8 local_port[0x8]; 10689 u8 reserved_at_10[0x10]; 10690 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10691 }; 10692 10693 struct mlx5_ifc_qpts_reg_bits { 10694 u8 reserved_at_0[0x8]; 10695 u8 local_port[0x8]; 10696 u8 reserved_at_10[0x2d]; 10697 u8 trust_state[0x3]; 10698 }; 10699 10700 struct mlx5_ifc_pptb_reg_bits { 10701 u8 reserved_at_0[0x2]; 10702 u8 mm[0x2]; 10703 u8 reserved_at_4[0x4]; 10704 u8 local_port[0x8]; 10705 u8 reserved_at_10[0x6]; 10706 u8 cm[0x1]; 10707 u8 um[0x1]; 10708 u8 pm[0x8]; 10709 10710 u8 prio_x_buff[0x20]; 10711 10712 u8 pm_msb[0x8]; 10713 u8 reserved_at_48[0x10]; 10714 u8 ctrl_buff[0x4]; 10715 u8 untagged_buff[0x4]; 10716 }; 10717 10718 struct mlx5_ifc_sbcam_reg_bits { 10719 u8 reserved_at_0[0x8]; 10720 u8 feature_group[0x8]; 10721 u8 reserved_at_10[0x8]; 10722 u8 access_reg_group[0x8]; 10723 10724 u8 reserved_at_20[0x20]; 10725 10726 u8 sb_access_reg_cap_mask[4][0x20]; 10727 10728 u8 reserved_at_c0[0x80]; 10729 10730 u8 sb_feature_cap_mask[4][0x20]; 10731 10732 u8 reserved_at_1c0[0x40]; 10733 10734 u8 cap_total_buffer_size[0x20]; 10735 10736 u8 cap_cell_size[0x10]; 10737 u8 cap_max_pg_buffers[0x8]; 10738 u8 cap_num_pool_supported[0x8]; 10739 10740 u8 reserved_at_240[0x8]; 10741 u8 cap_sbsr_stat_size[0x8]; 10742 u8 cap_max_tclass_data[0x8]; 10743 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10744 }; 10745 10746 struct mlx5_ifc_pbmc_reg_bits { 10747 u8 reserved_at_0[0x8]; 10748 u8 local_port[0x8]; 10749 u8 reserved_at_10[0x10]; 10750 10751 u8 xoff_timer_value[0x10]; 10752 u8 xoff_refresh[0x10]; 10753 10754 u8 reserved_at_40[0x9]; 10755 u8 fullness_threshold[0x7]; 10756 u8 port_buffer_size[0x10]; 10757 10758 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10759 10760 u8 reserved_at_2e0[0x80]; 10761 }; 10762 10763 struct mlx5_ifc_qtct_reg_bits { 10764 u8 reserved_at_0[0x8]; 10765 u8 port_number[0x8]; 10766 u8 reserved_at_10[0xd]; 10767 u8 prio[0x3]; 10768 10769 u8 reserved_at_20[0x1d]; 10770 u8 tclass[0x3]; 10771 }; 10772 10773 struct mlx5_ifc_mcia_reg_bits { 10774 u8 l[0x1]; 10775 u8 reserved_at_1[0x7]; 10776 u8 module[0x8]; 10777 u8 reserved_at_10[0x8]; 10778 u8 status[0x8]; 10779 10780 u8 i2c_device_address[0x8]; 10781 u8 page_number[0x8]; 10782 u8 device_address[0x10]; 10783 10784 u8 reserved_at_40[0x10]; 10785 u8 size[0x10]; 10786 10787 u8 reserved_at_60[0x20]; 10788 10789 u8 dword_0[0x20]; 10790 u8 dword_1[0x20]; 10791 u8 dword_2[0x20]; 10792 u8 dword_3[0x20]; 10793 u8 dword_4[0x20]; 10794 u8 dword_5[0x20]; 10795 u8 dword_6[0x20]; 10796 u8 dword_7[0x20]; 10797 u8 dword_8[0x20]; 10798 u8 dword_9[0x20]; 10799 u8 dword_10[0x20]; 10800 u8 dword_11[0x20]; 10801 }; 10802 10803 struct mlx5_ifc_dcbx_param_bits { 10804 u8 dcbx_cee_cap[0x1]; 10805 u8 dcbx_ieee_cap[0x1]; 10806 u8 dcbx_standby_cap[0x1]; 10807 u8 reserved_at_3[0x5]; 10808 u8 port_number[0x8]; 10809 u8 reserved_at_10[0xa]; 10810 u8 max_application_table_size[6]; 10811 u8 reserved_at_20[0x15]; 10812 u8 version_oper[0x3]; 10813 u8 reserved_at_38[5]; 10814 u8 version_admin[0x3]; 10815 u8 willing_admin[0x1]; 10816 u8 reserved_at_41[0x3]; 10817 u8 pfc_cap_oper[0x4]; 10818 u8 reserved_at_48[0x4]; 10819 u8 pfc_cap_admin[0x4]; 10820 u8 reserved_at_50[0x4]; 10821 u8 num_of_tc_oper[0x4]; 10822 u8 reserved_at_58[0x4]; 10823 u8 num_of_tc_admin[0x4]; 10824 u8 remote_willing[0x1]; 10825 u8 reserved_at_61[3]; 10826 u8 remote_pfc_cap[4]; 10827 u8 reserved_at_68[0x14]; 10828 u8 remote_num_of_tc[0x4]; 10829 u8 reserved_at_80[0x18]; 10830 u8 error[0x8]; 10831 u8 reserved_at_a0[0x160]; 10832 }; 10833 10834 enum { 10835 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10836 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10837 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10838 }; 10839 10840 struct mlx5_ifc_lagc_bits { 10841 u8 fdb_selection_mode[0x1]; 10842 u8 reserved_at_1[0x14]; 10843 u8 port_select_mode[0x3]; 10844 u8 reserved_at_18[0x5]; 10845 u8 lag_state[0x3]; 10846 10847 u8 reserved_at_20[0x14]; 10848 u8 tx_remap_affinity_2[0x4]; 10849 u8 reserved_at_38[0x4]; 10850 u8 tx_remap_affinity_1[0x4]; 10851 }; 10852 10853 struct mlx5_ifc_create_lag_out_bits { 10854 u8 status[0x8]; 10855 u8 reserved_at_8[0x18]; 10856 10857 u8 syndrome[0x20]; 10858 10859 u8 reserved_at_40[0x40]; 10860 }; 10861 10862 struct mlx5_ifc_create_lag_in_bits { 10863 u8 opcode[0x10]; 10864 u8 reserved_at_10[0x10]; 10865 10866 u8 reserved_at_20[0x10]; 10867 u8 op_mod[0x10]; 10868 10869 struct mlx5_ifc_lagc_bits ctx; 10870 }; 10871 10872 struct mlx5_ifc_modify_lag_out_bits { 10873 u8 status[0x8]; 10874 u8 reserved_at_8[0x18]; 10875 10876 u8 syndrome[0x20]; 10877 10878 u8 reserved_at_40[0x40]; 10879 }; 10880 10881 struct mlx5_ifc_modify_lag_in_bits { 10882 u8 opcode[0x10]; 10883 u8 reserved_at_10[0x10]; 10884 10885 u8 reserved_at_20[0x10]; 10886 u8 op_mod[0x10]; 10887 10888 u8 reserved_at_40[0x20]; 10889 u8 field_select[0x20]; 10890 10891 struct mlx5_ifc_lagc_bits ctx; 10892 }; 10893 10894 struct mlx5_ifc_query_lag_out_bits { 10895 u8 status[0x8]; 10896 u8 reserved_at_8[0x18]; 10897 10898 u8 syndrome[0x20]; 10899 10900 struct mlx5_ifc_lagc_bits ctx; 10901 }; 10902 10903 struct mlx5_ifc_query_lag_in_bits { 10904 u8 opcode[0x10]; 10905 u8 reserved_at_10[0x10]; 10906 10907 u8 reserved_at_20[0x10]; 10908 u8 op_mod[0x10]; 10909 10910 u8 reserved_at_40[0x40]; 10911 }; 10912 10913 struct mlx5_ifc_destroy_lag_out_bits { 10914 u8 status[0x8]; 10915 u8 reserved_at_8[0x18]; 10916 10917 u8 syndrome[0x20]; 10918 10919 u8 reserved_at_40[0x40]; 10920 }; 10921 10922 struct mlx5_ifc_destroy_lag_in_bits { 10923 u8 opcode[0x10]; 10924 u8 reserved_at_10[0x10]; 10925 10926 u8 reserved_at_20[0x10]; 10927 u8 op_mod[0x10]; 10928 10929 u8 reserved_at_40[0x40]; 10930 }; 10931 10932 struct mlx5_ifc_create_vport_lag_out_bits { 10933 u8 status[0x8]; 10934 u8 reserved_at_8[0x18]; 10935 10936 u8 syndrome[0x20]; 10937 10938 u8 reserved_at_40[0x40]; 10939 }; 10940 10941 struct mlx5_ifc_create_vport_lag_in_bits { 10942 u8 opcode[0x10]; 10943 u8 reserved_at_10[0x10]; 10944 10945 u8 reserved_at_20[0x10]; 10946 u8 op_mod[0x10]; 10947 10948 u8 reserved_at_40[0x40]; 10949 }; 10950 10951 struct mlx5_ifc_destroy_vport_lag_out_bits { 10952 u8 status[0x8]; 10953 u8 reserved_at_8[0x18]; 10954 10955 u8 syndrome[0x20]; 10956 10957 u8 reserved_at_40[0x40]; 10958 }; 10959 10960 struct mlx5_ifc_destroy_vport_lag_in_bits { 10961 u8 opcode[0x10]; 10962 u8 reserved_at_10[0x10]; 10963 10964 u8 reserved_at_20[0x10]; 10965 u8 op_mod[0x10]; 10966 10967 u8 reserved_at_40[0x40]; 10968 }; 10969 10970 enum { 10971 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10972 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10973 }; 10974 10975 struct mlx5_ifc_modify_memic_in_bits { 10976 u8 opcode[0x10]; 10977 u8 uid[0x10]; 10978 10979 u8 reserved_at_20[0x10]; 10980 u8 op_mod[0x10]; 10981 10982 u8 reserved_at_40[0x20]; 10983 10984 u8 reserved_at_60[0x18]; 10985 u8 memic_operation_type[0x8]; 10986 10987 u8 memic_start_addr[0x40]; 10988 10989 u8 reserved_at_c0[0x140]; 10990 }; 10991 10992 struct mlx5_ifc_modify_memic_out_bits { 10993 u8 status[0x8]; 10994 u8 reserved_at_8[0x18]; 10995 10996 u8 syndrome[0x20]; 10997 10998 u8 reserved_at_40[0x40]; 10999 11000 u8 memic_operation_addr[0x40]; 11001 11002 u8 reserved_at_c0[0x140]; 11003 }; 11004 11005 struct mlx5_ifc_alloc_memic_in_bits { 11006 u8 opcode[0x10]; 11007 u8 reserved_at_10[0x10]; 11008 11009 u8 reserved_at_20[0x10]; 11010 u8 op_mod[0x10]; 11011 11012 u8 reserved_at_30[0x20]; 11013 11014 u8 reserved_at_40[0x18]; 11015 u8 log_memic_addr_alignment[0x8]; 11016 11017 u8 range_start_addr[0x40]; 11018 11019 u8 range_size[0x20]; 11020 11021 u8 memic_size[0x20]; 11022 }; 11023 11024 struct mlx5_ifc_alloc_memic_out_bits { 11025 u8 status[0x8]; 11026 u8 reserved_at_8[0x18]; 11027 11028 u8 syndrome[0x20]; 11029 11030 u8 memic_start_addr[0x40]; 11031 }; 11032 11033 struct mlx5_ifc_dealloc_memic_in_bits { 11034 u8 opcode[0x10]; 11035 u8 reserved_at_10[0x10]; 11036 11037 u8 reserved_at_20[0x10]; 11038 u8 op_mod[0x10]; 11039 11040 u8 reserved_at_40[0x40]; 11041 11042 u8 memic_start_addr[0x40]; 11043 11044 u8 memic_size[0x20]; 11045 11046 u8 reserved_at_e0[0x20]; 11047 }; 11048 11049 struct mlx5_ifc_dealloc_memic_out_bits { 11050 u8 status[0x8]; 11051 u8 reserved_at_8[0x18]; 11052 11053 u8 syndrome[0x20]; 11054 11055 u8 reserved_at_40[0x40]; 11056 }; 11057 11058 struct mlx5_ifc_umem_bits { 11059 u8 reserved_at_0[0x80]; 11060 11061 u8 reserved_at_80[0x1b]; 11062 u8 log_page_size[0x5]; 11063 11064 u8 page_offset[0x20]; 11065 11066 u8 num_of_mtt[0x40]; 11067 11068 struct mlx5_ifc_mtt_bits mtt[]; 11069 }; 11070 11071 struct mlx5_ifc_uctx_bits { 11072 u8 cap[0x20]; 11073 11074 u8 reserved_at_20[0x160]; 11075 }; 11076 11077 struct mlx5_ifc_sw_icm_bits { 11078 u8 modify_field_select[0x40]; 11079 11080 u8 reserved_at_40[0x18]; 11081 u8 log_sw_icm_size[0x8]; 11082 11083 u8 reserved_at_60[0x20]; 11084 11085 u8 sw_icm_start_addr[0x40]; 11086 11087 u8 reserved_at_c0[0x140]; 11088 }; 11089 11090 struct mlx5_ifc_geneve_tlv_option_bits { 11091 u8 modify_field_select[0x40]; 11092 11093 u8 reserved_at_40[0x18]; 11094 u8 geneve_option_fte_index[0x8]; 11095 11096 u8 option_class[0x10]; 11097 u8 option_type[0x8]; 11098 u8 reserved_at_78[0x3]; 11099 u8 option_data_length[0x5]; 11100 11101 u8 reserved_at_80[0x180]; 11102 }; 11103 11104 struct mlx5_ifc_create_umem_in_bits { 11105 u8 opcode[0x10]; 11106 u8 uid[0x10]; 11107 11108 u8 reserved_at_20[0x10]; 11109 u8 op_mod[0x10]; 11110 11111 u8 reserved_at_40[0x40]; 11112 11113 struct mlx5_ifc_umem_bits umem; 11114 }; 11115 11116 struct mlx5_ifc_create_umem_out_bits { 11117 u8 status[0x8]; 11118 u8 reserved_at_8[0x18]; 11119 11120 u8 syndrome[0x20]; 11121 11122 u8 reserved_at_40[0x8]; 11123 u8 umem_id[0x18]; 11124 11125 u8 reserved_at_60[0x20]; 11126 }; 11127 11128 struct mlx5_ifc_destroy_umem_in_bits { 11129 u8 opcode[0x10]; 11130 u8 uid[0x10]; 11131 11132 u8 reserved_at_20[0x10]; 11133 u8 op_mod[0x10]; 11134 11135 u8 reserved_at_40[0x8]; 11136 u8 umem_id[0x18]; 11137 11138 u8 reserved_at_60[0x20]; 11139 }; 11140 11141 struct mlx5_ifc_destroy_umem_out_bits { 11142 u8 status[0x8]; 11143 u8 reserved_at_8[0x18]; 11144 11145 u8 syndrome[0x20]; 11146 11147 u8 reserved_at_40[0x40]; 11148 }; 11149 11150 struct mlx5_ifc_create_uctx_in_bits { 11151 u8 opcode[0x10]; 11152 u8 reserved_at_10[0x10]; 11153 11154 u8 reserved_at_20[0x10]; 11155 u8 op_mod[0x10]; 11156 11157 u8 reserved_at_40[0x40]; 11158 11159 struct mlx5_ifc_uctx_bits uctx; 11160 }; 11161 11162 struct mlx5_ifc_create_uctx_out_bits { 11163 u8 status[0x8]; 11164 u8 reserved_at_8[0x18]; 11165 11166 u8 syndrome[0x20]; 11167 11168 u8 reserved_at_40[0x10]; 11169 u8 uid[0x10]; 11170 11171 u8 reserved_at_60[0x20]; 11172 }; 11173 11174 struct mlx5_ifc_destroy_uctx_in_bits { 11175 u8 opcode[0x10]; 11176 u8 reserved_at_10[0x10]; 11177 11178 u8 reserved_at_20[0x10]; 11179 u8 op_mod[0x10]; 11180 11181 u8 reserved_at_40[0x10]; 11182 u8 uid[0x10]; 11183 11184 u8 reserved_at_60[0x20]; 11185 }; 11186 11187 struct mlx5_ifc_destroy_uctx_out_bits { 11188 u8 status[0x8]; 11189 u8 reserved_at_8[0x18]; 11190 11191 u8 syndrome[0x20]; 11192 11193 u8 reserved_at_40[0x40]; 11194 }; 11195 11196 struct mlx5_ifc_create_sw_icm_in_bits { 11197 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11198 struct mlx5_ifc_sw_icm_bits sw_icm; 11199 }; 11200 11201 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11202 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11203 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11204 }; 11205 11206 struct mlx5_ifc_mtrc_string_db_param_bits { 11207 u8 string_db_base_address[0x20]; 11208 11209 u8 reserved_at_20[0x8]; 11210 u8 string_db_size[0x18]; 11211 }; 11212 11213 struct mlx5_ifc_mtrc_cap_bits { 11214 u8 trace_owner[0x1]; 11215 u8 trace_to_memory[0x1]; 11216 u8 reserved_at_2[0x4]; 11217 u8 trc_ver[0x2]; 11218 u8 reserved_at_8[0x14]; 11219 u8 num_string_db[0x4]; 11220 11221 u8 first_string_trace[0x8]; 11222 u8 num_string_trace[0x8]; 11223 u8 reserved_at_30[0x28]; 11224 11225 u8 log_max_trace_buffer_size[0x8]; 11226 11227 u8 reserved_at_60[0x20]; 11228 11229 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11230 11231 u8 reserved_at_280[0x180]; 11232 }; 11233 11234 struct mlx5_ifc_mtrc_conf_bits { 11235 u8 reserved_at_0[0x1c]; 11236 u8 trace_mode[0x4]; 11237 u8 reserved_at_20[0x18]; 11238 u8 log_trace_buffer_size[0x8]; 11239 u8 trace_mkey[0x20]; 11240 u8 reserved_at_60[0x3a0]; 11241 }; 11242 11243 struct mlx5_ifc_mtrc_stdb_bits { 11244 u8 string_db_index[0x4]; 11245 u8 reserved_at_4[0x4]; 11246 u8 read_size[0x18]; 11247 u8 start_offset[0x20]; 11248 u8 string_db_data[]; 11249 }; 11250 11251 struct mlx5_ifc_mtrc_ctrl_bits { 11252 u8 trace_status[0x2]; 11253 u8 reserved_at_2[0x2]; 11254 u8 arm_event[0x1]; 11255 u8 reserved_at_5[0xb]; 11256 u8 modify_field_select[0x10]; 11257 u8 reserved_at_20[0x2b]; 11258 u8 current_timestamp52_32[0x15]; 11259 u8 current_timestamp31_0[0x20]; 11260 u8 reserved_at_80[0x180]; 11261 }; 11262 11263 struct mlx5_ifc_host_params_context_bits { 11264 u8 host_number[0x8]; 11265 u8 reserved_at_8[0x7]; 11266 u8 host_pf_disabled[0x1]; 11267 u8 host_num_of_vfs[0x10]; 11268 11269 u8 host_total_vfs[0x10]; 11270 u8 host_pci_bus[0x10]; 11271 11272 u8 reserved_at_40[0x10]; 11273 u8 host_pci_device[0x10]; 11274 11275 u8 reserved_at_60[0x10]; 11276 u8 host_pci_function[0x10]; 11277 11278 u8 reserved_at_80[0x180]; 11279 }; 11280 11281 struct mlx5_ifc_query_esw_functions_in_bits { 11282 u8 opcode[0x10]; 11283 u8 reserved_at_10[0x10]; 11284 11285 u8 reserved_at_20[0x10]; 11286 u8 op_mod[0x10]; 11287 11288 u8 reserved_at_40[0x40]; 11289 }; 11290 11291 struct mlx5_ifc_query_esw_functions_out_bits { 11292 u8 status[0x8]; 11293 u8 reserved_at_8[0x18]; 11294 11295 u8 syndrome[0x20]; 11296 11297 u8 reserved_at_40[0x40]; 11298 11299 struct mlx5_ifc_host_params_context_bits host_params_context; 11300 11301 u8 reserved_at_280[0x180]; 11302 u8 host_sf_enable[][0x40]; 11303 }; 11304 11305 struct mlx5_ifc_sf_partition_bits { 11306 u8 reserved_at_0[0x10]; 11307 u8 log_num_sf[0x8]; 11308 u8 log_sf_bar_size[0x8]; 11309 }; 11310 11311 struct mlx5_ifc_query_sf_partitions_out_bits { 11312 u8 status[0x8]; 11313 u8 reserved_at_8[0x18]; 11314 11315 u8 syndrome[0x20]; 11316 11317 u8 reserved_at_40[0x18]; 11318 u8 num_sf_partitions[0x8]; 11319 11320 u8 reserved_at_60[0x20]; 11321 11322 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11323 }; 11324 11325 struct mlx5_ifc_query_sf_partitions_in_bits { 11326 u8 opcode[0x10]; 11327 u8 reserved_at_10[0x10]; 11328 11329 u8 reserved_at_20[0x10]; 11330 u8 op_mod[0x10]; 11331 11332 u8 reserved_at_40[0x40]; 11333 }; 11334 11335 struct mlx5_ifc_dealloc_sf_out_bits { 11336 u8 status[0x8]; 11337 u8 reserved_at_8[0x18]; 11338 11339 u8 syndrome[0x20]; 11340 11341 u8 reserved_at_40[0x40]; 11342 }; 11343 11344 struct mlx5_ifc_dealloc_sf_in_bits { 11345 u8 opcode[0x10]; 11346 u8 reserved_at_10[0x10]; 11347 11348 u8 reserved_at_20[0x10]; 11349 u8 op_mod[0x10]; 11350 11351 u8 reserved_at_40[0x10]; 11352 u8 function_id[0x10]; 11353 11354 u8 reserved_at_60[0x20]; 11355 }; 11356 11357 struct mlx5_ifc_alloc_sf_out_bits { 11358 u8 status[0x8]; 11359 u8 reserved_at_8[0x18]; 11360 11361 u8 syndrome[0x20]; 11362 11363 u8 reserved_at_40[0x40]; 11364 }; 11365 11366 struct mlx5_ifc_alloc_sf_in_bits { 11367 u8 opcode[0x10]; 11368 u8 reserved_at_10[0x10]; 11369 11370 u8 reserved_at_20[0x10]; 11371 u8 op_mod[0x10]; 11372 11373 u8 reserved_at_40[0x10]; 11374 u8 function_id[0x10]; 11375 11376 u8 reserved_at_60[0x20]; 11377 }; 11378 11379 struct mlx5_ifc_affiliated_event_header_bits { 11380 u8 reserved_at_0[0x10]; 11381 u8 obj_type[0x10]; 11382 11383 u8 obj_id[0x20]; 11384 }; 11385 11386 enum { 11387 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11388 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11389 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11390 }; 11391 11392 enum { 11393 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11394 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11395 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11396 }; 11397 11398 enum { 11399 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11400 }; 11401 11402 struct mlx5_ifc_ipsec_obj_bits { 11403 u8 modify_field_select[0x40]; 11404 u8 full_offload[0x1]; 11405 u8 reserved_at_41[0x1]; 11406 u8 esn_en[0x1]; 11407 u8 esn_overlap[0x1]; 11408 u8 reserved_at_44[0x2]; 11409 u8 icv_length[0x2]; 11410 u8 reserved_at_48[0x4]; 11411 u8 aso_return_reg[0x4]; 11412 u8 reserved_at_50[0x10]; 11413 11414 u8 esn_msb[0x20]; 11415 11416 u8 reserved_at_80[0x8]; 11417 u8 dekn[0x18]; 11418 11419 u8 salt[0x20]; 11420 11421 u8 implicit_iv[0x40]; 11422 11423 u8 reserved_at_100[0x700]; 11424 }; 11425 11426 struct mlx5_ifc_create_ipsec_obj_in_bits { 11427 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11428 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11429 }; 11430 11431 enum { 11432 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11433 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11434 }; 11435 11436 struct mlx5_ifc_query_ipsec_obj_out_bits { 11437 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11438 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11439 }; 11440 11441 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11442 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11443 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11444 }; 11445 11446 struct mlx5_ifc_encryption_key_obj_bits { 11447 u8 modify_field_select[0x40]; 11448 11449 u8 reserved_at_40[0x14]; 11450 u8 key_size[0x4]; 11451 u8 reserved_at_58[0x4]; 11452 u8 key_type[0x4]; 11453 11454 u8 reserved_at_60[0x8]; 11455 u8 pd[0x18]; 11456 11457 u8 reserved_at_80[0x180]; 11458 u8 key[8][0x20]; 11459 11460 u8 reserved_at_300[0x500]; 11461 }; 11462 11463 struct mlx5_ifc_create_encryption_key_in_bits { 11464 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11465 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11466 }; 11467 11468 struct mlx5_ifc_sampler_obj_bits { 11469 u8 modify_field_select[0x40]; 11470 11471 u8 table_type[0x8]; 11472 u8 level[0x8]; 11473 u8 reserved_at_50[0xf]; 11474 u8 ignore_flow_level[0x1]; 11475 11476 u8 sample_ratio[0x20]; 11477 11478 u8 reserved_at_80[0x8]; 11479 u8 sample_table_id[0x18]; 11480 11481 u8 reserved_at_a0[0x8]; 11482 u8 default_table_id[0x18]; 11483 11484 u8 sw_steering_icm_address_rx[0x40]; 11485 u8 sw_steering_icm_address_tx[0x40]; 11486 11487 u8 reserved_at_140[0xa0]; 11488 }; 11489 11490 struct mlx5_ifc_create_sampler_obj_in_bits { 11491 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11492 struct mlx5_ifc_sampler_obj_bits sampler_object; 11493 }; 11494 11495 struct mlx5_ifc_query_sampler_obj_out_bits { 11496 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11497 struct mlx5_ifc_sampler_obj_bits sampler_object; 11498 }; 11499 11500 enum { 11501 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11502 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11503 }; 11504 11505 enum { 11506 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11507 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11508 }; 11509 11510 struct mlx5_ifc_tls_static_params_bits { 11511 u8 const_2[0x2]; 11512 u8 tls_version[0x4]; 11513 u8 const_1[0x2]; 11514 u8 reserved_at_8[0x14]; 11515 u8 encryption_standard[0x4]; 11516 11517 u8 reserved_at_20[0x20]; 11518 11519 u8 initial_record_number[0x40]; 11520 11521 u8 resync_tcp_sn[0x20]; 11522 11523 u8 gcm_iv[0x20]; 11524 11525 u8 implicit_iv[0x40]; 11526 11527 u8 reserved_at_100[0x8]; 11528 u8 dek_index[0x18]; 11529 11530 u8 reserved_at_120[0xe0]; 11531 }; 11532 11533 struct mlx5_ifc_tls_progress_params_bits { 11534 u8 next_record_tcp_sn[0x20]; 11535 11536 u8 hw_resync_tcp_sn[0x20]; 11537 11538 u8 record_tracker_state[0x2]; 11539 u8 auth_state[0x2]; 11540 u8 reserved_at_44[0x4]; 11541 u8 hw_offset_record_number[0x18]; 11542 }; 11543 11544 enum { 11545 MLX5_MTT_PERM_READ = 1 << 0, 11546 MLX5_MTT_PERM_WRITE = 1 << 1, 11547 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11548 }; 11549 11550 enum { 11551 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11552 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11553 }; 11554 11555 struct mlx5_ifc_suspend_vhca_in_bits { 11556 u8 opcode[0x10]; 11557 u8 uid[0x10]; 11558 11559 u8 reserved_at_20[0x10]; 11560 u8 op_mod[0x10]; 11561 11562 u8 reserved_at_40[0x10]; 11563 u8 vhca_id[0x10]; 11564 11565 u8 reserved_at_60[0x20]; 11566 }; 11567 11568 struct mlx5_ifc_suspend_vhca_out_bits { 11569 u8 status[0x8]; 11570 u8 reserved_at_8[0x18]; 11571 11572 u8 syndrome[0x20]; 11573 11574 u8 reserved_at_40[0x40]; 11575 }; 11576 11577 enum { 11578 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11579 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11580 }; 11581 11582 struct mlx5_ifc_resume_vhca_in_bits { 11583 u8 opcode[0x10]; 11584 u8 uid[0x10]; 11585 11586 u8 reserved_at_20[0x10]; 11587 u8 op_mod[0x10]; 11588 11589 u8 reserved_at_40[0x10]; 11590 u8 vhca_id[0x10]; 11591 11592 u8 reserved_at_60[0x20]; 11593 }; 11594 11595 struct mlx5_ifc_resume_vhca_out_bits { 11596 u8 status[0x8]; 11597 u8 reserved_at_8[0x18]; 11598 11599 u8 syndrome[0x20]; 11600 11601 u8 reserved_at_40[0x40]; 11602 }; 11603 11604 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11605 u8 opcode[0x10]; 11606 u8 uid[0x10]; 11607 11608 u8 reserved_at_20[0x10]; 11609 u8 op_mod[0x10]; 11610 11611 u8 reserved_at_40[0x10]; 11612 u8 vhca_id[0x10]; 11613 11614 u8 reserved_at_60[0x20]; 11615 }; 11616 11617 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11618 u8 status[0x8]; 11619 u8 reserved_at_8[0x18]; 11620 11621 u8 syndrome[0x20]; 11622 11623 u8 reserved_at_40[0x40]; 11624 11625 u8 required_umem_size[0x20]; 11626 11627 u8 reserved_at_a0[0x160]; 11628 }; 11629 11630 struct mlx5_ifc_save_vhca_state_in_bits { 11631 u8 opcode[0x10]; 11632 u8 uid[0x10]; 11633 11634 u8 reserved_at_20[0x10]; 11635 u8 op_mod[0x10]; 11636 11637 u8 reserved_at_40[0x10]; 11638 u8 vhca_id[0x10]; 11639 11640 u8 reserved_at_60[0x20]; 11641 11642 u8 va[0x40]; 11643 11644 u8 mkey[0x20]; 11645 11646 u8 size[0x20]; 11647 }; 11648 11649 struct mlx5_ifc_save_vhca_state_out_bits { 11650 u8 status[0x8]; 11651 u8 reserved_at_8[0x18]; 11652 11653 u8 syndrome[0x20]; 11654 11655 u8 actual_image_size[0x20]; 11656 11657 u8 reserved_at_60[0x20]; 11658 }; 11659 11660 struct mlx5_ifc_load_vhca_state_in_bits { 11661 u8 opcode[0x10]; 11662 u8 uid[0x10]; 11663 11664 u8 reserved_at_20[0x10]; 11665 u8 op_mod[0x10]; 11666 11667 u8 reserved_at_40[0x10]; 11668 u8 vhca_id[0x10]; 11669 11670 u8 reserved_at_60[0x20]; 11671 11672 u8 va[0x40]; 11673 11674 u8 mkey[0x20]; 11675 11676 u8 size[0x20]; 11677 }; 11678 11679 struct mlx5_ifc_load_vhca_state_out_bits { 11680 u8 status[0x8]; 11681 u8 reserved_at_8[0x18]; 11682 11683 u8 syndrome[0x20]; 11684 11685 u8 reserved_at_40[0x40]; 11686 }; 11687 11688 #endif /* MLX5_IFC_H */ 11689