1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _D11_H 18 #define _D11_H 19 20 #ifndef WL_RSSI_ANT_MAX 21 #define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */ 22 #elif WL_RSSI_ANT_MAX != 4 23 #error "WL_RSSI_ANT_MAX does not match" 24 #endif 25 26 /* cpp contortions to concatenate w/arg prescan */ 27 #ifndef PAD 28 #define _PADLINE(line) pad ## line 29 #define _XSTR(line) _PADLINE(line) 30 #define PAD _XSTR(__LINE__) 31 #endif 32 33 #define BCN_TMPL_LEN 512 /* length of the BCN template area */ 34 35 /* RX FIFO numbers */ 36 #define RX_FIFO 0 /* data and ctl frames */ 37 #define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */ 38 39 /* TX FIFO numbers using WME Access Classes */ 40 #define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */ 41 #define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */ 42 #define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */ 43 #define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */ 44 #define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */ 45 #define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */ 46 47 /* Addr is byte address used by SW; offset is word offset used by uCode */ 48 49 /* Per AC TX limit settings */ 50 #define M_AC_TXLMT_BASE_ADDR (0x180 * 2) 51 #define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac))) 52 53 /* Legacy TX FIFO numbers */ 54 #define TX_DATA_FIFO TX_AC_BE_FIFO 55 #define TX_CTL_FIFO TX_AC_VO_FIFO 56 57 typedef volatile struct { 58 u32 intstatus; 59 u32 intmask; 60 } intctrlregs_t; 61 62 /* PIO structure, 63 * support two PIO format: 2 bytes access and 4 bytes access 64 * basic FIFO register set is per channel(transmit or receive) 65 * a pair of channels is defined for convenience 66 */ 67 /* 2byte-wide pio register set per channel(xmt or rcv) */ 68 typedef volatile struct { 69 u16 fifocontrol; 70 u16 fifodata; 71 u16 fifofree; /* only valid in xmt channel, not in rcv channel */ 72 u16 PAD; 73 } pio2regs_t; 74 75 /* a pair of pio channels(tx and rx) */ 76 typedef volatile struct { 77 pio2regs_t tx; 78 pio2regs_t rx; 79 } pio2regp_t; 80 81 /* 4byte-wide pio register set per channel(xmt or rcv) */ 82 typedef volatile struct { 83 u32 fifocontrol; 84 u32 fifodata; 85 } pio4regs_t; 86 87 /* a pair of pio channels(tx and rx) */ 88 typedef volatile struct { 89 pio4regs_t tx; 90 pio4regs_t rx; 91 } pio4regp_t; 92 93 /* read: 32-bit register that can be read as 32-bit or as 2 16-bit 94 * write: only low 16b-it half can be written 95 */ 96 typedef volatile union { 97 u32 pmqhostdata; /* read only! */ 98 struct { 99 u16 pmqctrlstatus; /* read/write */ 100 u16 PAD; 101 } w; 102 } pmqreg_t; 103 104 typedef volatile struct { 105 dma64regs_t dmaxmt; /* dma tx */ 106 pio4regs_t piotx; /* pio tx */ 107 dma64regs_t dmarcv; /* dma rx */ 108 pio4regs_t piorx; /* pio rx */ 109 } fifo64_t; 110 111 /* 112 * Host Interface Registers 113 * - primed from hnd_cores/dot11mac/systemC/registers/ihr.h 114 * - but definitely not complete 115 */ 116 typedef volatile struct _d11regs { 117 /* Device Control ("semi-standard host registers") */ 118 u32 PAD[3]; /* 0x0 - 0x8 */ 119 u32 biststatus; /* 0xC */ 120 u32 biststatus2; /* 0x10 */ 121 u32 PAD; /* 0x14 */ 122 u32 gptimer; /* 0x18 */ 123 u32 usectimer; /* 0x1c *//* for corerev >= 26 */ 124 125 /* Interrupt Control *//* 0x20 */ 126 intctrlregs_t intctrlregs[8]; 127 128 u32 PAD[40]; /* 0x60 - 0xFC */ 129 130 u32 intrcvlazy[4]; /* 0x100 - 0x10C */ 131 132 u32 PAD[4]; /* 0x110 - 0x11c */ 133 134 u32 maccontrol; /* 0x120 */ 135 u32 maccommand; /* 0x124 */ 136 u32 macintstatus; /* 0x128 */ 137 u32 macintmask; /* 0x12C */ 138 139 /* Transmit Template Access */ 140 u32 tplatewrptr; /* 0x130 */ 141 u32 tplatewrdata; /* 0x134 */ 142 u32 PAD[2]; /* 0x138 - 0x13C */ 143 144 /* PMQ registers */ 145 pmqreg_t pmqreg; /* 0x140 */ 146 u32 pmqpatl; /* 0x144 */ 147 u32 pmqpath; /* 0x148 */ 148 u32 PAD; /* 0x14C */ 149 150 u32 chnstatus; /* 0x150 */ 151 u32 psmdebug; /* 0x154 */ 152 u32 phydebug; /* 0x158 */ 153 u32 machwcap; /* 0x15C */ 154 155 /* Extended Internal Objects */ 156 u32 objaddr; /* 0x160 */ 157 u32 objdata; /* 0x164 */ 158 u32 PAD[2]; /* 0x168 - 0x16c */ 159 160 u32 frmtxstatus; /* 0x170 */ 161 u32 frmtxstatus2; /* 0x174 */ 162 u32 PAD[2]; /* 0x178 - 0x17c */ 163 164 /* TSF host access */ 165 u32 tsf_timerlow; /* 0x180 */ 166 u32 tsf_timerhigh; /* 0x184 */ 167 u32 tsf_cfprep; /* 0x188 */ 168 u32 tsf_cfpstart; /* 0x18c */ 169 u32 tsf_cfpmaxdur32; /* 0x190 */ 170 u32 PAD[3]; /* 0x194 - 0x19c */ 171 172 u32 maccontrol1; /* 0x1a0 */ 173 u32 machwcap1; /* 0x1a4 */ 174 u32 PAD[14]; /* 0x1a8 - 0x1dc */ 175 176 /* Clock control and hardware workarounds*/ 177 u32 clk_ctl_st; /* 0x1e0 */ 178 u32 hw_war; 179 u32 d11_phypllctl; /* the phypll request/avail bits are 180 * moved to clk_ctl_st 181 */ 182 u32 PAD[5]; /* 0x1ec - 0x1fc */ 183 184 /* 0x200-0x37F dma/pio registers */ 185 fifo64_t fifo64regs[6]; 186 187 /* FIFO diagnostic port access */ 188 dma32diag_t dmafifo; /* 0x380 - 0x38C */ 189 190 u32 aggfifocnt; /* 0x390 */ 191 u32 aggfifodata; /* 0x394 */ 192 u32 PAD[16]; /* 0x398 - 0x3d4 */ 193 u16 radioregaddr; /* 0x3d8 */ 194 u16 radioregdata; /* 0x3da */ 195 196 /* 197 * time delay between the change on rf disable input and 198 * radio shutdown 199 */ 200 u32 rfdisabledly; /* 0x3DC */ 201 202 /* PHY register access */ 203 u16 phyversion; /* 0x3e0 - 0x0 */ 204 u16 phybbconfig; /* 0x3e2 - 0x1 */ 205 u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */ 206 u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */ 207 u16 phyrxstatus0; /* 0x3e8 - 0x4 */ 208 u16 phyrxstatus1; /* 0x3ea - 0x5 */ 209 u16 phycrsth; /* 0x3ec - 0x6 */ 210 u16 phytxerror; /* 0x3ee - 0x7 */ 211 u16 phychannel; /* 0x3f0 - 0x8 */ 212 u16 PAD[1]; /* 0x3f2 - 0x9 */ 213 u16 phytest; /* 0x3f4 - 0xa */ 214 u16 phy4waddr; /* 0x3f6 - 0xb */ 215 u16 phy4wdatahi; /* 0x3f8 - 0xc */ 216 u16 phy4wdatalo; /* 0x3fa - 0xd */ 217 u16 phyregaddr; /* 0x3fc - 0xe */ 218 u16 phyregdata; /* 0x3fe - 0xf */ 219 220 /* IHR *//* 0x400 - 0x7FE */ 221 222 /* RXE Block */ 223 u16 PAD[3]; /* 0x400 - 0x406 */ 224 u16 rcv_fifo_ctl; /* 0x406 */ 225 u16 PAD; /* 0x408 - 0x40a */ 226 u16 rcv_frm_cnt; /* 0x40a */ 227 u16 PAD[4]; /* 0x40a - 0x414 */ 228 u16 rssi; /* 0x414 */ 229 u16 PAD[5]; /* 0x414 - 0x420 */ 230 u16 rcm_ctl; /* 0x420 */ 231 u16 rcm_mat_data; /* 0x422 */ 232 u16 rcm_mat_mask; /* 0x424 */ 233 u16 rcm_mat_dly; /* 0x426 */ 234 u16 rcm_cond_mask_l; /* 0x428 */ 235 u16 rcm_cond_mask_h; /* 0x42A */ 236 u16 rcm_cond_dly; /* 0x42C */ 237 u16 PAD[1]; /* 0x42E */ 238 u16 ext_ihr_addr; /* 0x430 */ 239 u16 ext_ihr_data; /* 0x432 */ 240 u16 rxe_phyrs_2; /* 0x434 */ 241 u16 rxe_phyrs_3; /* 0x436 */ 242 u16 phy_mode; /* 0x438 */ 243 u16 rcmta_ctl; /* 0x43a */ 244 u16 rcmta_size; /* 0x43c */ 245 u16 rcmta_addr0; /* 0x43e */ 246 u16 rcmta_addr1; /* 0x440 */ 247 u16 rcmta_addr2; /* 0x442 */ 248 u16 PAD[30]; /* 0x444 - 0x480 */ 249 250 /* PSM Block *//* 0x480 - 0x500 */ 251 252 u16 PAD; /* 0x480 */ 253 u16 psm_maccontrol_h; /* 0x482 */ 254 u16 psm_macintstatus_l; /* 0x484 */ 255 u16 psm_macintstatus_h; /* 0x486 */ 256 u16 psm_macintmask_l; /* 0x488 */ 257 u16 psm_macintmask_h; /* 0x48A */ 258 u16 PAD; /* 0x48C */ 259 u16 psm_maccommand; /* 0x48E */ 260 u16 psm_brc; /* 0x490 */ 261 u16 psm_phy_hdr_param; /* 0x492 */ 262 u16 psm_postcard; /* 0x494 */ 263 u16 psm_pcard_loc_l; /* 0x496 */ 264 u16 psm_pcard_loc_h; /* 0x498 */ 265 u16 psm_gpio_in; /* 0x49A */ 266 u16 psm_gpio_out; /* 0x49C */ 267 u16 psm_gpio_oe; /* 0x49E */ 268 269 u16 psm_bred_0; /* 0x4A0 */ 270 u16 psm_bred_1; /* 0x4A2 */ 271 u16 psm_bred_2; /* 0x4A4 */ 272 u16 psm_bred_3; /* 0x4A6 */ 273 u16 psm_brcl_0; /* 0x4A8 */ 274 u16 psm_brcl_1; /* 0x4AA */ 275 u16 psm_brcl_2; /* 0x4AC */ 276 u16 psm_brcl_3; /* 0x4AE */ 277 u16 psm_brpo_0; /* 0x4B0 */ 278 u16 psm_brpo_1; /* 0x4B2 */ 279 u16 psm_brpo_2; /* 0x4B4 */ 280 u16 psm_brpo_3; /* 0x4B6 */ 281 u16 psm_brwk_0; /* 0x4B8 */ 282 u16 psm_brwk_1; /* 0x4BA */ 283 u16 psm_brwk_2; /* 0x4BC */ 284 u16 psm_brwk_3; /* 0x4BE */ 285 286 u16 psm_base_0; /* 0x4C0 */ 287 u16 psm_base_1; /* 0x4C2 */ 288 u16 psm_base_2; /* 0x4C4 */ 289 u16 psm_base_3; /* 0x4C6 */ 290 u16 psm_base_4; /* 0x4C8 */ 291 u16 psm_base_5; /* 0x4CA */ 292 u16 psm_base_6; /* 0x4CC */ 293 u16 psm_pc_reg_0; /* 0x4CE */ 294 u16 psm_pc_reg_1; /* 0x4D0 */ 295 u16 psm_pc_reg_2; /* 0x4D2 */ 296 u16 psm_pc_reg_3; /* 0x4D4 */ 297 u16 PAD[0xD]; /* 0x4D6 - 0x4DE */ 298 u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */ 299 u16 PAD[0x7]; /* 0x4f2 - 0x4fE */ 300 301 /* TXE0 Block *//* 0x500 - 0x580 */ 302 u16 txe_ctl; /* 0x500 */ 303 u16 txe_aux; /* 0x502 */ 304 u16 txe_ts_loc; /* 0x504 */ 305 u16 txe_time_out; /* 0x506 */ 306 u16 txe_wm_0; /* 0x508 */ 307 u16 txe_wm_1; /* 0x50A */ 308 u16 txe_phyctl; /* 0x50C */ 309 u16 txe_status; /* 0x50E */ 310 u16 txe_mmplcp0; /* 0x510 */ 311 u16 txe_mmplcp1; /* 0x512 */ 312 u16 txe_phyctl1; /* 0x514 */ 313 314 u16 PAD[0x05]; /* 0x510 - 0x51E */ 315 316 /* Transmit control */ 317 u16 xmtfifodef; /* 0x520 */ 318 u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */ 319 u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */ 320 u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */ 321 u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */ 322 u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */ 323 u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */ 324 325 u16 PAD[0x09]; /* 0x52E - 0x53E */ 326 327 u16 xmtfifocmd; /* 0x540 */ 328 u16 xmtfifoflush; /* 0x542 */ 329 u16 xmtfifothresh; /* 0x544 */ 330 u16 xmtfifordy; /* 0x546 */ 331 u16 xmtfifoprirdy; /* 0x548 */ 332 u16 xmtfiforqpri; /* 0x54A */ 333 u16 xmttplatetxptr; /* 0x54C */ 334 u16 PAD; /* 0x54E */ 335 u16 xmttplateptr; /* 0x550 */ 336 u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */ 337 u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */ 338 u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */ 339 u16 PAD[0x04]; /* 0x558 - 0x55E */ 340 u16 xmttplatedatalo; /* 0x560 */ 341 u16 xmttplatedatahi; /* 0x562 */ 342 343 u16 PAD[2]; /* 0x564 - 0x566 */ 344 345 u16 xmtsel; /* 0x568 */ 346 u16 xmttxcnt; /* 0x56A */ 347 u16 xmttxshmaddr; /* 0x56C */ 348 349 u16 PAD[0x09]; /* 0x56E - 0x57E */ 350 351 /* TXE1 Block */ 352 u16 PAD[0x40]; /* 0x580 - 0x5FE */ 353 354 /* TSF Block */ 355 u16 PAD[0X02]; /* 0x600 - 0x602 */ 356 u16 tsf_cfpstrt_l; /* 0x604 */ 357 u16 tsf_cfpstrt_h; /* 0x606 */ 358 u16 PAD[0X05]; /* 0x608 - 0x610 */ 359 u16 tsf_cfppretbtt; /* 0x612 */ 360 u16 PAD[0XD]; /* 0x614 - 0x62C */ 361 u16 tsf_clk_frac_l; /* 0x62E */ 362 u16 tsf_clk_frac_h; /* 0x630 */ 363 u16 PAD[0X14]; /* 0x632 - 0x658 */ 364 u16 tsf_random; /* 0x65A */ 365 u16 PAD[0x05]; /* 0x65C - 0x664 */ 366 /* GPTimer 2 registers */ 367 u16 tsf_gpt2_stat; /* 0x666 */ 368 u16 tsf_gpt2_ctr_l; /* 0x668 */ 369 u16 tsf_gpt2_ctr_h; /* 0x66A */ 370 u16 tsf_gpt2_val_l; /* 0x66C */ 371 u16 tsf_gpt2_val_h; /* 0x66E */ 372 u16 tsf_gptall_stat; /* 0x670 */ 373 u16 PAD[0x07]; /* 0x672 - 0x67E */ 374 375 /* IFS Block */ 376 u16 ifs_sifs_rx_tx_tx; /* 0x680 */ 377 u16 ifs_sifs_nav_tx; /* 0x682 */ 378 u16 ifs_slot; /* 0x684 */ 379 u16 PAD; /* 0x686 */ 380 u16 ifs_ctl; /* 0x688 */ 381 u16 PAD[0x3]; /* 0x68a - 0x68F */ 382 u16 ifsstat; /* 0x690 */ 383 u16 ifsmedbusyctl; /* 0x692 */ 384 u16 iftxdur; /* 0x694 */ 385 u16 PAD[0x3]; /* 0x696 - 0x69b */ 386 /* EDCF support in dot11macs */ 387 u16 ifs_aifsn; /* 0x69c */ 388 u16 ifs_ctl1; /* 0x69e */ 389 390 /* slow clock registers */ 391 u16 scc_ctl; /* 0x6a0 */ 392 u16 scc_timer_l; /* 0x6a2 */ 393 u16 scc_timer_h; /* 0x6a4 */ 394 u16 scc_frac; /* 0x6a6 */ 395 u16 scc_fastpwrup_dly; /* 0x6a8 */ 396 u16 scc_per; /* 0x6aa */ 397 u16 scc_per_frac; /* 0x6ac */ 398 u16 scc_cal_timer_l; /* 0x6ae */ 399 u16 scc_cal_timer_h; /* 0x6b0 */ 400 u16 PAD; /* 0x6b2 */ 401 402 u16 PAD[0x26]; 403 404 /* NAV Block */ 405 u16 nav_ctl; /* 0x700 */ 406 u16 navstat; /* 0x702 */ 407 u16 PAD[0x3e]; /* 0x702 - 0x77E */ 408 409 /* WEP/PMQ Block *//* 0x780 - 0x7FE */ 410 u16 PAD[0x20]; /* 0x780 - 0x7BE */ 411 412 u16 wepctl; /* 0x7C0 */ 413 u16 wepivloc; /* 0x7C2 */ 414 u16 wepivkey; /* 0x7C4 */ 415 u16 wepwkey; /* 0x7C6 */ 416 417 u16 PAD[4]; /* 0x7C8 - 0x7CE */ 418 u16 pcmctl; /* 0X7D0 */ 419 u16 pcmstat; /* 0X7D2 */ 420 u16 PAD[6]; /* 0x7D4 - 0x7DE */ 421 422 u16 pmqctl; /* 0x7E0 */ 423 u16 pmqstatus; /* 0x7E2 */ 424 u16 pmqpat0; /* 0x7E4 */ 425 u16 pmqpat1; /* 0x7E6 */ 426 u16 pmqpat2; /* 0x7E8 */ 427 428 u16 pmqdat; /* 0x7EA */ 429 u16 pmqdator; /* 0x7EC */ 430 u16 pmqhst; /* 0x7EE */ 431 u16 pmqpath0; /* 0x7F0 */ 432 u16 pmqpath1; /* 0x7F2 */ 433 u16 pmqpath2; /* 0x7F4 */ 434 u16 pmqdath; /* 0x7F6 */ 435 436 u16 PAD[0x04]; /* 0x7F8 - 0x7FE */ 437 438 /* SHM *//* 0x800 - 0xEFE */ 439 u16 PAD[0x380]; /* 0x800 - 0xEFE */ 440 441 /* SB configuration registers: 0xF00 */ 442 sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */ 443 } d11regs_t; 444 445 #define PIHR_BASE 0x0400 /* byte address of packed IHR region */ 446 447 /* biststatus */ 448 #define BT_DONE (1U << 31) /* bist done */ 449 #define BT_B2S (1 << 30) /* bist2 ram summary bit */ 450 451 /* intstatus and intmask */ 452 #define I_PC (1 << 10) /* pci descriptor error */ 453 #define I_PD (1 << 11) /* pci data error */ 454 #define I_DE (1 << 12) /* descriptor protocol error */ 455 #define I_RU (1 << 13) /* receive descriptor underflow */ 456 #define I_RO (1 << 14) /* receive fifo overflow */ 457 #define I_XU (1 << 15) /* transmit fifo underflow */ 458 #define I_RI (1 << 16) /* receive interrupt */ 459 #define I_XI (1 << 24) /* transmit interrupt */ 460 461 /* interrupt receive lazy */ 462 #define IRL_TO_MASK 0x00ffffff /* timeout */ 463 #define IRL_FC_MASK 0xff000000 /* frame count */ 464 #define IRL_FC_SHIFT 24 /* frame count */ 465 466 /* maccontrol register */ 467 #define MCTL_GMODE (1U << 31) 468 #define MCTL_DISCARD_PMQ (1 << 30) 469 #define MCTL_WAKE (1 << 26) 470 #define MCTL_HPS (1 << 25) 471 #define MCTL_PROMISC (1 << 24) 472 #define MCTL_KEEPBADFCS (1 << 23) 473 #define MCTL_KEEPCONTROL (1 << 22) 474 #define MCTL_PHYLOCK (1 << 21) 475 #define MCTL_BCNS_PROMISC (1 << 20) 476 #define MCTL_LOCK_RADIO (1 << 19) 477 #define MCTL_AP (1 << 18) 478 #define MCTL_INFRA (1 << 17) 479 #define MCTL_BIGEND (1 << 16) 480 #define MCTL_GPOUT_SEL_MASK (3 << 14) 481 #define MCTL_GPOUT_SEL_SHIFT 14 482 #define MCTL_EN_PSMDBG (1 << 13) 483 #define MCTL_IHR_EN (1 << 10) 484 #define MCTL_SHM_UPPER (1 << 9) 485 #define MCTL_SHM_EN (1 << 8) 486 #define MCTL_PSM_JMP_0 (1 << 2) 487 #define MCTL_PSM_RUN (1 << 1) 488 #define MCTL_EN_MAC (1 << 0) 489 490 /* maccommand register */ 491 #define MCMD_BCN0VLD (1 << 0) 492 #define MCMD_BCN1VLD (1 << 1) 493 #define MCMD_DIRFRMQVAL (1 << 2) 494 #define MCMD_CCA (1 << 3) 495 #define MCMD_BG_NOISE (1 << 4) 496 #define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */ 497 #define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */ 498 499 /* macintstatus/macintmask */ 500 #define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */ 501 #define MI_BCNTPL (1 << 1) /* beacon template available */ 502 #define MI_TBTT (1 << 2) /* TBTT indication */ 503 #define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */ 504 #define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */ 505 #define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */ 506 #define MI_PMQ (1 << 6) /* PMQ entries available */ 507 #define MI_NSPECGEN_0 (1 << 7) /* non-specific gen-stat bits that are set by PSM */ 508 #define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */ 509 #define MI_MACTXERR (1 << 9) /* MAC level Tx error */ 510 #define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */ 511 #define MI_PHYTXERR (1 << 11) /* PHY Tx error */ 512 #define MI_PME (1 << 12) /* Power Management Event */ 513 #define MI_GP0 (1 << 13) /* General-purpose timer0 */ 514 #define MI_GP1 (1 << 14) /* General-purpose timer1 */ 515 #define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */ 516 #define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */ 517 #define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */ 518 #define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */ 519 #define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */ 520 #define MI_PRQ (1 << 20) /* Probe response queue needs attention */ 521 #define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */ 522 #define MI_RESERVED3 (1 << 22) 523 #define MI_RESERVED2 (1 << 23) 524 #define MI_RESERVED1 (1 << 25) 525 /* MAC detected change on RF Disable input*/ 526 #define MI_RFDISABLE (1 << 28) 527 #define MI_TFS (1 << 29) /* MAC has completed a TX */ 528 #define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */ 529 #define MI_TO (1U << 31) /* general purpose timeout */ 530 531 /* Mac capabilities registers */ 532 /* machwcap */ 533 #define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */ 534 535 /* pmqhost data */ 536 #define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */ 537 #define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */ 538 #define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */ 539 #define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */ 540 #define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */ 541 #define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */ 542 #define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */ 543 #define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */ 544 #define PMQH_OFLO 0x00000004 /* pmq overflow indication */ 545 #define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */ 546 547 /* phydebug */ 548 #define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */ 549 #define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */ 550 #define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */ 551 #define PDBG_TXE (1 << 3) /* phy is signalling a transmit Error to the mac */ 552 #define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */ 553 #define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */ 554 #define PDBG_RXFRG (1 << 6) /* rx start not asserted */ 555 #define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */ 556 #define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */ 557 558 /* objaddr register */ 559 #define OBJADDR_SEL_MASK 0x000F0000 560 #define OBJADDR_UCM_SEL 0x00000000 561 #define OBJADDR_SHM_SEL 0x00010000 562 #define OBJADDR_SCR_SEL 0x00020000 563 #define OBJADDR_IHR_SEL 0x00030000 564 #define OBJADDR_RCMTA_SEL 0x00040000 565 #define OBJADDR_SRCHM_SEL 0x00060000 566 #define OBJADDR_WINC 0x01000000 567 #define OBJADDR_RINC 0x02000000 568 #define OBJADDR_AUTO_INC 0x03000000 569 570 #define WEP_PCMADDR 0x07d4 571 #define WEP_PCMDATA 0x07d6 572 573 /* frmtxstatus */ 574 #define TXS_V (1 << 0) /* valid bit */ 575 #define TXS_STATUS_MASK 0xffff 576 #define TXS_FID_MASK 0xffff0000 577 #define TXS_FID_SHIFT 16 578 579 /* frmtxstatus2 */ 580 #define TXS_SEQ_MASK 0xffff 581 #define TXS_PTX_MASK 0xff0000 582 #define TXS_PTX_SHIFT 16 583 #define TXS_MU_MASK 0x01000000 584 #define TXS_MU_SHIFT 24 585 586 /* clk_ctl_st */ 587 #define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */ 588 #define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */ 589 #define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */ 590 #define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */ 591 592 /* HT Cloclk Ctrl and Clock Avail for 4313 */ 593 #define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */ 594 #define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */ 595 596 /* tsf_cfprep register */ 597 #define CFPREP_CBI_MASK 0xffffffc0 598 #define CFPREP_CBI_SHIFT 6 599 #define CFPREP_CFPP 0x00000001 600 601 /* tx fifo sizes values are in terms of 256 byte blocks */ 602 #define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */ 603 #define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */ 604 #define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */ 605 606 #define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */ 607 #define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */ 608 #define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */ 609 #define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */ 610 611 /* phy versions, PhyVersion:Revision field */ 612 #define PV_AV_MASK 0xf000 /* analog block version */ 613 #define PV_AV_SHIFT 12 /* analog block version bitfield offset */ 614 #define PV_PT_MASK 0x0f00 /* phy type */ 615 #define PV_PT_SHIFT 8 /* phy type bitfield offset */ 616 #define PV_PV_MASK 0x000f /* phy version */ 617 #define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT) 618 619 /* phy types, PhyVersion:PhyType field */ 620 #define PHY_TYPE_N 4 /* N-Phy value */ 621 #define PHY_TYPE_SSN 6 /* SSLPN-Phy value */ 622 #define PHY_TYPE_LCN 8 /* LCN-Phy value */ 623 #define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */ 624 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */ 625 626 /* analog types, PhyVersion:AnalogType field */ 627 #define ANA_11N_013 5 628 629 /* 802.11a PLCP header def */ 630 typedef struct ofdm_phy_hdr ofdm_phy_hdr_t; 631 struct ofdm_phy_hdr { 632 u8 rlpt[3]; /* rate, length, parity, tail */ 633 u16 service; 634 u8 pad; 635 } __attribute__((packed)); 636 637 #define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f) 638 #define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01) 639 #define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff) 640 #define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01) 641 #define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f) 642 643 /* rate encoded per 802.11a-1999 sec 17.3.4.1 */ 644 #define D11A_PHY_HDR_SRATE(phdr, rate) \ 645 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf)) 646 /* set reserved field to zero */ 647 #define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef) 648 /* length is number of octets in PSDU */ 649 #define D11A_PHY_HDR_SLENGTH(phdr, length) \ 650 (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \ 651 (((length) & 0x0fff) << 5)) 652 /* set the tail to all zeros */ 653 #define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03) 654 655 #define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */ 656 #define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */ 657 658 #define D11A_PHY_TX_DELAY (2) /* 2.1 usec */ 659 660 #define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */ 661 #define D11A_PHY_PRE_TIME (16) 662 #define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME) 663 664 /* 802.11b PLCP header def */ 665 typedef struct cck_phy_hdr cck_phy_hdr_t; 666 struct cck_phy_hdr { 667 u8 signal; 668 u8 service; 669 u16 length; 670 u16 crc; 671 } __attribute__((packed)); 672 673 #define D11B_PHY_HDR_LEN 6 674 675 #define D11B_PHY_TX_DELAY (3) /* 3.4 usec */ 676 677 #define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3) 678 #define D11B_PHY_LPRE_TIME (144) 679 #define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME) 680 681 #define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1) 682 #define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1) 683 #define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME) 684 685 #define D11B_PLCP_SIGNAL_LOCKED (1 << 2) 686 #define D11B_PLCP_SIGNAL_LE (1 << 7) 687 688 #define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */ 689 #define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */ 690 #define MIMO_PLCP_AMPDU 0x08 /* ampdu */ 691 692 #define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8)) 693 #define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8)) 694 #define WLC_SET_MIMO_PLCP_LEN(plcp, len) \ 695 do { \ 696 plcp[1] = len & 0xff; \ 697 plcp[2] = ((len >> 8) & 0xff); \ 698 } while (0); 699 700 #define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU) 701 #define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU) 702 #define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU) 703 704 /* The dot11a PLCP header is 5 bytes. To simplify the software (so that we 705 * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has 706 * padding added in the ucode. 707 */ 708 #define D11_PHY_HDR_LEN 6 709 710 /* TX DMA buffer header */ 711 typedef struct d11txh d11txh_t; 712 struct d11txh { 713 u16 MacTxControlLow; /* 0x0 */ 714 u16 MacTxControlHigh; /* 0x1 */ 715 u16 MacFrameControl; /* 0x2 */ 716 u16 TxFesTimeNormal; /* 0x3 */ 717 u16 PhyTxControlWord; /* 0x4 */ 718 u16 PhyTxControlWord_1; /* 0x5 */ 719 u16 PhyTxControlWord_1_Fbr; /* 0x6 */ 720 u16 PhyTxControlWord_1_Rts; /* 0x7 */ 721 u16 PhyTxControlWord_1_FbrRts; /* 0x8 */ 722 u16 MainRates; /* 0x9 */ 723 u16 XtraFrameTypes; /* 0xa */ 724 u8 IV[16]; /* 0x0b - 0x12 */ 725 u8 TxFrameRA[6]; /* 0x13 - 0x15 */ 726 u16 TxFesTimeFallback; /* 0x16 */ 727 u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */ 728 u16 RTSDurFallback; /* 0x1a */ 729 u8 FragPLCPFallback[6]; /* 0x1b - 1d */ 730 u16 FragDurFallback; /* 0x1e */ 731 u16 MModeLen; /* 0x1f */ 732 u16 MModeFbrLen; /* 0x20 */ 733 u16 TstampLow; /* 0x21 */ 734 u16 TstampHigh; /* 0x22 */ 735 u16 ABI_MimoAntSel; /* 0x23 */ 736 u16 PreloadSize; /* 0x24 */ 737 u16 AmpduSeqCtl; /* 0x25 */ 738 u16 TxFrameID; /* 0x26 */ 739 u16 TxStatus; /* 0x27 */ 740 u16 MaxNMpdus; /* 0x28 */ 741 u16 MaxABytes_MRT; /* 0x29 */ 742 u16 MaxABytes_FBR; /* 0x2a */ 743 u16 MinMBytes; /* 0x2b */ 744 u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */ 745 struct ieee80211_rts rts_frame; /* 0x2f - 0x36 */ 746 u16 PAD; /* 0x37 */ 747 } __attribute__((packed)); 748 749 #define D11_TXH_LEN 112 /* bytes */ 750 751 /* Frame Types */ 752 #define FT_CCK 0 753 #define FT_OFDM 1 754 #define FT_HT 2 755 #define FT_N 3 756 757 /* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */ 758 #define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */ 759 #define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */ 760 #define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */ 761 #define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */ 762 #define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */ 763 764 /* MacTxControlLow */ 765 #define TXC_AMIC 0x8000 766 #define TXC_SENDCTS 0x0800 767 #define TXC_AMPDU_MASK 0x0600 768 #define TXC_BW_40 0x0100 769 #define TXC_FREQBAND_5G 0x0080 770 #define TXC_DFCS 0x0040 771 #define TXC_IGNOREPMQ 0x0020 772 #define TXC_HWSEQ 0x0010 773 #define TXC_STARTMSDU 0x0008 774 #define TXC_SENDRTS 0x0004 775 #define TXC_LONGFRAME 0x0002 776 #define TXC_IMMEDACK 0x0001 777 778 /* MacTxControlHigh */ 779 #define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */ 780 #define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */ 781 #define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type 782 * 1 = SHORT for OFDM/GF for MIMO 783 * 0 = LONG for CCK/MM for MIMO 784 */ 785 /* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */ 786 #define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */ 787 #define TXC_SECKEY_MASK 0x0FF0 788 #define TXC_SECKEY_SHIFT 4 789 #define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */ 790 #define TXC_SECTYPE_MASK 0x0007 791 #define TXC_SECTYPE_SHIFT 0 792 793 /* Null delimiter for Fallback rate */ 794 #define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */ 795 796 /* PhyTxControl for Mimophy */ 797 #define PHY_TXC_PWR_MASK 0xFC00 798 #define PHY_TXC_PWR_SHIFT 10 799 #define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */ 800 #define PHY_TXC_ANT_SHIFT 6 801 #define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */ 802 #define PHY_TXC_LCNPHY_ANT_LAST 0x0000 803 #define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */ 804 #define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */ 805 #define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */ 806 #define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */ 807 #define PHY_TXC_SHORT_HDR 0x0010 808 809 #define PHY_TXC_OLD_ANT_0 0x0000 810 #define PHY_TXC_OLD_ANT_1 0x0100 811 #define PHY_TXC_OLD_ANT_LAST 0x0300 812 813 /* PhyTxControl_1 for Mimophy */ 814 #define PHY_TXC1_BW_MASK 0x0007 815 #define PHY_TXC1_BW_10MHZ 0 816 #define PHY_TXC1_BW_10MHZ_UP 1 817 #define PHY_TXC1_BW_20MHZ 2 818 #define PHY_TXC1_BW_20MHZ_UP 3 819 #define PHY_TXC1_BW_40MHZ 4 820 #define PHY_TXC1_BW_40MHZ_DUP 5 821 #define PHY_TXC1_MODE_SHIFT 3 822 #define PHY_TXC1_MODE_MASK 0x0038 823 #define PHY_TXC1_MODE_SISO 0 824 #define PHY_TXC1_MODE_CDD 1 825 #define PHY_TXC1_MODE_STBC 2 826 #define PHY_TXC1_MODE_SDM 3 827 828 /* PhyTxControl for HTphy that are different from Mimophy */ 829 #define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */ 830 831 /* XtraFrameTypes */ 832 #define XFTS_RTS_FT_SHIFT 2 833 #define XFTS_FBRRTS_FT_SHIFT 4 834 #define XFTS_CHANNEL_SHIFT 8 835 836 /* Antenna diversity bit in ant_wr_settle */ 837 #define PHY_AWS_ANTDIV 0x2000 838 839 /* IFS ctl */ 840 #define IFS_USEEDCF (1 << 2) 841 842 /* IFS ctl1 */ 843 #define IFS_CTL1_EDCRS (1 << 3) 844 #define IFS_CTL1_EDCRS_20L (1 << 4) 845 #define IFS_CTL1_EDCRS_40 (1 << 5) 846 847 /* ABI_MimoAntSel */ 848 #define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00 849 #define ABI_MAS_ADDR_BMP_IDX_SHIFT 8 850 #define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0 851 #define ABI_MAS_FBR_ANT_PTN_SHIFT 4 852 #define ABI_MAS_MRT_ANT_PTN_MASK 0x000f 853 854 /* tx status packet */ 855 typedef struct tx_status tx_status_t; 856 struct tx_status { 857 u16 framelen; 858 u16 PAD; 859 u16 frameid; 860 u16 status; 861 u16 lasttxtime; 862 u16 sequence; 863 u16 phyerr; 864 u16 ackphyrxsh; 865 } __attribute__((packed)); 866 867 #define TXSTATUS_LEN 16 868 869 /* status field bit definitions */ 870 #define TX_STATUS_FRM_RTX_MASK 0xF000 871 #define TX_STATUS_FRM_RTX_SHIFT 12 872 #define TX_STATUS_RTS_RTX_MASK 0x0F00 873 #define TX_STATUS_RTS_RTX_SHIFT 8 874 #define TX_STATUS_MASK 0x00FE 875 #define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */ 876 #define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */ 877 #define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */ 878 #define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */ 879 #define TX_STATUS_SUPR_SHIFT 2 880 #define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */ 881 #define TX_STATUS_VALID (1 << 0) /* Tx status valid */ 882 #define TX_STATUS_NO_ACK 0 883 884 /* suppress status reason codes */ 885 #define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */ 886 #define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */ 887 #define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */ 888 #define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe response supr for TBTT */ 889 #define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */ 890 #define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */ 891 #define TX_STATUS_SUPR_UF (6 << 2) /* underflow */ 892 893 /* Unexpected tx status for rate update */ 894 #define TX_STATUS_UNEXP(status) \ 895 ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \ 896 TX_STATUS_UNEXP_AMPDU(status)) 897 898 /* Unexpected tx status for A-MPDU rate update */ 899 #define TX_STATUS_UNEXP_AMPDU(status) \ 900 ((((status) & TX_STATUS_SUPR_MASK) != 0) && \ 901 (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME)) 902 903 #define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */ 904 #define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */ 905 #define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */ 906 #define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */ 907 908 /* RXE (Receive Engine) */ 909 910 /* RCM_CTL */ 911 #define RCM_INC_MASK_H 0x0080 912 #define RCM_INC_MASK_L 0x0040 913 #define RCM_INC_DATA 0x0020 914 #define RCM_INDEX_MASK 0x001F 915 #define RCM_SIZE 15 916 917 #define RCM_MAC_OFFSET 0 /* current MAC address */ 918 #define RCM_BSSID_OFFSET 3 /* current BSSID address */ 919 #define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */ 920 #define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */ 921 #define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */ 922 923 #define RCM_WEP_TA0_OFFSET 16 924 #define RCM_WEP_TA1_OFFSET 19 925 #define RCM_WEP_TA2_OFFSET 22 926 #define RCM_WEP_TA3_OFFSET 25 927 928 /* PSM Block */ 929 930 /* psm_phy_hdr_param bits */ 931 #define MAC_PHY_RESET 1 932 #define MAC_PHY_CLOCK_EN 2 933 #define MAC_PHY_FORCE_CLK 4 934 935 /* WEP Block */ 936 937 /* WEP_WKEY */ 938 #define WKEY_START (1 << 8) 939 #define WKEY_SEL_MASK 0x1F 940 941 /* WEP data formats */ 942 943 /* the number of RCMTA entries */ 944 #define RCMTA_SIZE 50 945 946 #define M_ADDR_BMP_BLK (0x37e * 2) 947 #define M_ADDR_BMP_BLK_SZ 12 948 949 #define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */ 950 #define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */ 951 #define ADDR_BMP_BSSID (1 << 2) /* BSSID */ 952 #define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */ 953 #define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */ 954 #define ADDR_BMP_RESERVED1 (1 << 5) 955 #define ADDR_BMP_RESERVED2 (1 << 6) 956 #define ADDR_BMP_RESERVED3 (1 << 7) 957 #define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */ 958 #define ADDR_BMP_BSS_IDX_SHIFT 8 959 960 #define WSEC_MAX_RCMTA_KEYS 54 961 962 /* max keys in M_TKMICKEYS_BLK */ 963 #define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */ 964 965 /* max RXE match registers */ 966 #define WSEC_MAX_RXE_KEYS 4 967 968 /* SECKINDXALGO (Security Key Index & Algorithm Block) word format */ 969 /* SKL (Security Key Lookup) */ 970 #define SKL_ALGO_MASK 0x0007 971 #define SKL_ALGO_SHIFT 0 972 #define SKL_KEYID_MASK 0x0008 973 #define SKL_KEYID_SHIFT 3 974 #define SKL_INDEX_MASK 0x03F0 975 #define SKL_INDEX_SHIFT 4 976 #define SKL_GRP_ALGO_MASK 0x1c00 977 #define SKL_GRP_ALGO_SHIFT 10 978 979 /* additional bits defined for IBSS group key support */ 980 #define SKL_IBSS_INDEX_MASK 0x01F0 981 #define SKL_IBSS_INDEX_SHIFT 4 982 #define SKL_IBSS_KEYID1_MASK 0x0600 983 #define SKL_IBSS_KEYID1_SHIFT 9 984 #define SKL_IBSS_KEYID2_MASK 0x1800 985 #define SKL_IBSS_KEYID2_SHIFT 11 986 #define SKL_IBSS_KEYALGO_MASK 0xE000 987 #define SKL_IBSS_KEYALGO_SHIFT 13 988 989 #define WSEC_MODE_OFF 0 990 #define WSEC_MODE_HW 1 991 #define WSEC_MODE_SW 2 992 993 #define WSEC_ALGO_OFF 0 994 #define WSEC_ALGO_WEP1 1 995 #define WSEC_ALGO_TKIP 2 996 #define WSEC_ALGO_AES 3 997 #define WSEC_ALGO_WEP128 4 998 #define WSEC_ALGO_AES_LEGACY 5 999 #define WSEC_ALGO_NALG 6 1000 1001 #define AES_MODE_NONE 0 1002 #define AES_MODE_CCM 1 1003 1004 /* WEP_CTL (Rev 0) */ 1005 #define WECR0_KEYREG_SHIFT 0 1006 #define WECR0_KEYREG_MASK 0x7 1007 #define WECR0_DECRYPT (1 << 3) 1008 #define WECR0_IVINLINE (1 << 4) 1009 #define WECR0_WEPALG_SHIFT 5 1010 #define WECR0_WEPALG_MASK (0x7 << 5) 1011 #define WECR0_WKEYSEL_SHIFT 8 1012 #define WECR0_WKEYSEL_MASK (0x7 << 8) 1013 #define WECR0_WKEYSTART (1 << 11) 1014 #define WECR0_WEPINIT (1 << 14) 1015 #define WECR0_ICVERR (1 << 15) 1016 1017 /* Frame template map byte offsets */ 1018 #define T_ACTS_TPL_BASE (0) 1019 #define T_NULL_TPL_BASE (0xc * 2) 1020 #define T_QNULL_TPL_BASE (0x1c * 2) 1021 #define T_RR_TPL_BASE (0x2c * 2) 1022 #define T_BCN0_TPL_BASE (0x34 * 2) 1023 #define T_PRS_TPL_BASE (0x134 * 2) 1024 #define T_BCN1_TPL_BASE (0x234 * 2) 1025 #define T_TX_FIFO_TXRAM_BASE (T_ACTS_TPL_BASE + (TXFIFO_START_BLK * TXFIFO_SIZE_UNIT)) 1026 1027 #define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */ 1028 1029 #define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */ 1030 1031 /* Shared Mem byte offsets */ 1032 1033 /* Location where the ucode expects the corerev */ 1034 #define M_MACHW_VER (0x00b * 2) 1035 1036 /* Location where the ucode expects the MAC capabilities */ 1037 #define M_MACHW_CAP_L (0x060 * 2) 1038 #define M_MACHW_CAP_H (0x061 * 2) 1039 1040 /* WME shared memory */ 1041 #define M_EDCF_STATUS_OFF (0x007 * 2) 1042 #define M_TXF_CUR_INDEX (0x018 * 2) 1043 #define M_EDCF_QINFO (0x120 * 2) 1044 1045 /* PS-mode related parameters */ 1046 #define M_DOT11_SLOT (0x008 * 2) 1047 #define M_DOT11_DTIMPERIOD (0x009 * 2) 1048 #define M_NOSLPZNATDTIM (0x026 * 2) 1049 1050 /* Beacon-related parameters */ 1051 #define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */ 1052 #define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */ 1053 #define M_BCN_TXTSF_OFFSET (0x00e * 2) 1054 #define M_TIMBPOS_INBEACON (0x00f * 2) 1055 #define M_SFRMTXCNTFBRTHSD (0x022 * 2) 1056 #define M_LFRMTXCNTFBRTHSD (0x023 * 2) 1057 #define M_BCN_PCTLWD (0x02a * 2) 1058 #define M_BCN_LI (0x05b * 2) /* beacon listen interval */ 1059 1060 /* MAX Rx Frame len */ 1061 #define M_MAXRXFRM_LEN (0x010 * 2) 1062 1063 /* ACK/CTS related params */ 1064 #define M_RSP_PCTLWD (0x011 * 2) 1065 1066 /* Hardware Power Control */ 1067 #define M_TXPWR_N (0x012 * 2) 1068 #define M_TXPWR_TARGET (0x013 * 2) 1069 #define M_TXPWR_MAX (0x014 * 2) 1070 #define M_TXPWR_CUR (0x019 * 2) 1071 1072 /* Rx-related parameters */ 1073 #define M_RX_PAD_DATA_OFFSET (0x01a * 2) 1074 1075 /* WEP Shared mem data */ 1076 #define M_SEC_DEFIVLOC (0x01e * 2) 1077 #define M_SEC_VALNUMSOFTMCHTA (0x01f * 2) 1078 #define M_PHYVER (0x028 * 2) 1079 #define M_PHYTYPE (0x029 * 2) 1080 #define M_SECRXKEYS_PTR (0x02b * 2) 1081 #define M_TKMICKEYS_PTR (0x059 * 2) 1082 #define M_SECKINDXALGO_BLK (0x2ea * 2) 1083 #define M_SECKINDXALGO_BLK_SZ 54 1084 #define M_SECPSMRXTAMCH_BLK (0x2fa * 2) 1085 #define M_TKIP_TSC_TTAK (0x18c * 2) 1086 #define D11_MAX_KEY_SIZE 16 1087 1088 #define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */ 1089 1090 /* Probe response related parameters */ 1091 #define M_SSIDLEN (0x024 * 2) 1092 #define M_PRB_RESP_FRM_LEN (0x025 * 2) 1093 #define M_PRS_MAXTIME (0x03a * 2) 1094 #define M_SSID (0xb0 * 2) 1095 #define M_CTXPRS_BLK (0xc0 * 2) 1096 #define C_CTX_PCTLWD_POS (0x4 * 2) 1097 1098 /* Delta between OFDM and CCK power in CCK power boost mode */ 1099 #define M_OFDM_OFFSET (0x027 * 2) 1100 1101 /* TSSI for last 4 11b/g CCK packets transmitted */ 1102 #define M_B_TSSI_0 (0x02c * 2) 1103 #define M_B_TSSI_1 (0x02d * 2) 1104 1105 /* Host flags to turn on ucode options */ 1106 #define M_HOST_FLAGS1 (0x02f * 2) 1107 #define M_HOST_FLAGS2 (0x030 * 2) 1108 #define M_HOST_FLAGS3 (0x031 * 2) 1109 #define M_HOST_FLAGS4 (0x03c * 2) 1110 #define M_HOST_FLAGS5 (0x06a * 2) 1111 #define M_HOST_FLAGS_SZ 16 1112 1113 #define M_RADAR_REG (0x033 * 2) 1114 1115 /* TSSI for last 4 11a OFDM packets transmitted */ 1116 #define M_A_TSSI_0 (0x034 * 2) 1117 #define M_A_TSSI_1 (0x035 * 2) 1118 1119 /* noise interference measurement */ 1120 #define M_NOISE_IF_COUNT (0x034 * 2) 1121 #define M_NOISE_IF_TIMEOUT (0x035 * 2) 1122 1123 #define M_RF_RX_SP_REG1 (0x036 * 2) 1124 1125 /* TSSI for last 4 11g OFDM packets transmitted */ 1126 #define M_G_TSSI_0 (0x038 * 2) 1127 #define M_G_TSSI_1 (0x039 * 2) 1128 1129 /* Background noise measure */ 1130 #define M_JSSI_0 (0x44 * 2) 1131 #define M_JSSI_1 (0x45 * 2) 1132 #define M_JSSI_AUX (0x46 * 2) 1133 1134 #define M_CUR_2050_RADIOCODE (0x47 * 2) 1135 1136 /* TX fifo sizes */ 1137 #define M_FIFOSIZE0 (0x4c * 2) 1138 #define M_FIFOSIZE1 (0x4d * 2) 1139 #define M_FIFOSIZE2 (0x4e * 2) 1140 #define M_FIFOSIZE3 (0x4f * 2) 1141 #define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */ 1142 1143 /* Current channel number plus upper bits */ 1144 #define M_CURCHANNEL (0x50 * 2) 1145 #define D11_CURCHANNEL_5G 0x0100; 1146 #define D11_CURCHANNEL_40 0x0200; 1147 #define D11_CURCHANNEL_MAX 0x00FF; 1148 1149 /* last posted frameid on the bcmc fifo */ 1150 #define M_BCMC_FID (0x54 * 2) 1151 #define INVALIDFID 0xffff 1152 1153 /* extended beacon phyctl bytes for 11N */ 1154 #define M_BCN_PCTL1WD (0x058 * 2) 1155 1156 /* idle busy ratio to duty_cycle requirement */ 1157 #define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2) 1158 #define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2) 1159 1160 /* CW RSSI for LCNPHY */ 1161 #define M_LCN_RSSI_0 0x1332 1162 #define M_LCN_RSSI_1 0x1338 1163 #define M_LCN_RSSI_2 0x133e 1164 #define M_LCN_RSSI_3 0x1344 1165 1166 /* SNR for LCNPHY */ 1167 #define M_LCN_SNR_A_0 0x1334 1168 #define M_LCN_SNR_B_0 0x1336 1169 1170 #define M_LCN_SNR_A_1 0x133a 1171 #define M_LCN_SNR_B_1 0x133c 1172 1173 #define M_LCN_SNR_A_2 0x1340 1174 #define M_LCN_SNR_B_2 0x1342 1175 1176 #define M_LCN_SNR_A_3 0x1346 1177 #define M_LCN_SNR_B_3 0x1348 1178 1179 #define M_LCN_LAST_RESET (81*2) 1180 #define M_LCN_LAST_LOC (63*2) 1181 #define M_LCNPHY_RESET_STATUS (4902) 1182 #define M_LCNPHY_DSC_TIME (0x98d*2) 1183 #define M_LCNPHY_RESET_CNT_DSC (0x98b*2) 1184 #define M_LCNPHY_RESET_CNT (0x98c*2) 1185 1186 /* Rate table offsets */ 1187 #define M_RT_DIRMAP_A (0xe0 * 2) 1188 #define M_RT_BBRSMAP_A (0xf0 * 2) 1189 #define M_RT_DIRMAP_B (0x100 * 2) 1190 #define M_RT_BBRSMAP_B (0x110 * 2) 1191 1192 /* Rate table entry offsets */ 1193 #define M_RT_PRS_PLCP_POS 10 1194 #define M_RT_PRS_DUR_POS 16 1195 #define M_RT_OFDM_PCTL1_POS 18 1196 1197 #define M_20IN40_IQ (0x380 * 2) 1198 1199 /* SHM locations where ucode stores the current power index */ 1200 #define M_CURR_IDX1 (0x384 * 2) 1201 #define M_CURR_IDX2 (0x387 * 2) 1202 1203 #define M_BSCALE_ANT0 (0x5e * 2) 1204 #define M_BSCALE_ANT1 (0x5f * 2) 1205 1206 /* Antenna Diversity Testing */ 1207 #define M_MIMO_ANTSEL_RXDFLT (0x63 * 2) 1208 #define M_ANTSEL_CLKDIV (0x61 * 2) 1209 #define M_MIMO_ANTSEL_TXDFLT (0x64 * 2) 1210 1211 #define M_MIMO_MAXSYM (0x5d * 2) 1212 #define MIMO_MAXSYM_DEF 0x8000 /* 32k */ 1213 #define MIMO_MAXSYM_MAX 0xffff /* 64k */ 1214 1215 #define M_WATCHDOG_8TU (0x1e * 2) 1216 #define WATCHDOG_8TU_DEF 5 1217 #define WATCHDOG_8TU_MAX 10 1218 1219 /* Manufacturing Test Variables */ 1220 #define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */ 1221 #define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */ 1222 #define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */ 1223 #define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */ 1224 1225 /* Index variation in vbat ripple */ 1226 #define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */ 1227 #define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */ 1228 1229 /* M_PKTENG_CTRL bit definitions */ 1230 #define M_PKTENG_MODE_TX 0x0001 1231 #define M_PKTENG_MODE_TX_RIFS 0x0004 1232 #define M_PKTENG_MODE_TX_CTS 0x0008 1233 #define M_PKTENG_MODE_RX 0x0002 1234 #define M_PKTENG_MODE_RX_WITH_ACK 0x0402 1235 #define M_PKTENG_MODE_MASK 0x0003 1236 #define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */ 1237 1238 /* Sample Collect parameters (bitmap and type) */ 1239 #define M_SMPL_COL_BMP (0x37d * 2) /* Trigger bitmap for sample collect */ 1240 #define M_SMPL_COL_CTL (0x3b2 * 2) /* Sample collect type */ 1241 1242 #define ANTSEL_CLKDIV_4MHZ 6 1243 #define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */ 1244 #define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */ 1245 #define MIMO_ANTSEL_WAIT 50 /* 50us wait */ 1246 #define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */ 1247 1248 typedef struct shm_acparams shm_acparams_t; 1249 struct shm_acparams { 1250 u16 txop; 1251 u16 cwmin; 1252 u16 cwmax; 1253 u16 cwcur; 1254 u16 aifs; 1255 u16 bslots; 1256 u16 reggap; 1257 u16 status; 1258 u16 rsvd[8]; 1259 } __attribute__((packed)); 1260 #define M_EDCF_QLEN (16 * 2) 1261 1262 #define WME_STATUS_NEWAC (1 << 8) 1263 1264 /* M_HOST_FLAGS */ 1265 #define MHFMAX 5 /* Number of valid hostflag half-word (u16) */ 1266 #define MHF1 0 /* Hostflag 1 index */ 1267 #define MHF2 1 /* Hostflag 2 index */ 1268 #define MHF3 2 /* Hostflag 3 index */ 1269 #define MHF4 3 /* Hostflag 4 index */ 1270 #define MHF5 4 /* Hostflag 5 index */ 1271 1272 /* Flags in M_HOST_FLAGS */ 1273 #define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */ 1274 #define MHF1_EDCF 0x0100 /* Enable EDCF access control */ 1275 #define MHF1_IQSWAP_WAR 0x0200 1276 #define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */ 1277 1278 /* Flags in M_HOST_FLAGS2 */ 1279 #define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */ 1280 #define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */ 1281 #define MHF2_HWPWRCTL 0x0080 /* Enable ucode/hw power control */ 1282 #define MHF2_NPHY40MHZ_WAR 0x0800 1283 1284 /* Flags in M_HOST_FLAGS3 */ 1285 #define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */ 1286 #define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */ 1287 #define MHF3_RESERVED1 0x0004 1288 #define MHF3_RESERVED2 0x0008 1289 #define MHF3_NPHY_MLADV_WAR 0x0010 1290 1291 /* Flags in M_HOST_FLAGS4 */ 1292 #define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */ 1293 #define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */ 1294 1295 /* Flags in M_HOST_FLAGS5 */ 1296 #define MHF5_4313_GPIOCTRL 0x0001 1297 #define MHF5_RESERVED1 0x0002 1298 #define MHF5_RESERVED2 0x0004 1299 /* Radio power setting for ucode */ 1300 #define M_RADIO_PWR (0x32 * 2) 1301 1302 /* phy noise recorded by ucode right after tx */ 1303 #define M_PHY_NOISE (0x037 * 2) 1304 #define PHY_NOISE_MASK 0x00ff 1305 1306 /* Receive Frame Data Header for 802.11b DCF-only frames */ 1307 typedef struct d11rxhdr d11rxhdr_t; 1308 struct d11rxhdr { 1309 u16 RxFrameSize; /* Actual byte length of the frame data received */ 1310 u16 PAD; 1311 u16 PhyRxStatus_0; /* PhyRxStatus 15:0 */ 1312 u16 PhyRxStatus_1; /* PhyRxStatus 31:16 */ 1313 u16 PhyRxStatus_2; /* PhyRxStatus 47:32 */ 1314 u16 PhyRxStatus_3; /* PhyRxStatus 63:48 */ 1315 u16 PhyRxStatus_4; /* PhyRxStatus 79:64 */ 1316 u16 PhyRxStatus_5; /* PhyRxStatus 95:80 */ 1317 u16 RxStatus1; /* MAC Rx Status */ 1318 u16 RxStatus2; /* extended MAC Rx status */ 1319 u16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */ 1320 u16 RxChan; /* gain code, channel radio code, and phy type */ 1321 } __attribute__((packed)); 1322 1323 #define RXHDR_LEN 24 /* sizeof d11rxhdr_t */ 1324 #define FRAMELEN(h) ((h)->RxFrameSize) 1325 1326 typedef struct wlc_d11rxhdr wlc_d11rxhdr_t; 1327 struct wlc_d11rxhdr { 1328 d11rxhdr_t rxhdr; 1329 u32 tsf_l; /* TSF_L reading */ 1330 s8 rssi; /* computed instanteneous rssi in BMAC */ 1331 s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ 1332 s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ 1333 s8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */ 1334 s8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */ 1335 } __attribute__((packed)); 1336 1337 /* PhyRxStatus_0: */ 1338 #define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, preN, N */ 1339 #define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */ 1340 #define PRXS0_CLIP_SHIFT 2 1341 #define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */ 1342 #define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */ 1343 #define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */ 1344 #define PRXS0_SHORTH 0x0080 /* Short Preamble */ 1345 #define PRXS0_PLCPFV 0x0100 /* PLCP violation */ 1346 #define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */ 1347 #define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */ 1348 #define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */ 1349 #define PRXS0_ANTSEL_SHIFT 0x12 1350 1351 /* subfield PRXS0_FT_MASK */ 1352 #define PRXS0_CCK 0x0000 1353 #define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */ 1354 #define PRXS0_PREN 0x0002 1355 #define PRXS0_STDN 0x0003 1356 1357 /* subfield PRXS0_ANTSEL_MASK */ 1358 #define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */ 1359 #define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */ 1360 #define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */ 1361 #define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */ 1362 1363 /* PhyRxStatus_1: */ 1364 #define PRXS1_JSSI_MASK 0x00FF 1365 #define PRXS1_JSSI_SHIFT 0 1366 #define PRXS1_SQ_MASK 0xFF00 1367 #define PRXS1_SQ_SHIFT 8 1368 1369 /* nphy PhyRxStatus_1: */ 1370 #define PRXS1_nphy_PWR0_MASK 0x00FF 1371 #define PRXS1_nphy_PWR1_MASK 0xFF00 1372 1373 /* HTPHY Rx Status defines */ 1374 /* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */ 1375 #define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */ 1376 #define PRXS0_RSVD 0x0800 /* reserved; set to 0 */ 1377 #define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */ 1378 1379 /* htphy PhyRxStatus_1: */ 1380 #define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */ 1381 #define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configation */ 1382 #define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */ 1383 1384 /* htphy PhyRxStatus_2: */ 1385 #define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */ 1386 #define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */ 1387 #define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */ 1388 1389 /* htphy PhyRxStatus_3: */ 1390 #define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */ 1391 #define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */ 1392 1393 /* htphy PhyRxStatus_4: */ 1394 #define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */ 1395 #define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */ 1396 1397 /* htphy PhyRxStatus_5: */ 1398 #define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */ 1399 #define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */ 1400 1401 #define HTPHY_MMPLCPLen(rxs) ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \ 1402 (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8)) 1403 /* Get Rx power on core 0 */ 1404 #define HTPHY_RXPWR_ANT0(rxs) ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8) 1405 /* Get Rx power on core 1 */ 1406 #define HTPHY_RXPWR_ANT1(rxs) (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1) 1407 /* Get Rx power on core 2 */ 1408 #define HTPHY_RXPWR_ANT2(rxs) ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8) 1409 1410 /* ucode RxStatus1: */ 1411 #define RXS_BCNSENT 0x8000 1412 #define RXS_SECKINDX_MASK 0x07e0 1413 #define RXS_SECKINDX_SHIFT 5 1414 #define RXS_DECERR (1 << 4) 1415 #define RXS_DECATMPT (1 << 3) 1416 #define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */ 1417 #define RXS_RESPFRAMETX (1 << 1) 1418 #define RXS_FCSERR (1 << 0) 1419 1420 /* ucode RxStatus2: */ 1421 #define RXS_AMSDU_MASK 1 1422 #define RXS_AGGTYPE_MASK 0x6 1423 #define RXS_AGGTYPE_SHIFT 1 1424 #define RXS_PHYRXST_VALID (1 << 8) 1425 #define RXS_RXANT_MASK 0x3 1426 #define RXS_RXANT_SHIFT 12 1427 1428 /* RxChan */ 1429 #define RXS_CHAN_40 0x1000 1430 #define RXS_CHAN_5G 0x0800 1431 #define RXS_CHAN_ID_MASK 0x07f8 1432 #define RXS_CHAN_ID_SHIFT 3 1433 #define RXS_CHAN_PHYTYPE_MASK 0x0007 1434 #define RXS_CHAN_PHYTYPE_SHIFT 0 1435 1436 /* Index of attenuations used during ucode power control. */ 1437 #define M_PWRIND_BLKS (0x184 * 2) 1438 #define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0) 1439 #define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2) 1440 #define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4) 1441 #define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6) 1442 /* M_PWRIND_MAP(core) macro */ 1443 #define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1)) 1444 1445 /* PSM SHM variable offsets */ 1446 #define M_PSM_SOFT_REGS 0x0 1447 #define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0) 1448 #define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2) 1449 #define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */ 1450 #define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */ 1451 1452 #define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */ 1453 #define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */ 1454 #define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */ 1455 #define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */ 1456 #define M_PRETBTT (0x4b * 2) 1457 1458 #define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */ 1459 #define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2)) 1460 #define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2)) 1461 #define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2)) 1462 1463 /* PKTENG Rx Stats Block */ 1464 #define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2)) 1465 1466 /* ucode debug status codes */ 1467 #define DBGST_INACTIVE 0 /* not valid really */ 1468 #define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */ 1469 #define DBGST_ACTIVE 2 /* "normal" state */ 1470 #define DBGST_SUSPENDED 3 /* suspended */ 1471 #define DBGST_ASLEEP 4 /* asleep (PS mode) */ 1472 1473 /* Scratch Reg defs */ 1474 typedef enum { 1475 S_RSV0 = 0, 1476 S_RSV1, 1477 S_RSV2, 1478 1479 /* scratch registers for Dot11-contants */ 1480 S_DOT11_CWMIN, /* CW-minimum 0x03 */ 1481 S_DOT11_CWMAX, /* CW-maximum 0x04 */ 1482 S_DOT11_CWCUR, /* CW-current 0x05 */ 1483 S_DOT11_SRC_LMT, /* short retry count limit 0x06 */ 1484 S_DOT11_LRC_LMT, /* long retry count limit 0x07 */ 1485 S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */ 1486 1487 /* Tx-side scratch registers */ 1488 S_SEQ_NUM, /* hardware sequence number reg 0x09 */ 1489 S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */ 1490 S_FRMRETX_CNT, /* frame retx count 0x0B */ 1491 S_SSRC, /* Station short retry count 0x0C */ 1492 S_SLRC, /* Station long retry count 0x0D */ 1493 S_EXP_RSP, /* Expected response frame 0x0E */ 1494 S_OLD_BREM, /* Remaining backoff ctr 0x0F */ 1495 S_OLD_CWWIN, /* saved-off CW-cur 0x10 */ 1496 S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */ 1497 S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */ 1498 1499 /* Rx-side scratch registers */ 1500 S_RXTST, /* Type and subtype in Rxframe 0x13 */ 1501 1502 /* Global state register */ 1503 S_STREG, /* state storage actual bit maps below 0x14 */ 1504 1505 S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */ 1506 S_TXPWR_ITER, /* Tx power control: iteration 0x16 */ 1507 S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */ 1508 S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */ 1509 1510 S_KEYINDX, /* 0x19 */ 1511 S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */ 1512 1513 /* Receive TSF time stored in SCR */ 1514 S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */ 1515 S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */ 1516 S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */ 1517 S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */ 1518 S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */ 1519 S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */ 1520 1521 /* Scratch pad regs used in microcode as temp storage */ 1522 S_TMP0, /* stmp0 0x21 */ 1523 S_TMP1, /* stmp1 0x22 */ 1524 S_TMP2, /* stmp2 0x23 */ 1525 S_TMP3, /* stmp3 0x24 */ 1526 S_TMP4, /* stmp4 0x25 */ 1527 S_TMP5, /* stmp5 0x26 */ 1528 S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */ 1529 S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */ 1530 S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */ 1531 S_RXTP, /* rx frame type 0x2A */ 1532 S_STREG2, /* extra state storage 0x2B */ 1533 S_STREG3, /* even more extra state storage 0x2C */ 1534 S_STREG4, /* ... 0x2D */ 1535 S_STREG5, /* remember to initialize it to zero 0x2E */ 1536 1537 S_ADJPWR_IDX, 1538 S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */ 1539 S_REVID4, /* 0x33 */ 1540 S_INDX, /* 0x34 */ 1541 S_ADDR0, /* 0x35 */ 1542 S_ADDR1, /* 0x36 */ 1543 S_ADDR2, /* 0x37 */ 1544 S_ADDR3, /* 0x38 */ 1545 S_ADDR4, /* 0x39 */ 1546 S_ADDR5, /* 0x3A */ 1547 S_TMP6, /* 0x3B */ 1548 S_KEYINDX_BU, /* Backup for Key index 0x3C */ 1549 S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */ 1550 S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */ 1551 S_STREG6, /* 0x3F */ 1552 } ePsmScratchPadRegDefinitions; 1553 1554 #define S_BEACON_INDX S_OLD_BREM 1555 #define S_PRS_INDX S_OLD_CWWIN 1556 #define S_PHYTYPE S_SSRC 1557 #define S_PHYVER S_SLRC 1558 1559 /* IHR SLOW_CTRL values */ 1560 #define SLOW_CTRL_PDE (1 << 0) 1561 #define SLOW_CTRL_FD (1 << 8) 1562 1563 /* ucode mac statistic counters in shared memory */ 1564 typedef struct macstat { 1565 u16 txallfrm; /* 0x80 */ 1566 u16 txrtsfrm; /* 0x82 */ 1567 u16 txctsfrm; /* 0x84 */ 1568 u16 txackfrm; /* 0x86 */ 1569 u16 txdnlfrm; /* 0x88 */ 1570 u16 txbcnfrm; /* 0x8a */ 1571 u16 txfunfl[8]; /* 0x8c - 0x9b */ 1572 u16 txtplunfl; /* 0x9c */ 1573 u16 txphyerr; /* 0x9e */ 1574 u16 pktengrxducast; /* 0xa0 */ 1575 u16 pktengrxdmcast; /* 0xa2 */ 1576 u16 rxfrmtoolong; /* 0xa4 */ 1577 u16 rxfrmtooshrt; /* 0xa6 */ 1578 u16 rxinvmachdr; /* 0xa8 */ 1579 u16 rxbadfcs; /* 0xaa */ 1580 u16 rxbadplcp; /* 0xac */ 1581 u16 rxcrsglitch; /* 0xae */ 1582 u16 rxstrt; /* 0xb0 */ 1583 u16 rxdfrmucastmbss; /* 0xb2 */ 1584 u16 rxmfrmucastmbss; /* 0xb4 */ 1585 u16 rxcfrmucast; /* 0xb6 */ 1586 u16 rxrtsucast; /* 0xb8 */ 1587 u16 rxctsucast; /* 0xba */ 1588 u16 rxackucast; /* 0xbc */ 1589 u16 rxdfrmocast; /* 0xbe */ 1590 u16 rxmfrmocast; /* 0xc0 */ 1591 u16 rxcfrmocast; /* 0xc2 */ 1592 u16 rxrtsocast; /* 0xc4 */ 1593 u16 rxctsocast; /* 0xc6 */ 1594 u16 rxdfrmmcast; /* 0xc8 */ 1595 u16 rxmfrmmcast; /* 0xca */ 1596 u16 rxcfrmmcast; /* 0xcc */ 1597 u16 rxbeaconmbss; /* 0xce */ 1598 u16 rxdfrmucastobss; /* 0xd0 */ 1599 u16 rxbeaconobss; /* 0xd2 */ 1600 u16 rxrsptmout; /* 0xd4 */ 1601 u16 bcntxcancl; /* 0xd6 */ 1602 u16 PAD; 1603 u16 rxf0ovfl; /* 0xda */ 1604 u16 rxf1ovfl; /* 0xdc */ 1605 u16 rxf2ovfl; /* 0xde */ 1606 u16 txsfovfl; /* 0xe0 */ 1607 u16 pmqovfl; /* 0xe2 */ 1608 u16 rxcgprqfrm; /* 0xe4 */ 1609 u16 rxcgprsqovfl; /* 0xe6 */ 1610 u16 txcgprsfail; /* 0xe8 */ 1611 u16 txcgprssuc; /* 0xea */ 1612 u16 prs_timeout; /* 0xec */ 1613 u16 rxnack; 1614 u16 frmscons; 1615 u16 txnack; 1616 u16 txglitch_nack; 1617 u16 txburst; /* 0xf6 # tx bursts */ 1618 u16 bphy_rxcrsglitch; /* bphy rx crs glitch */ 1619 u16 phywatchdog; /* 0xfa # of phy watchdog events */ 1620 u16 PAD; 1621 u16 bphy_badplcp; /* bphy bad plcp */ 1622 } macstat_t; 1623 1624 /* dot11 core-specific control flags */ 1625 #define SICF_PCLKE 0x0004 /* PHY clock enable */ 1626 #define SICF_PRST 0x0008 /* PHY reset */ 1627 #define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */ 1628 #define SICF_FREF 0x0020 /* PLL FreqRefSelect */ 1629 /* NOTE: the following bw bits only apply when the core is attached 1630 * to a NPHY 1631 */ 1632 #define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */ 1633 #define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */ 1634 #define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */ 1635 #define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */ 1636 #define SICF_GMODE 0x2000 /* gmode enable */ 1637 1638 /* dot11 core-specific status flags */ 1639 #define SISF_2G_PHY 0x0001 /* 2.4G capable phy */ 1640 #define SISF_5G_PHY 0x0002 /* 5G capable phy */ 1641 #define SISF_FCLKA 0x0004 /* FastClkAvailable */ 1642 #define SISF_DB_PHY 0x0008 /* Dualband phy */ 1643 1644 /* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */ 1645 1646 #define BPHY_REG_OFT_BASE 0x0 1647 /* offsets for indirect access to bphy registers */ 1648 #define BPHY_BB_CONFIG 0x01 1649 #define BPHY_ADCBIAS 0x02 1650 #define BPHY_ANACORE 0x03 1651 #define BPHY_PHYCRSTH 0x06 1652 #define BPHY_TEST 0x0a 1653 #define BPHY_PA_TX_TO 0x10 1654 #define BPHY_SYNTH_DC_TO 0x11 1655 #define BPHY_PA_TX_TIME_UP 0x12 1656 #define BPHY_RX_FLTR_TIME_UP 0x13 1657 #define BPHY_TX_POWER_OVERRIDE 0x14 1658 #define BPHY_RF_OVERRIDE 0x15 1659 #define BPHY_RF_TR_LOOKUP1 0x16 1660 #define BPHY_RF_TR_LOOKUP2 0x17 1661 #define BPHY_COEFFS 0x18 1662 #define BPHY_PLL_OUT 0x19 1663 #define BPHY_REFRESH_MAIN 0x1a 1664 #define BPHY_REFRESH_TO0 0x1b 1665 #define BPHY_REFRESH_TO1 0x1c 1666 #define BPHY_RSSI_TRESH 0x20 1667 #define BPHY_IQ_TRESH_HH 0x21 1668 #define BPHY_IQ_TRESH_H 0x22 1669 #define BPHY_IQ_TRESH_L 0x23 1670 #define BPHY_IQ_TRESH_LL 0x24 1671 #define BPHY_GAIN 0x25 1672 #define BPHY_LNA_GAIN_RANGE 0x26 1673 #define BPHY_JSSI 0x27 1674 #define BPHY_TSSI_CTL 0x28 1675 #define BPHY_TSSI 0x29 1676 #define BPHY_TR_LOSS_CTL 0x2a 1677 #define BPHY_LO_LEAKAGE 0x2b 1678 #define BPHY_LO_RSSI_ACC 0x2c 1679 #define BPHY_LO_IQMAG_ACC 0x2d 1680 #define BPHY_TX_DC_OFF1 0x2e 1681 #define BPHY_TX_DC_OFF2 0x2f 1682 #define BPHY_PEAK_CNT_THRESH 0x30 1683 #define BPHY_FREQ_OFFSET 0x31 1684 #define BPHY_DIVERSITY_CTL 0x32 1685 #define BPHY_PEAK_ENERGY_LO 0x33 1686 #define BPHY_PEAK_ENERGY_HI 0x34 1687 #define BPHY_SYNC_CTL 0x35 1688 #define BPHY_TX_PWR_CTRL 0x36 1689 #define BPHY_TX_EST_PWR 0x37 1690 #define BPHY_STEP 0x38 1691 #define BPHY_WARMUP 0x39 1692 #define BPHY_LMS_CFF_READ 0x3a 1693 #define BPHY_LMS_COEFF_I 0x3b 1694 #define BPHY_LMS_COEFF_Q 0x3c 1695 #define BPHY_SIG_POW 0x3d 1696 #define BPHY_RFDC_CANCEL_CTL 0x3e 1697 #define BPHY_HDR_TYPE 0x40 1698 #define BPHY_SFD_TO 0x41 1699 #define BPHY_SFD_CTL 0x42 1700 #define BPHY_DEBUG 0x43 1701 #define BPHY_RX_DELAY_COMP 0x44 1702 #define BPHY_CRS_DROP_TO 0x45 1703 #define BPHY_SHORT_SFD_NZEROS 0x46 1704 #define BPHY_DSSS_COEFF1 0x48 1705 #define BPHY_DSSS_COEFF2 0x49 1706 #define BPHY_CCK_COEFF1 0x4a 1707 #define BPHY_CCK_COEFF2 0x4b 1708 #define BPHY_TR_CORR 0x4c 1709 #define BPHY_ANGLE_SCALE 0x4d 1710 #define BPHY_TX_PWR_BASE_IDX 0x4e 1711 #define BPHY_OPTIONAL_MODES2 0x4f 1712 #define BPHY_CCK_LMS_STEP 0x50 1713 #define BPHY_BYPASS 0x51 1714 #define BPHY_CCK_DELAY_LONG 0x52 1715 #define BPHY_CCK_DELAY_SHORT 0x53 1716 #define BPHY_PPROC_CHAN_DELAY 0x54 1717 #define BPHY_DDFS_ENABLE 0x58 1718 #define BPHY_PHASE_SCALE 0x59 1719 #define BPHY_FREQ_CONTROL 0x5a 1720 #define BPHY_LNA_GAIN_RANGE_10 0x5b 1721 #define BPHY_LNA_GAIN_RANGE_32 0x5c 1722 #define BPHY_OPTIONAL_MODES 0x5d 1723 #define BPHY_RX_STATUS2 0x5e 1724 #define BPHY_RX_STATUS3 0x5f 1725 #define BPHY_DAC_CONTROL 0x60 1726 #define BPHY_ANA11G_FILT_CTRL 0x62 1727 #define BPHY_REFRESH_CTRL 0x64 1728 #define BPHY_RF_OVERRIDE2 0x65 1729 #define BPHY_SPUR_CANCEL_CTRL 0x66 1730 #define BPHY_FINE_DIGIGAIN_CTRL 0x67 1731 #define BPHY_RSSI_LUT 0x88 1732 #define BPHY_RSSI_LUT_END 0xa7 1733 #define BPHY_TSSI_LUT 0xa8 1734 #define BPHY_TSSI_LUT_END 0xc7 1735 #define BPHY_TSSI2PWR_LUT 0x380 1736 #define BPHY_TSSI2PWR_LUT_END 0x39f 1737 #define BPHY_LOCOMP_LUT 0x3a0 1738 #define BPHY_LOCOMP_LUT_END 0x3bf 1739 #define BPHY_TXGAIN_LUT 0x3c0 1740 #define BPHY_TXGAIN_LUT_END 0x3ff 1741 1742 /* Bits in BB_CONFIG: */ 1743 #define PHY_BBC_ANT_MASK 0x0180 1744 #define PHY_BBC_ANT_SHIFT 7 1745 #define BB_DARWIN 0x1000 1746 #define BBCFG_RESETCCA 0x4000 1747 #define BBCFG_RESETRX 0x8000 1748 1749 /* Bits in phytest(0x0a): */ 1750 #define TST_DDFS 0x2000 1751 #define TST_TXFILT1 0x0800 1752 #define TST_UNSCRAM 0x0400 1753 #define TST_CARR_SUPP 0x0200 1754 #define TST_DC_COMP_LOOP 0x0100 1755 #define TST_LOOPBACK 0x0080 1756 #define TST_TXFILT0 0x0040 1757 #define TST_TXTEST_ENABLE 0x0020 1758 #define TST_TXTEST_RATE 0x0018 1759 #define TST_TXTEST_PHASE 0x0007 1760 1761 /* phytest txTestRate values */ 1762 #define TST_TXTEST_RATE_1MBPS 0 1763 #define TST_TXTEST_RATE_2MBPS 1 1764 #define TST_TXTEST_RATE_5_5MBPS 2 1765 #define TST_TXTEST_RATE_11MBPS 3 1766 #define TST_TXTEST_RATE_SHIFT 3 1767 1768 #define SHM_BYT_CNT 0x2 /* IHR location */ 1769 #define MAX_BYT_CNT 0x600 /* Maximum frame len */ 1770 1771 #endif /* _D11_H */ 1772