1 /* i830_drv.h -- Private header for the I830 driver -*- linux-c -*- 2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com> 28 * Jeff Hartmann <jhartmann@valinux.com> 29 * 30 */ 31 32 #ifndef _I830_DRV_H_ 33 #define _I830_DRV_H_ 34 35 typedef struct drm_i830_buf_priv { 36 u32 *in_use; 37 int my_use_idx; 38 int currently_mapped; 39 void *virtual; 40 void *kernel_virtual; 41 int map_count; 42 struct vm_area_struct *vma; 43 } drm_i830_buf_priv_t; 44 45 typedef struct _drm_i830_ring_buffer{ 46 int tail_mask; 47 unsigned long Start; 48 unsigned long End; 49 unsigned long Size; 50 u8 *virtual_start; 51 int head; 52 int tail; 53 int space; 54 } drm_i830_ring_buffer_t; 55 56 typedef struct drm_i830_private { 57 drm_map_t *sarea_map; 58 drm_map_t *buffer_map; 59 drm_map_t *mmio_map; 60 61 drm_i830_sarea_t *sarea_priv; 62 drm_i830_ring_buffer_t ring; 63 64 unsigned long hw_status_page; 65 unsigned long counter; 66 67 dma_addr_t dma_status_page; 68 69 drm_buf_t *mmap_buffer; 70 71 u32 front_di1, back_di1, zi1; 72 73 int back_offset; 74 int depth_offset; 75 int front_offset; 76 int w, h; 77 int pitch; 78 int back_pitch; 79 int depth_pitch; 80 unsigned int cpp; 81 82 int do_boxes; 83 int dma_used; 84 85 int current_page; 86 int page_flipping; 87 88 wait_queue_head_t irq_queue; 89 atomic_t irq_received; 90 atomic_t irq_emitted; 91 92 int use_mi_batchbuffer_start; 93 94 } drm_i830_private_t; 95 96 /* i830_dma.c */ 97 extern int i830_dma_schedule(drm_device_t *dev, int locked); 98 extern int i830_getbuf(struct inode *inode, struct file *filp, 99 unsigned int cmd, unsigned long arg); 100 extern int i830_dma_init(struct inode *inode, struct file *filp, 101 unsigned int cmd, unsigned long arg); 102 extern int i830_flush_ioctl(struct inode *inode, struct file *filp, 103 unsigned int cmd, unsigned long arg); 104 extern void i830_reclaim_buffers(drm_device_t *dev, pid_t pid); 105 extern int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd, 106 unsigned long arg); 107 extern int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma); 108 extern int i830_copybuf(struct inode *inode, struct file *filp, 109 unsigned int cmd, unsigned long arg); 110 extern int i830_docopy(struct inode *inode, struct file *filp, 111 unsigned int cmd, unsigned long arg); 112 113 extern void i830_dma_quiescent(drm_device_t *dev); 114 115 extern int i830_dma_vertex(struct inode *inode, struct file *filp, 116 unsigned int cmd, unsigned long arg); 117 118 extern int i830_swap_bufs(struct inode *inode, struct file *filp, 119 unsigned int cmd, unsigned long arg); 120 121 extern int i830_clear_bufs(struct inode *inode, struct file *filp, 122 unsigned int cmd, unsigned long arg); 123 124 extern int i830_flip_bufs(struct inode *inode, struct file *filp, 125 unsigned int cmd, unsigned long arg); 126 127 extern int i830_getparam( struct inode *inode, struct file *filp, 128 unsigned int cmd, unsigned long arg ); 129 130 extern int i830_setparam( struct inode *inode, struct file *filp, 131 unsigned int cmd, unsigned long arg ); 132 133 /* i830_irq.c */ 134 extern int i830_irq_emit( struct inode *inode, struct file *filp, 135 unsigned int cmd, unsigned long arg ); 136 extern int i830_irq_wait( struct inode *inode, struct file *filp, 137 unsigned int cmd, unsigned long arg ); 138 extern int i830_wait_irq(drm_device_t *dev, int irq_nr); 139 extern int i830_emit_irq(drm_device_t *dev); 140 141 142 #define I830_BASE(reg) ((unsigned long) \ 143 dev_priv->mmio_map->handle) 144 #define I830_ADDR(reg) (I830_BASE(reg) + reg) 145 #define I830_DEREF(reg) *(__volatile__ unsigned int *)I830_ADDR(reg) 146 #define I830_READ(reg) readl((volatile u32 *)I830_ADDR(reg)) 147 #define I830_WRITE(reg,val) writel(val, (volatile u32 *)I830_ADDR(reg)) 148 #define I830_DEREF16(reg) *(__volatile__ u16 *)I830_ADDR(reg) 149 #define I830_READ16(reg) I830_DEREF16(reg) 150 #define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0) 151 152 153 154 #define I830_VERBOSE 0 155 156 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 157 volatile char *virt; 158 159 #define BEGIN_LP_RING(n) do { \ 160 if (I830_VERBOSE) \ 161 printk("BEGIN_LP_RING(%d) in %s\n", \ 162 n, __FUNCTION__); \ 163 if (dev_priv->ring.space < n*4) \ 164 i830_wait_ring(dev, n*4, __FUNCTION__); \ 165 outcount = 0; \ 166 outring = dev_priv->ring.tail; \ 167 ringmask = dev_priv->ring.tail_mask; \ 168 virt = dev_priv->ring.virtual_start; \ 169 } while (0) 170 171 172 #define OUT_RING(n) do { \ 173 if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \ 174 *(volatile unsigned int *)(virt + outring) = n; \ 175 outcount++; \ 176 outring += 4; \ 177 outring &= ringmask; \ 178 } while (0) 179 180 #define ADVANCE_LP_RING() do { \ 181 if (I830_VERBOSE) printk("ADVANCE_LP_RING %x\n", outring); \ 182 dev_priv->ring.tail = outring; \ 183 dev_priv->ring.space -= outcount * 4; \ 184 I830_WRITE(LP_RING + RING_TAIL, outring); \ 185 } while(0) 186 187 extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); 188 189 190 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 191 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 192 #define CMD_REPORT_HEAD (7<<23) 193 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 194 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 195 196 #define STATE3D_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)|(0x1d<<24)|(0x03<<16)) 197 #define LOAD_TEXTURE_MAP0 (1<<11) 198 199 #define INST_PARSER_CLIENT 0x00000000 200 #define INST_OP_FLUSH 0x02000000 201 #define INST_FLUSH_MAP_CACHE 0x00000001 202 203 204 #define BB1_START_ADDR_MASK (~0x7) 205 #define BB1_PROTECTED (1<<0) 206 #define BB1_UNPROTECTED (0<<0) 207 #define BB2_END_ADDR_MASK (~0x7) 208 209 #define I830REG_HWSTAM 0x02098 210 #define I830REG_INT_IDENTITY_R 0x020a4 211 #define I830REG_INT_MASK_R 0x020a8 212 #define I830REG_INT_ENABLE_R 0x020a0 213 214 #define I830_IRQ_RESERVED ((1<<13)|(3<<2)) 215 216 217 #define LP_RING 0x2030 218 #define HP_RING 0x2040 219 #define RING_TAIL 0x00 220 #define TAIL_ADDR 0x001FFFF8 221 #define RING_HEAD 0x04 222 #define HEAD_WRAP_COUNT 0xFFE00000 223 #define HEAD_WRAP_ONE 0x00200000 224 #define HEAD_ADDR 0x001FFFFC 225 #define RING_START 0x08 226 #define START_ADDR 0x0xFFFFF000 227 #define RING_LEN 0x0C 228 #define RING_NR_PAGES 0x001FF000 229 #define RING_REPORT_MASK 0x00000006 230 #define RING_REPORT_64K 0x00000002 231 #define RING_REPORT_128K 0x00000004 232 #define RING_NO_REPORT 0x00000000 233 #define RING_VALID_MASK 0x00000001 234 #define RING_VALID 0x00000001 235 #define RING_INVALID 0x00000000 236 237 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 238 #define SC_UPDATE_SCISSOR (0x1<<1) 239 #define SC_ENABLE_MASK (0x1<<0) 240 #define SC_ENABLE (0x1<<0) 241 242 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 243 #define SCI_YMIN_MASK (0xffff<<16) 244 #define SCI_XMIN_MASK (0xffff<<0) 245 #define SCI_YMAX_MASK (0xffff<<16) 246 #define SCI_XMAX_MASK (0xffff<<0) 247 248 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 249 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 250 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 251 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 252 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 253 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 254 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 255 #define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24)) 256 257 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 258 259 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 260 #define ASYNC_FLIP (1<<22) 261 262 #define CMD_3D (0x3<<29) 263 #define STATE3D_CONST_BLEND_COLOR_CMD (CMD_3D|(0x1d<<24)|(0x88<<16)) 264 #define STATE3D_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16)) 265 266 #define BR00_BITBLT_CLIENT 0x40000000 267 #define BR00_OP_COLOR_BLT 0x10000000 268 #define BR00_OP_SRC_COPY_BLT 0x10C00000 269 #define BR13_SOLID_PATTERN 0x80000000 270 271 #define BUF_3D_ID_COLOR_BACK (0x3<<24) 272 #define BUF_3D_ID_DEPTH (0x7<<24) 273 #define BUF_3D_USE_FENCE (1<<23) 274 #define BUF_3D_PITCH(x) (((x)/4)<<2) 275 276 #define CMD_OP_MAP_PALETTE_LOAD ((3<<29)|(0x1d<<24)|(0x82<<16)|255) 277 #define MAP_PALETTE_NUM(x) ((x<<8) & (1<<8)) 278 #define MAP_PALETTE_BOTH (1<<11) 279 280 #define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4) 281 #define XY_COLOR_BLT_WRITE_ALPHA (1<<21) 282 #define XY_COLOR_BLT_WRITE_RGB (1<<20) 283 284 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 285 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 286 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 287 288 #define MI_BATCH_BUFFER ((0x30<<23)|1) 289 #define MI_BATCH_BUFFER_START (0x31<<23) 290 #define MI_BATCH_BUFFER_END (0xA<<23) 291 #define MI_BATCH_NON_SECURE (1) 292 293 #define MI_WAIT_FOR_EVENT ((0x3<<23)) 294 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 295 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 296 297 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 298 299 #endif 300 301