1 /* 2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2008-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 #ifndef _ASM_MICROBLAZE_MMU_H 12 #define _ASM_MICROBLAZE_MMU_H 13 14 # ifndef CONFIG_MMU 15 # include <asm-generic/mmu.h> 16 # else /* CONFIG_MMU */ 17 # ifdef __KERNEL__ 18 # ifndef __ASSEMBLY__ 19 20 /* Default "unsigned long" context */ 21 typedef unsigned long mm_context_t; 22 23 /* Hardware Page Table Entry */ 24 typedef struct _PTE { 25 unsigned long v:1; /* Entry is valid */ 26 unsigned long vsid:24; /* Virtual segment identifier */ 27 unsigned long h:1; /* Hash algorithm indicator */ 28 unsigned long api:6; /* Abbreviated page index */ 29 unsigned long rpn:20; /* Real (physical) page number */ 30 unsigned long :3; /* Unused */ 31 unsigned long r:1; /* Referenced */ 32 unsigned long c:1; /* Changed */ 33 unsigned long w:1; /* Write-thru cache mode */ 34 unsigned long i:1; /* Cache inhibited */ 35 unsigned long m:1; /* Memory coherence */ 36 unsigned long g:1; /* Guarded */ 37 unsigned long :1; /* Unused */ 38 unsigned long pp:2; /* Page protection */ 39 } PTE; 40 41 /* Values for PP (assumes Ks=0, Kp=1) */ 42 # define PP_RWXX 0 /* Supervisor read/write, User none */ 43 # define PP_RWRX 1 /* Supervisor read/write, User read */ 44 # define PP_RWRW 2 /* Supervisor read/write, User read/write */ 45 # define PP_RXRX 3 /* Supervisor read, User read */ 46 47 /* Segment Register */ 48 typedef struct _SEGREG { 49 unsigned long t:1; /* Normal or I/O type */ 50 unsigned long ks:1; /* Supervisor 'key' (normally 0) */ 51 unsigned long kp:1; /* User 'key' (normally 1) */ 52 unsigned long n:1; /* No-execute */ 53 unsigned long :4; /* Unused */ 54 unsigned long vsid:24; /* Virtual Segment Identifier */ 55 } SEGREG; 56 57 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ 58 extern void _tlbia(void); /* invalidate all TLB entries */ 59 60 /* 61 * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB 62 * mapping has to increase tlb_skip size. 63 */ 64 extern u32 tlb_skip; 65 # endif /* __ASSEMBLY__ */ 66 67 /* 68 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The 69 * instruction and data sides share a unified, 64-entry, semi-associative 70 * TLB which is maintained totally under software control. In addition, the 71 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative 72 * TLB which serves as a first level to the shared TLB. These two TLBs are 73 * known as the UTLB and ITLB, respectively. 74 */ 75 76 # define MICROBLAZE_TLB_SIZE 64 77 78 /* For cases when you want to skip some TLB entries */ 79 # define MICROBLAZE_TLB_SKIP 0 80 81 /* Use the last TLB for temporary access to LMB */ 82 # define MICROBLAZE_LMB_TLB_ID 63 83 84 /* 85 * TLB entries are defined by a "high" tag portion and a "low" data 86 * portion. The data portion is 32-bits. 87 * 88 * TLB entries are managed entirely under software control by reading, 89 * writing, and searching using the MTS and MFS instructions. 90 */ 91 92 # define TLB_LO 1 93 # define TLB_HI 0 94 # define TLB_DATA TLB_LO 95 # define TLB_TAG TLB_HI 96 97 /* Tag portion */ 98 # define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ 99 # define TLB_PAGESZ_MASK 0x00000380 100 # define TLB_PAGESZ(x) (((x) & 0x7) << 7) 101 # define PAGESZ_1K 0 102 # define PAGESZ_4K 1 103 # define PAGESZ_16K 2 104 # define PAGESZ_64K 3 105 # define PAGESZ_256K 4 106 # define PAGESZ_1M 5 107 # define PAGESZ_4M 6 108 # define PAGESZ_16M 7 109 # define TLB_VALID 0x00000040 /* Entry is valid */ 110 111 /* Data portion */ 112 # define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ 113 # define TLB_PERM_MASK 0x00000300 114 # define TLB_EX 0x00000200 /* Instruction execution allowed */ 115 # define TLB_WR 0x00000100 /* Writes permitted */ 116 # define TLB_ZSEL_MASK 0x000000F0 117 # define TLB_ZSEL(x) (((x) & 0xF) << 4) 118 # define TLB_ATTR_MASK 0x0000000F 119 # define TLB_W 0x00000008 /* Caching is write-through */ 120 # define TLB_I 0x00000004 /* Caching is inhibited */ 121 # define TLB_M 0x00000002 /* Memory is coherent */ 122 # define TLB_G 0x00000001 /* Memory is guarded from prefetch */ 123 124 # endif /* __KERNEL__ */ 125 # endif /* CONFIG_MMU */ 126 #endif /* _ASM_MICROBLAZE_MMU_H */ 127