1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3  *
4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6  * All rights reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25  * OTHER DEALINGS IN THE SOFTWARE.
26  *
27  * Authors:
28  *    Gareth Hughes <gareth@valinux.com>
29  */
30 
31 #ifndef __MGA_DRV_H__
32 #define __MGA_DRV_H__
33 
34 #include <linux/irqreturn.h>
35 #include <linux/pci.h>
36 #include <linux/slab.h>
37 
38 #include <drm/drm_device.h>
39 #include <drm/drm_file.h>
40 #include <drm/drm_ioctl.h>
41 #include <drm/drm_legacy.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_sarea.h>
44 #include <drm/drm_vblank.h>
45 #include <drm/mga_drm.h>
46 
47 /* General customization:
48  */
49 
50 #define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
51 
52 #define DRIVER_NAME		"mga"
53 #define DRIVER_DESC		"Matrox G200/G400"
54 #define DRIVER_DATE		"20051102"
55 
56 #define DRIVER_MAJOR		3
57 #define DRIVER_MINOR		2
58 #define DRIVER_PATCHLEVEL	1
59 
60 typedef struct drm_mga_primary_buffer {
61 	u8 *start;
62 	u8 *end;
63 	int size;
64 
65 	u32 tail;
66 	int space;
67 	volatile long wrapped;
68 
69 	volatile u32 *status;
70 
71 	u32 last_flush;
72 	u32 last_wrap;
73 
74 	u32 high_mark;
75 } drm_mga_primary_buffer_t;
76 
77 typedef struct drm_mga_freelist {
78 	struct drm_mga_freelist *next;
79 	struct drm_mga_freelist *prev;
80 	drm_mga_age_t age;
81 	struct drm_buf *buf;
82 } drm_mga_freelist_t;
83 
84 typedef struct {
85 	drm_mga_freelist_t *list_entry;
86 	int discard;
87 	int dispatched;
88 } drm_mga_buf_priv_t;
89 
90 typedef struct drm_mga_private {
91 	drm_mga_primary_buffer_t prim;
92 	drm_mga_sarea_t *sarea_priv;
93 
94 	drm_mga_freelist_t *head;
95 	drm_mga_freelist_t *tail;
96 
97 	unsigned int warp_pipe;
98 	unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
99 
100 	int chipset;
101 	int usec_timeout;
102 
103 	/**
104 	 * If set, the new DMA initialization sequence was used.  This is
105 	 * primarilly used to select how the driver should uninitialized its
106 	 * internal DMA structures.
107 	 */
108 	int used_new_dma_init;
109 
110 	/**
111 	 * If AGP memory is used for DMA buffers, this will be the value
112 	 * \c MGA_PAGPXFER.  Otherwise, it will be zero (for a PCI transfer).
113 	 */
114 	u32 dma_access;
115 
116 	/**
117 	 * If AGP memory is used for DMA buffers, this will be the value
118 	 * \c MGA_WAGP_ENABLE.  Otherwise, it will be zero (for a PCI
119 	 * transfer).
120 	 */
121 	u32 wagp_enable;
122 
123 	/**
124 	 * \name MMIO region parameters.
125 	 *
126 	 * \sa drm_mga_private_t::mmio
127 	 */
128 	/*@{ */
129 	resource_size_t mmio_base;	   /**< Bus address of base of MMIO. */
130 	resource_size_t mmio_size;	   /**< Size of the MMIO region. */
131 	/*@} */
132 
133 	u32 clear_cmd;
134 	u32 maccess;
135 
136 	atomic_t vbl_received;          /**< Number of vblanks received. */
137 	wait_queue_head_t fence_queue;
138 	atomic_t last_fence_retired;
139 	u32 next_fence_to_post;
140 
141 	unsigned int fb_cpp;
142 	unsigned int front_offset;
143 	unsigned int front_pitch;
144 	unsigned int back_offset;
145 	unsigned int back_pitch;
146 
147 	unsigned int depth_cpp;
148 	unsigned int depth_offset;
149 	unsigned int depth_pitch;
150 
151 	unsigned int texture_offset;
152 	unsigned int texture_size;
153 
154 	drm_local_map_t *sarea;
155 	drm_local_map_t *mmio;
156 	drm_local_map_t *status;
157 	drm_local_map_t *warp;
158 	drm_local_map_t *primary;
159 	drm_local_map_t *agp_textures;
160 
161 	unsigned long agp_handle;
162 	unsigned int agp_size;
163 } drm_mga_private_t;
164 
165 extern const struct drm_ioctl_desc mga_ioctls[];
166 extern int mga_max_ioctl;
167 
168 				/* mga_dma.c */
169 extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
170 			     struct drm_file *file_priv);
171 extern int mga_dma_init(struct drm_device *dev, void *data,
172 			struct drm_file *file_priv);
173 extern int mga_getparam(struct drm_device *dev, void *data,
174 			struct drm_file *file_priv);
175 extern int mga_dma_flush(struct drm_device *dev, void *data,
176 			 struct drm_file *file_priv);
177 extern int mga_dma_reset(struct drm_device *dev, void *data,
178 			 struct drm_file *file_priv);
179 extern int mga_dma_buffers(struct drm_device *dev, void *data,
180 			   struct drm_file *file_priv);
181 extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
182 extern void mga_driver_unload(struct drm_device *dev);
183 extern void mga_driver_lastclose(struct drm_device *dev);
184 extern int mga_driver_dma_quiescent(struct drm_device *dev);
185 
186 extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv);
187 
188 extern void mga_do_dma_flush(drm_mga_private_t *dev_priv);
189 extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv);
190 extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv);
191 
192 extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf);
193 
194 				/* mga_warp.c */
195 extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv);
196 extern int mga_warp_init(drm_mga_private_t *dev_priv);
197 
198 				/* mga_irq.c */
199 extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe);
200 extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe);
201 extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
202 extern void mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
203 extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
204 extern irqreturn_t mga_driver_irq_handler(int irq, void *arg);
205 extern void mga_driver_irq_preinstall(struct drm_device *dev);
206 extern int mga_driver_irq_postinstall(struct drm_device *dev);
207 extern void mga_driver_irq_uninstall(struct drm_device *dev);
208 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
209 			     unsigned long arg);
210 
211 #define mga_flush_write_combine()	wmb()
212 
213 #define MGA_READ8(reg) \
214 	readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
215 #define MGA_READ(reg) \
216 	readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
217 #define MGA_WRITE8(reg, val) \
218 	writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
219 #define MGA_WRITE(reg, val) \
220 	writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
221 
222 #define DWGREG0		0x1c00
223 #define DWGREG0_END	0x1dff
224 #define DWGREG1		0x2c00
225 #define DWGREG1_END	0x2dff
226 
227 #define ISREG0(r)	(r >= DWGREG0 && r <= DWGREG0_END)
228 #define DMAREG0(r)	(u8)((r - DWGREG0) >> 2)
229 #define DMAREG1(r)	(u8)(((r - DWGREG1) >> 2) | 0x80)
230 #define DMAREG(r)	(ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
231 
232 /* ================================================================
233  * Helper macross...
234  */
235 
236 #define MGA_EMIT_STATE(dev_priv, dirty)					\
237 do {									\
238 	if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) {				\
239 		if (dev_priv->chipset >= MGA_CARD_TYPE_G400)		\
240 			mga_g400_emit_state(dev_priv);			\
241 		else							\
242 			mga_g200_emit_state(dev_priv);			\
243 	}								\
244 } while (0)
245 
246 #define WRAP_TEST_WITH_RETURN(dev_priv)					\
247 do {									\
248 	if (test_bit(0, &dev_priv->prim.wrapped)) {			\
249 		if (mga_is_idle(dev_priv)) {				\
250 			mga_do_dma_wrap_end(dev_priv);			\
251 		} else if (dev_priv->prim.space <			\
252 			   dev_priv->prim.high_mark) {			\
253 			if (MGA_DMA_DEBUG)				\
254 				DRM_INFO("wrap...\n");			\
255 			return -EBUSY;					\
256 		}							\
257 	}								\
258 } while (0)
259 
260 #define WRAP_WAIT_WITH_RETURN(dev_priv)					\
261 do {									\
262 	if (test_bit(0, &dev_priv->prim.wrapped)) {			\
263 		if (mga_do_wait_for_idle(dev_priv) < 0) {		\
264 			if (MGA_DMA_DEBUG)				\
265 				DRM_INFO("wrap...\n");			\
266 			return -EBUSY;					\
267 		}							\
268 		mga_do_dma_wrap_end(dev_priv);				\
269 	}								\
270 } while (0)
271 
272 /* ================================================================
273  * Primary DMA command stream
274  */
275 
276 #define MGA_VERBOSE	0
277 
278 #define DMA_LOCALS	unsigned int write; volatile u8 *prim;
279 
280 #define DMA_BLOCK_SIZE	(5 * sizeof(u32))
281 
282 #define BEGIN_DMA(n)							\
283 do {									\
284 	if (MGA_VERBOSE) {						\
285 		DRM_INFO("BEGIN_DMA(%d)\n", (n));			\
286 		DRM_INFO("   space=0x%x req=0x%zx\n",			\
287 			 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE);	\
288 	}								\
289 	prim = dev_priv->prim.start;					\
290 	write = dev_priv->prim.tail;					\
291 } while (0)
292 
293 #define BEGIN_DMA_WRAP()						\
294 do {									\
295 	if (MGA_VERBOSE) {						\
296 		DRM_INFO("BEGIN_DMA()\n");				\
297 		DRM_INFO("   space=0x%x\n", dev_priv->prim.space);	\
298 	}								\
299 	prim = dev_priv->prim.start;					\
300 	write = dev_priv->prim.tail;					\
301 } while (0)
302 
303 #define ADVANCE_DMA()							\
304 do {									\
305 	dev_priv->prim.tail = write;					\
306 	if (MGA_VERBOSE)						\
307 		DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n",		\
308 			 write, dev_priv->prim.space);			\
309 } while (0)
310 
311 #define FLUSH_DMA()							\
312 do {									\
313 	if (0) {							\
314 		DRM_INFO("\n");						\
315 		DRM_INFO("   tail=0x%06x head=0x%06lx\n",		\
316 			 dev_priv->prim.tail,				\
317 			 (unsigned long)(MGA_READ(MGA_PRIMADDRESS) -	\
318 					 dev_priv->primary->offset));	\
319 	}								\
320 	if (!test_bit(0, &dev_priv->prim.wrapped)) {			\
321 		if (dev_priv->prim.space < dev_priv->prim.high_mark)	\
322 			mga_do_dma_wrap_start(dev_priv);		\
323 		else							\
324 			mga_do_dma_flush(dev_priv);			\
325 	}								\
326 } while (0)
327 
328 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
329  */
330 #define DMA_WRITE(offset, val)						\
331 do {									\
332 	if (MGA_VERBOSE)						\
333 		DRM_INFO("   DMA_WRITE( 0x%08x ) at 0x%04zx\n",		\
334 			 (u32)(val), write + (offset) * sizeof(u32));	\
335 	*(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val;	\
336 } while (0)
337 
338 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3)	\
339 do {									\
340 	DMA_WRITE(0, ((DMAREG(reg0) << 0) |				\
341 		      (DMAREG(reg1) << 8) |				\
342 		      (DMAREG(reg2) << 16) |				\
343 		      (DMAREG(reg3) << 24)));				\
344 	DMA_WRITE(1, val0);						\
345 	DMA_WRITE(2, val1);						\
346 	DMA_WRITE(3, val2);						\
347 	DMA_WRITE(4, val3);						\
348 	write += DMA_BLOCK_SIZE;					\
349 } while (0)
350 
351 /* Buffer aging via primary DMA stream head pointer.
352  */
353 
354 #define SET_AGE(age, h, w)						\
355 do {									\
356 	(age)->head = h;						\
357 	(age)->wrap = w;						\
358 } while (0)
359 
360 #define TEST_AGE(age, h, w)		((age)->wrap < w ||		\
361 					 ((age)->wrap == w &&		\
362 					  (age)->head < h))
363 
364 #define AGE_BUFFER(buf_priv)						\
365 do {									\
366 	drm_mga_freelist_t *entry = (buf_priv)->list_entry;		\
367 	if ((buf_priv)->dispatched) {					\
368 		entry->age.head = (dev_priv->prim.tail +		\
369 				   dev_priv->primary->offset);		\
370 		entry->age.wrap = dev_priv->sarea_priv->last_wrap;	\
371 	} else {							\
372 		entry->age.head = 0;					\
373 		entry->age.wrap = 0;					\
374 	}								\
375 } while (0)
376 
377 #define MGA_ENGINE_IDLE_MASK		(MGA_SOFTRAPEN |		\
378 					 MGA_DWGENGSTS |		\
379 					 MGA_ENDPRDMASTS)
380 #define MGA_DMA_IDLE_MASK		(MGA_SOFTRAPEN |		\
381 					 MGA_ENDPRDMASTS)
382 
383 #define MGA_DMA_DEBUG			0
384 
385 /* A reduced set of the mga registers.
386  */
387 #define MGA_CRTC_INDEX			0x1fd4
388 #define MGA_CRTC_DATA			0x1fd5
389 
390 /* CRTC11 */
391 #define MGA_VINTCLR			(1 << 4)
392 #define MGA_VINTEN			(1 << 5)
393 
394 #define MGA_ALPHACTRL			0x2c7c
395 #define MGA_AR0				0x1c60
396 #define MGA_AR1				0x1c64
397 #define MGA_AR2				0x1c68
398 #define MGA_AR3				0x1c6c
399 #define MGA_AR4				0x1c70
400 #define MGA_AR5				0x1c74
401 #define MGA_AR6				0x1c78
402 
403 #define MGA_CXBNDRY			0x1c80
404 #define MGA_CXLEFT			0x1ca0
405 #define MGA_CXRIGHT			0x1ca4
406 
407 #define MGA_DMAPAD			0x1c54
408 #define MGA_DSTORG			0x2cb8
409 #define MGA_DWGCTL			0x1c00
410 #	define MGA_OPCOD_MASK			(15 << 0)
411 #	define MGA_OPCOD_TRAP			(4 << 0)
412 #	define MGA_OPCOD_TEXTURE_TRAP		(6 << 0)
413 #	define MGA_OPCOD_BITBLT			(8 << 0)
414 #	define MGA_OPCOD_ILOAD			(9 << 0)
415 #	define MGA_ATYPE_MASK			(7 << 4)
416 #	define MGA_ATYPE_RPL			(0 << 4)
417 #	define MGA_ATYPE_RSTR			(1 << 4)
418 #	define MGA_ATYPE_ZI			(3 << 4)
419 #	define MGA_ATYPE_BLK			(4 << 4)
420 #	define MGA_ATYPE_I			(7 << 4)
421 #	define MGA_LINEAR			(1 << 7)
422 #	define MGA_ZMODE_MASK			(7 << 8)
423 #	define MGA_ZMODE_NOZCMP			(0 << 8)
424 #	define MGA_ZMODE_ZE			(2 << 8)
425 #	define MGA_ZMODE_ZNE			(3 << 8)
426 #	define MGA_ZMODE_ZLT			(4 << 8)
427 #	define MGA_ZMODE_ZLTE			(5 << 8)
428 #	define MGA_ZMODE_ZGT			(6 << 8)
429 #	define MGA_ZMODE_ZGTE			(7 << 8)
430 #	define MGA_SOLID			(1 << 11)
431 #	define MGA_ARZERO			(1 << 12)
432 #	define MGA_SGNZERO			(1 << 13)
433 #	define MGA_SHIFTZERO			(1 << 14)
434 #	define MGA_BOP_MASK			(15 << 16)
435 #	define MGA_BOP_ZERO			(0 << 16)
436 #	define MGA_BOP_DST			(10 << 16)
437 #	define MGA_BOP_SRC			(12 << 16)
438 #	define MGA_BOP_ONE			(15 << 16)
439 #	define MGA_TRANS_SHIFT			20
440 #	define MGA_TRANS_MASK			(15 << 20)
441 #	define MGA_BLTMOD_MASK			(15 << 25)
442 #	define MGA_BLTMOD_BMONOLEF		(0 << 25)
443 #	define MGA_BLTMOD_BMONOWF		(4 << 25)
444 #	define MGA_BLTMOD_PLAN			(1 << 25)
445 #	define MGA_BLTMOD_BFCOL			(2 << 25)
446 #	define MGA_BLTMOD_BU32BGR		(3 << 25)
447 #	define MGA_BLTMOD_BU32RGB		(7 << 25)
448 #	define MGA_BLTMOD_BU24BGR		(11 << 25)
449 #	define MGA_BLTMOD_BU24RGB		(15 << 25)
450 #	define MGA_PATTERN			(1 << 29)
451 #	define MGA_TRANSC			(1 << 30)
452 #	define MGA_CLIPDIS			(1 << 31)
453 #define MGA_DWGSYNC			0x2c4c
454 
455 #define MGA_FCOL			0x1c24
456 #define MGA_FIFOSTATUS			0x1e10
457 #define MGA_FOGCOL			0x1cf4
458 #define MGA_FXBNDRY			0x1c84
459 #define MGA_FXLEFT			0x1ca8
460 #define MGA_FXRIGHT			0x1cac
461 
462 #define MGA_ICLEAR			0x1e18
463 #	define MGA_SOFTRAPICLR			(1 << 0)
464 #	define MGA_VLINEICLR			(1 << 5)
465 #define MGA_IEN				0x1e1c
466 #	define MGA_SOFTRAPIEN			(1 << 0)
467 #	define MGA_VLINEIEN			(1 << 5)
468 
469 #define MGA_LEN				0x1c5c
470 
471 #define MGA_MACCESS			0x1c04
472 
473 #define MGA_PITCH			0x1c8c
474 #define MGA_PLNWT			0x1c1c
475 #define MGA_PRIMADDRESS			0x1e58
476 #	define MGA_DMA_GENERAL			(0 << 0)
477 #	define MGA_DMA_BLIT			(1 << 0)
478 #	define MGA_DMA_VECTOR			(2 << 0)
479 #	define MGA_DMA_VERTEX			(3 << 0)
480 #define MGA_PRIMEND			0x1e5c
481 #	define MGA_PRIMNOSTART			(1 << 0)
482 #	define MGA_PAGPXFER			(1 << 1)
483 #define MGA_PRIMPTR			0x1e50
484 #	define MGA_PRIMPTREN0			(1 << 0)
485 #	define MGA_PRIMPTREN1			(1 << 1)
486 
487 #define MGA_RST				0x1e40
488 #	define MGA_SOFTRESET			(1 << 0)
489 #	define MGA_SOFTEXTRST			(1 << 1)
490 
491 #define MGA_SECADDRESS			0x2c40
492 #define MGA_SECEND			0x2c44
493 #define MGA_SETUPADDRESS		0x2cd0
494 #define MGA_SETUPEND			0x2cd4
495 #define MGA_SGN				0x1c58
496 #define MGA_SOFTRAP			0x2c48
497 #define MGA_SRCORG			0x2cb4
498 #	define MGA_SRMMAP_MASK			(1 << 0)
499 #	define MGA_SRCMAP_FB			(0 << 0)
500 #	define MGA_SRCMAP_SYSMEM		(1 << 0)
501 #	define MGA_SRCACC_MASK			(1 << 1)
502 #	define MGA_SRCACC_PCI			(0 << 1)
503 #	define MGA_SRCACC_AGP			(1 << 1)
504 #define MGA_STATUS			0x1e14
505 #	define MGA_SOFTRAPEN			(1 << 0)
506 #	define MGA_VSYNCPEN			(1 << 4)
507 #	define MGA_VLINEPEN			(1 << 5)
508 #	define MGA_DWGENGSTS			(1 << 16)
509 #	define MGA_ENDPRDMASTS			(1 << 17)
510 #define MGA_STENCIL			0x2cc8
511 #define MGA_STENCILCTL			0x2ccc
512 
513 #define MGA_TDUALSTAGE0			0x2cf8
514 #define MGA_TDUALSTAGE1			0x2cfc
515 #define MGA_TEXBORDERCOL		0x2c5c
516 #define MGA_TEXCTL			0x2c30
517 #define MGA_TEXCTL2			0x2c3c
518 #	define MGA_DUALTEX			(1 << 7)
519 #	define MGA_G400_TC2_MAGIC		(1 << 15)
520 #	define MGA_MAP1_ENABLE			(1 << 31)
521 #define MGA_TEXFILTER			0x2c58
522 #define MGA_TEXHEIGHT			0x2c2c
523 #define MGA_TEXORG			0x2c24
524 #	define MGA_TEXORGMAP_MASK		(1 << 0)
525 #	define MGA_TEXORGMAP_FB			(0 << 0)
526 #	define MGA_TEXORGMAP_SYSMEM		(1 << 0)
527 #	define MGA_TEXORGACC_MASK		(1 << 1)
528 #	define MGA_TEXORGACC_PCI		(0 << 1)
529 #	define MGA_TEXORGACC_AGP		(1 << 1)
530 #define MGA_TEXORG1			0x2ca4
531 #define MGA_TEXORG2			0x2ca8
532 #define MGA_TEXORG3			0x2cac
533 #define MGA_TEXORG4			0x2cb0
534 #define MGA_TEXTRANS			0x2c34
535 #define MGA_TEXTRANSHIGH		0x2c38
536 #define MGA_TEXWIDTH			0x2c28
537 
538 #define MGA_WACCEPTSEQ			0x1dd4
539 #define MGA_WCODEADDR			0x1e6c
540 #define MGA_WFLAG			0x1dc4
541 #define MGA_WFLAG1			0x1de0
542 #define MGA_WFLAGNB			0x1e64
543 #define MGA_WFLAGNB1			0x1e08
544 #define MGA_WGETMSB			0x1dc8
545 #define MGA_WIADDR			0x1dc0
546 #define MGA_WIADDR2			0x1dd8
547 #	define MGA_WMODE_SUSPEND		(0 << 0)
548 #	define MGA_WMODE_RESUME			(1 << 0)
549 #	define MGA_WMODE_JUMP			(2 << 0)
550 #	define MGA_WMODE_START			(3 << 0)
551 #	define MGA_WAGP_ENABLE			(1 << 2)
552 #define MGA_WMISC			0x1e70
553 #	define MGA_WUCODECACHE_ENABLE		(1 << 0)
554 #	define MGA_WMASTER_ENABLE		(1 << 1)
555 #	define MGA_WCACHEFLUSH_ENABLE		(1 << 3)
556 #define MGA_WVRTXSZ			0x1dcc
557 
558 #define MGA_YBOT			0x1c9c
559 #define MGA_YDST			0x1c90
560 #define MGA_YDSTLEN			0x1c88
561 #define MGA_YDSTORG			0x1c94
562 #define MGA_YTOP			0x1c98
563 
564 #define MGA_ZORG			0x1c0c
565 
566 /* This finishes the current batch of commands
567  */
568 #define MGA_EXEC			0x0100
569 
570 /* AGP PLL encoding (for G200 only).
571  */
572 #define MGA_AGP_PLL			0x1e4c
573 #	define MGA_AGP2XPLL_DISABLE		(0 << 0)
574 #	define MGA_AGP2XPLL_ENABLE		(1 << 0)
575 
576 /* Warp registers
577  */
578 #define MGA_WR0				0x2d00
579 #define MGA_WR1				0x2d04
580 #define MGA_WR2				0x2d08
581 #define MGA_WR3				0x2d0c
582 #define MGA_WR4				0x2d10
583 #define MGA_WR5				0x2d14
584 #define MGA_WR6				0x2d18
585 #define MGA_WR7				0x2d1c
586 #define MGA_WR8				0x2d20
587 #define MGA_WR9				0x2d24
588 #define MGA_WR10			0x2d28
589 #define MGA_WR11			0x2d2c
590 #define MGA_WR12			0x2d30
591 #define MGA_WR13			0x2d34
592 #define MGA_WR14			0x2d38
593 #define MGA_WR15			0x2d3c
594 #define MGA_WR16			0x2d40
595 #define MGA_WR17			0x2d44
596 #define MGA_WR18			0x2d48
597 #define MGA_WR19			0x2d4c
598 #define MGA_WR20			0x2d50
599 #define MGA_WR21			0x2d54
600 #define MGA_WR22			0x2d58
601 #define MGA_WR23			0x2d5c
602 #define MGA_WR24			0x2d60
603 #define MGA_WR25			0x2d64
604 #define MGA_WR26			0x2d68
605 #define MGA_WR27			0x2d6c
606 #define MGA_WR28			0x2d70
607 #define MGA_WR29			0x2d74
608 #define MGA_WR30			0x2d78
609 #define MGA_WR31			0x2d7c
610 #define MGA_WR32			0x2d80
611 #define MGA_WR33			0x2d84
612 #define MGA_WR34			0x2d88
613 #define MGA_WR35			0x2d8c
614 #define MGA_WR36			0x2d90
615 #define MGA_WR37			0x2d94
616 #define MGA_WR38			0x2d98
617 #define MGA_WR39			0x2d9c
618 #define MGA_WR40			0x2da0
619 #define MGA_WR41			0x2da4
620 #define MGA_WR42			0x2da8
621 #define MGA_WR43			0x2dac
622 #define MGA_WR44			0x2db0
623 #define MGA_WR45			0x2db4
624 #define MGA_WR46			0x2db8
625 #define MGA_WR47			0x2dbc
626 #define MGA_WR48			0x2dc0
627 #define MGA_WR49			0x2dc4
628 #define MGA_WR50			0x2dc8
629 #define MGA_WR51			0x2dcc
630 #define MGA_WR52			0x2dd0
631 #define MGA_WR53			0x2dd4
632 #define MGA_WR54			0x2dd8
633 #define MGA_WR55			0x2ddc
634 #define MGA_WR56			0x2de0
635 #define MGA_WR57			0x2de4
636 #define MGA_WR58			0x2de8
637 #define MGA_WR59			0x2dec
638 #define MGA_WR60			0x2df0
639 #define MGA_WR61			0x2df4
640 #define MGA_WR62			0x2df8
641 #define MGA_WR63			0x2dfc
642 #	define MGA_G400_WR_MAGIC		(1 << 6)
643 #	define MGA_G400_WR56_MAGIC		0x46480000	/* 12800.0f */
644 
645 #define MGA_ILOAD_ALIGN		64
646 #define MGA_ILOAD_MASK		(MGA_ILOAD_ALIGN - 1)
647 
648 #define MGA_DWGCTL_FLUSH	(MGA_OPCOD_TEXTURE_TRAP |		\
649 				 MGA_ATYPE_I |				\
650 				 MGA_ZMODE_NOZCMP |			\
651 				 MGA_ARZERO |				\
652 				 MGA_SGNZERO |				\
653 				 MGA_BOP_SRC |				\
654 				 (15 << MGA_TRANS_SHIFT))
655 
656 #define MGA_DWGCTL_CLEAR	(MGA_OPCOD_TRAP |			\
657 				 MGA_ZMODE_NOZCMP |			\
658 				 MGA_SOLID |				\
659 				 MGA_ARZERO |				\
660 				 MGA_SGNZERO |				\
661 				 MGA_SHIFTZERO |			\
662 				 MGA_BOP_SRC |				\
663 				 (0 << MGA_TRANS_SHIFT) |		\
664 				 MGA_BLTMOD_BMONOLEF |			\
665 				 MGA_TRANSC |				\
666 				 MGA_CLIPDIS)
667 
668 #define MGA_DWGCTL_COPY		(MGA_OPCOD_BITBLT |			\
669 				 MGA_ATYPE_RPL |			\
670 				 MGA_SGNZERO |				\
671 				 MGA_SHIFTZERO |			\
672 				 MGA_BOP_SRC |				\
673 				 (0 << MGA_TRANS_SHIFT) |		\
674 				 MGA_BLTMOD_BFCOL |			\
675 				 MGA_CLIPDIS)
676 
677 /* Simple idle test.
678  */
mga_is_idle(drm_mga_private_t * dev_priv)679 static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv)
680 {
681 	u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
682 	return (status == MGA_ENDPRDMASTS);
683 }
684 
685 #endif
686