1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __MGA_DRV_H__
32 #define __MGA_DRV_H__
33
34 typedef struct drm_mga_primary_buffer {
35 u8 *start;
36 u8 *end;
37 int size;
38
39 u32 tail;
40 int space;
41 volatile long wrapped;
42
43 volatile u32 *status;
44
45 u32 last_flush;
46 u32 last_wrap;
47
48 u32 high_mark;
49 } drm_mga_primary_buffer_t;
50
51 typedef struct drm_mga_freelist {
52 struct drm_mga_freelist *next;
53 struct drm_mga_freelist *prev;
54 drm_mga_age_t age;
55 drm_buf_t *buf;
56 } drm_mga_freelist_t;
57
58 typedef struct {
59 drm_mga_freelist_t *list_entry;
60 int discard;
61 int dispatched;
62 } drm_mga_buf_priv_t;
63
64 typedef struct drm_mga_private {
65 drm_mga_primary_buffer_t prim;
66 drm_mga_sarea_t *sarea_priv;
67
68 drm_mga_freelist_t *head;
69 drm_mga_freelist_t *tail;
70
71 unsigned int warp_pipe;
72 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
73
74 int chipset;
75 int usec_timeout;
76
77 u32 clear_cmd;
78 u32 maccess;
79
80 unsigned int fb_cpp;
81 unsigned int front_offset;
82 unsigned int front_pitch;
83 unsigned int back_offset;
84 unsigned int back_pitch;
85
86 unsigned int depth_cpp;
87 unsigned int depth_offset;
88 unsigned int depth_pitch;
89
90 unsigned int texture_offset;
91 unsigned int texture_size;
92
93 drm_map_t *sarea;
94 drm_map_t *fb;
95 drm_map_t *mmio;
96 drm_map_t *status;
97 drm_map_t *warp;
98 drm_map_t *primary;
99 drm_map_t *buffers;
100 drm_map_t *agp_textures;
101 } drm_mga_private_t;
102
103 /* mga_dma.c */
104 extern int mga_dma_init( struct inode *inode, struct file *filp,
105 unsigned int cmd, unsigned long arg );
106 extern int mga_dma_flush( struct inode *inode, struct file *filp,
107 unsigned int cmd, unsigned long arg );
108 extern int mga_dma_reset( struct inode *inode, struct file *filp,
109 unsigned int cmd, unsigned long arg );
110 extern int mga_dma_buffers( struct inode *inode, struct file *filp,
111 unsigned int cmd, unsigned long arg );
112
113 extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
114 extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
115 extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
116 extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
117 extern int mga_do_cleanup_dma( drm_device_t *dev );
118
119 extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
120 extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
121 extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
122
123 extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
124
125 /* mga_state.c */
126 extern int mga_dma_clear( struct inode *inode, struct file *filp,
127 unsigned int cmd, unsigned long arg );
128 extern int mga_dma_swap( struct inode *inode, struct file *filp,
129 unsigned int cmd, unsigned long arg );
130 extern int mga_dma_vertex( struct inode *inode, struct file *filp,
131 unsigned int cmd, unsigned long arg );
132 extern int mga_dma_indices( struct inode *inode, struct file *filp,
133 unsigned int cmd, unsigned long arg );
134 extern int mga_dma_iload( struct inode *inode, struct file *filp,
135 unsigned int cmd, unsigned long arg );
136 extern int mga_dma_blit( struct inode *inode, struct file *filp,
137 unsigned int cmd, unsigned long arg );
138
139 /* mga_warp.c */
140 extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
141 extern int mga_warp_init( drm_mga_private_t *dev_priv );
142
143 #define mga_flush_write_combine() mb()
144
145
146 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
147 #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
148
149 #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
150 #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
151
152 #ifdef __alpha__
153 #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
154 #define MGA_WRITE( reg, val ) do { wmb(); MGA_DEREF( reg ) = val; } while (0)
155 #define MGA_WRITE8( reg, val ) do { wmb(); MGA_DEREF8( reg ) = val; } while (0)
156
_MGA_READ(u32 * addr)157 static inline u32 _MGA_READ(u32 *addr)
158 {
159 mb();
160 return *(volatile u32 *)addr;
161 }
162
163 #else
164 #define MGA_READ( reg ) MGA_DEREF( reg )
165 #define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0)
166 #define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0)
167 #endif
168
169 #define DWGREG0 0x1c00
170 #define DWGREG0_END 0x1dff
171 #define DWGREG1 0x2c00
172 #define DWGREG1_END 0x2dff
173
174 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
175 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
176 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
177 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
178
179
180
181 /* ================================================================
182 * Helper macross...
183 */
184
185 #define MGA_EMIT_STATE( dev_priv, dirty ) \
186 do { \
187 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \
188 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \
189 mga_g400_emit_state( dev_priv ); \
190 } else { \
191 mga_g200_emit_state( dev_priv ); \
192 } \
193 } \
194 } while (0)
195
196 #define LOCK_TEST_WITH_RETURN( dev ) \
197 do { \
198 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
199 dev->lock.pid != current->pid ) { \
200 DRM_ERROR( "%s called without lock held\n", \
201 __FUNCTION__ ); \
202 return -EINVAL; \
203 } \
204 } while (0)
205
206 #define WRAP_TEST_WITH_RETURN( dev_priv ) \
207 do { \
208 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
209 if ( mga_is_idle( dev_priv ) ) { \
210 mga_do_dma_wrap_end( dev_priv ); \
211 } else if ( dev_priv->prim.space < \
212 dev_priv->prim.high_mark ) { \
213 if ( MGA_DMA_DEBUG ) \
214 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
215 return -EBUSY; \
216 } \
217 } \
218 } while (0)
219
220 #define WRAP_WAIT_WITH_RETURN( dev_priv ) \
221 do { \
222 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
223 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \
224 if ( MGA_DMA_DEBUG ) \
225 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
226 return -EBUSY; \
227 } \
228 mga_do_dma_wrap_end( dev_priv ); \
229 } \
230 } while (0)
231
232
233 /* ================================================================
234 * Primary DMA command stream
235 */
236
237 #define MGA_VERBOSE 0
238
239 #define DMA_LOCALS unsigned int write; volatile u8 *prim;
240
241 #define DMA_BLOCK_SIZE (5 * sizeof(u32))
242
243 #define BEGIN_DMA( n ) \
244 do { \
245 if ( MGA_VERBOSE ) { \
246 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
247 (n), __FUNCTION__ ); \
248 DRM_INFO( " space=0x%x req=0x%x\n", \
249 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
250 } \
251 prim = dev_priv->prim.start; \
252 write = dev_priv->prim.tail; \
253 } while (0)
254
255 #define BEGIN_DMA_WRAP() \
256 do { \
257 if ( MGA_VERBOSE ) { \
258 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \
259 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
260 } \
261 prim = dev_priv->prim.start; \
262 write = dev_priv->prim.tail; \
263 } while (0)
264
265 #define ADVANCE_DMA() \
266 do { \
267 dev_priv->prim.tail = write; \
268 if ( MGA_VERBOSE ) { \
269 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
270 write, dev_priv->prim.space ); \
271 } \
272 } while (0)
273
274 #define FLUSH_DMA() \
275 do { \
276 if ( 0 ) { \
277 DRM_INFO( "%s:\n", __FUNCTION__ ); \
278 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
279 dev_priv->prim.tail, \
280 MGA_READ( MGA_PRIMADDRESS ) - \
281 dev_priv->primary->offset ); \
282 } \
283 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \
284 if ( dev_priv->prim.space < \
285 dev_priv->prim.high_mark ) { \
286 mga_do_dma_wrap_start( dev_priv ); \
287 } else { \
288 mga_do_dma_flush( dev_priv ); \
289 } \
290 } \
291 } while (0)
292
293 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
294 */
295 #define DMA_WRITE( offset, val ) \
296 do { \
297 if ( MGA_VERBOSE ) { \
298 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04x\n", \
299 (u32)(val), write + (offset) * sizeof(u32) ); \
300 } \
301 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
302 } while (0)
303
304 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
305 do { \
306 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
307 (DMAREG( reg1 ) << 8) | \
308 (DMAREG( reg2 ) << 16) | \
309 (DMAREG( reg3 ) << 24)) ); \
310 DMA_WRITE( 1, val0 ); \
311 DMA_WRITE( 2, val1 ); \
312 DMA_WRITE( 3, val2 ); \
313 DMA_WRITE( 4, val3 ); \
314 write += DMA_BLOCK_SIZE; \
315 } while (0)
316
317
318 /* Buffer aging via primary DMA stream head pointer.
319 */
320
321 #define SET_AGE( age, h, w ) \
322 do { \
323 (age)->head = h; \
324 (age)->wrap = w; \
325 } while (0)
326
327 #define TEST_AGE( age, h, w ) ( (age)->wrap < w || \
328 ( (age)->wrap == w && \
329 (age)->head < h ) )
330
331 #define AGE_BUFFER( buf_priv ) \
332 do { \
333 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
334 if ( (buf_priv)->dispatched ) { \
335 entry->age.head = (dev_priv->prim.tail + \
336 dev_priv->primary->offset); \
337 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
338 } else { \
339 entry->age.head = 0; \
340 entry->age.wrap = 0; \
341 } \
342 } while (0)
343
344
345 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
346 MGA_DWGENGSTS | \
347 MGA_ENDPRDMASTS)
348 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
349 MGA_ENDPRDMASTS)
350
351 #define MGA_DMA_DEBUG 0
352
353
354
355 /* A reduced set of the mga registers.
356 */
357 #define MGA_CRTC_INDEX 0x1fd4
358
359 #define MGA_ALPHACTRL 0x2c7c
360 #define MGA_AR0 0x1c60
361 #define MGA_AR1 0x1c64
362 #define MGA_AR2 0x1c68
363 #define MGA_AR3 0x1c6c
364 #define MGA_AR4 0x1c70
365 #define MGA_AR5 0x1c74
366 #define MGA_AR6 0x1c78
367
368 #define MGA_CXBNDRY 0x1c80
369 #define MGA_CXLEFT 0x1ca0
370 #define MGA_CXRIGHT 0x1ca4
371
372 #define MGA_DMAPAD 0x1c54
373 #define MGA_DSTORG 0x2cb8
374 #define MGA_DWGCTL 0x1c00
375 # define MGA_OPCOD_MASK (15 << 0)
376 # define MGA_OPCOD_TRAP (4 << 0)
377 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
378 # define MGA_OPCOD_BITBLT (8 << 0)
379 # define MGA_OPCOD_ILOAD (9 << 0)
380 # define MGA_ATYPE_MASK (7 << 4)
381 # define MGA_ATYPE_RPL (0 << 4)
382 # define MGA_ATYPE_RSTR (1 << 4)
383 # define MGA_ATYPE_ZI (3 << 4)
384 # define MGA_ATYPE_BLK (4 << 4)
385 # define MGA_ATYPE_I (7 << 4)
386 # define MGA_LINEAR (1 << 7)
387 # define MGA_ZMODE_MASK (7 << 8)
388 # define MGA_ZMODE_NOZCMP (0 << 8)
389 # define MGA_ZMODE_ZE (2 << 8)
390 # define MGA_ZMODE_ZNE (3 << 8)
391 # define MGA_ZMODE_ZLT (4 << 8)
392 # define MGA_ZMODE_ZLTE (5 << 8)
393 # define MGA_ZMODE_ZGT (6 << 8)
394 # define MGA_ZMODE_ZGTE (7 << 8)
395 # define MGA_SOLID (1 << 11)
396 # define MGA_ARZERO (1 << 12)
397 # define MGA_SGNZERO (1 << 13)
398 # define MGA_SHIFTZERO (1 << 14)
399 # define MGA_BOP_MASK (15 << 16)
400 # define MGA_BOP_ZERO (0 << 16)
401 # define MGA_BOP_DST (10 << 16)
402 # define MGA_BOP_SRC (12 << 16)
403 # define MGA_BOP_ONE (15 << 16)
404 # define MGA_TRANS_SHIFT 20
405 # define MGA_TRANS_MASK (15 << 20)
406 # define MGA_BLTMOD_MASK (15 << 25)
407 # define MGA_BLTMOD_BMONOLEF (0 << 25)
408 # define MGA_BLTMOD_BMONOWF (4 << 25)
409 # define MGA_BLTMOD_PLAN (1 << 25)
410 # define MGA_BLTMOD_BFCOL (2 << 25)
411 # define MGA_BLTMOD_BU32BGR (3 << 25)
412 # define MGA_BLTMOD_BU32RGB (7 << 25)
413 # define MGA_BLTMOD_BU24BGR (11 << 25)
414 # define MGA_BLTMOD_BU24RGB (15 << 25)
415 # define MGA_PATTERN (1 << 29)
416 # define MGA_TRANSC (1 << 30)
417 # define MGA_CLIPDIS (1 << 31)
418 #define MGA_DWGSYNC 0x2c4c
419
420 #define MGA_FCOL 0x1c24
421 #define MGA_FIFOSTATUS 0x1e10
422 #define MGA_FOGCOL 0x1cf4
423 #define MGA_FXBNDRY 0x1c84
424 #define MGA_FXLEFT 0x1ca8
425 #define MGA_FXRIGHT 0x1cac
426
427 #define MGA_ICLEAR 0x1e18
428 # define MGA_SOFTRAPICLR (1 << 0)
429 #define MGA_IEN 0x1e1c
430 # define MGA_SOFTRAPIEN (1 << 0)
431
432 #define MGA_LEN 0x1c5c
433
434 #define MGA_MACCESS 0x1c04
435
436 #define MGA_PITCH 0x1c8c
437 #define MGA_PLNWT 0x1c1c
438 #define MGA_PRIMADDRESS 0x1e58
439 # define MGA_DMA_GENERAL (0 << 0)
440 # define MGA_DMA_BLIT (1 << 0)
441 # define MGA_DMA_VECTOR (2 << 0)
442 # define MGA_DMA_VERTEX (3 << 0)
443 #define MGA_PRIMEND 0x1e5c
444 # define MGA_PRIMNOSTART (1 << 0)
445 # define MGA_PAGPXFER (1 << 1)
446 #define MGA_PRIMPTR 0x1e50
447 # define MGA_PRIMPTREN0 (1 << 0)
448 # define MGA_PRIMPTREN1 (1 << 1)
449
450 #define MGA_RST 0x1e40
451 # define MGA_SOFTRESET (1 << 0)
452 # define MGA_SOFTEXTRST (1 << 1)
453
454 #define MGA_SECADDRESS 0x2c40
455 #define MGA_SECEND 0x2c44
456 #define MGA_SETUPADDRESS 0x2cd0
457 #define MGA_SETUPEND 0x2cd4
458 #define MGA_SGN 0x1c58
459 #define MGA_SOFTRAP 0x2c48
460 #define MGA_SRCORG 0x2cb4
461 # define MGA_SRMMAP_MASK (1 << 0)
462 # define MGA_SRCMAP_FB (0 << 0)
463 # define MGA_SRCMAP_SYSMEM (1 << 0)
464 # define MGA_SRCACC_MASK (1 << 1)
465 # define MGA_SRCACC_PCI (0 << 1)
466 # define MGA_SRCACC_AGP (1 << 1)
467 #define MGA_STATUS 0x1e14
468 # define MGA_SOFTRAPEN (1 << 0)
469 # define MGA_DWGENGSTS (1 << 16)
470 # define MGA_ENDPRDMASTS (1 << 17)
471 #define MGA_STENCIL 0x2cc8
472 #define MGA_STENCILCTL 0x2ccc
473
474 #define MGA_TDUALSTAGE0 0x2cf8
475 #define MGA_TDUALSTAGE1 0x2cfc
476 #define MGA_TEXBORDERCOL 0x2c5c
477 #define MGA_TEXCTL 0x2c30
478 #define MGA_TEXCTL2 0x2c3c
479 # define MGA_DUALTEX (1 << 7)
480 # define MGA_G400_TC2_MAGIC (1 << 15)
481 # define MGA_MAP1_ENABLE (1 << 31)
482 #define MGA_TEXFILTER 0x2c58
483 #define MGA_TEXHEIGHT 0x2c2c
484 #define MGA_TEXORG 0x2c24
485 # define MGA_TEXORGMAP_MASK (1 << 0)
486 # define MGA_TEXORGMAP_FB (0 << 0)
487 # define MGA_TEXORGMAP_SYSMEM (1 << 0)
488 # define MGA_TEXORGACC_MASK (1 << 1)
489 # define MGA_TEXORGACC_PCI (0 << 1)
490 # define MGA_TEXORGACC_AGP (1 << 1)
491 #define MGA_TEXORG1 0x2ca4
492 #define MGA_TEXORG2 0x2ca8
493 #define MGA_TEXORG3 0x2cac
494 #define MGA_TEXORG4 0x2cb0
495 #define MGA_TEXTRANS 0x2c34
496 #define MGA_TEXTRANSHIGH 0x2c38
497 #define MGA_TEXWIDTH 0x2c28
498
499 #define MGA_WACCEPTSEQ 0x1dd4
500 #define MGA_WCODEADDR 0x1e6c
501 #define MGA_WFLAG 0x1dc4
502 #define MGA_WFLAG1 0x1de0
503 #define MGA_WFLAGNB 0x1e64
504 #define MGA_WFLAGNB1 0x1e08
505 #define MGA_WGETMSB 0x1dc8
506 #define MGA_WIADDR 0x1dc0
507 #define MGA_WIADDR2 0x1dd8
508 # define MGA_WMODE_SUSPEND (0 << 0)
509 # define MGA_WMODE_RESUME (1 << 0)
510 # define MGA_WMODE_JUMP (2 << 0)
511 # define MGA_WMODE_START (3 << 0)
512 # define MGA_WAGP_ENABLE (1 << 2)
513 #define MGA_WMISC 0x1e70
514 # define MGA_WUCODECACHE_ENABLE (1 << 0)
515 # define MGA_WMASTER_ENABLE (1 << 1)
516 # define MGA_WCACHEFLUSH_ENABLE (1 << 3)
517 #define MGA_WVRTXSZ 0x1dcc
518
519 #define MGA_YBOT 0x1c9c
520 #define MGA_YDST 0x1c90
521 #define MGA_YDSTLEN 0x1c88
522 #define MGA_YDSTORG 0x1c94
523 #define MGA_YTOP 0x1c98
524
525 #define MGA_ZORG 0x1c0c
526
527 /* This finishes the current batch of commands
528 */
529 #define MGA_EXEC 0x0100
530
531 /* Warp registers
532 */
533 #define MGA_WR0 0x2d00
534 #define MGA_WR1 0x2d04
535 #define MGA_WR2 0x2d08
536 #define MGA_WR3 0x2d0c
537 #define MGA_WR4 0x2d10
538 #define MGA_WR5 0x2d14
539 #define MGA_WR6 0x2d18
540 #define MGA_WR7 0x2d1c
541 #define MGA_WR8 0x2d20
542 #define MGA_WR9 0x2d24
543 #define MGA_WR10 0x2d28
544 #define MGA_WR11 0x2d2c
545 #define MGA_WR12 0x2d30
546 #define MGA_WR13 0x2d34
547 #define MGA_WR14 0x2d38
548 #define MGA_WR15 0x2d3c
549 #define MGA_WR16 0x2d40
550 #define MGA_WR17 0x2d44
551 #define MGA_WR18 0x2d48
552 #define MGA_WR19 0x2d4c
553 #define MGA_WR20 0x2d50
554 #define MGA_WR21 0x2d54
555 #define MGA_WR22 0x2d58
556 #define MGA_WR23 0x2d5c
557 #define MGA_WR24 0x2d60
558 #define MGA_WR25 0x2d64
559 #define MGA_WR26 0x2d68
560 #define MGA_WR27 0x2d6c
561 #define MGA_WR28 0x2d70
562 #define MGA_WR29 0x2d74
563 #define MGA_WR30 0x2d78
564 #define MGA_WR31 0x2d7c
565 #define MGA_WR32 0x2d80
566 #define MGA_WR33 0x2d84
567 #define MGA_WR34 0x2d88
568 #define MGA_WR35 0x2d8c
569 #define MGA_WR36 0x2d90
570 #define MGA_WR37 0x2d94
571 #define MGA_WR38 0x2d98
572 #define MGA_WR39 0x2d9c
573 #define MGA_WR40 0x2da0
574 #define MGA_WR41 0x2da4
575 #define MGA_WR42 0x2da8
576 #define MGA_WR43 0x2dac
577 #define MGA_WR44 0x2db0
578 #define MGA_WR45 0x2db4
579 #define MGA_WR46 0x2db8
580 #define MGA_WR47 0x2dbc
581 #define MGA_WR48 0x2dc0
582 #define MGA_WR49 0x2dc4
583 #define MGA_WR50 0x2dc8
584 #define MGA_WR51 0x2dcc
585 #define MGA_WR52 0x2dd0
586 #define MGA_WR53 0x2dd4
587 #define MGA_WR54 0x2dd8
588 #define MGA_WR55 0x2ddc
589 #define MGA_WR56 0x2de0
590 #define MGA_WR57 0x2de4
591 #define MGA_WR58 0x2de8
592 #define MGA_WR59 0x2dec
593 #define MGA_WR60 0x2df0
594 #define MGA_WR61 0x2df4
595 #define MGA_WR62 0x2df8
596 #define MGA_WR63 0x2dfc
597 # define MGA_G400_WR_MAGIC (1 << 6)
598 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
599
600
601 #define MGA_ILOAD_ALIGN 64
602 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
603
604 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
605 MGA_ATYPE_I | \
606 MGA_ZMODE_NOZCMP | \
607 MGA_ARZERO | \
608 MGA_SGNZERO | \
609 MGA_BOP_SRC | \
610 (15 << MGA_TRANS_SHIFT))
611
612 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
613 MGA_ZMODE_NOZCMP | \
614 MGA_SOLID | \
615 MGA_ARZERO | \
616 MGA_SGNZERO | \
617 MGA_SHIFTZERO | \
618 MGA_BOP_SRC | \
619 (0 << MGA_TRANS_SHIFT) | \
620 MGA_BLTMOD_BMONOLEF | \
621 MGA_TRANSC | \
622 MGA_CLIPDIS)
623
624 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
625 MGA_ATYPE_RPL | \
626 MGA_SGNZERO | \
627 MGA_SHIFTZERO | \
628 MGA_BOP_SRC | \
629 (0 << MGA_TRANS_SHIFT) | \
630 MGA_BLTMOD_BFCOL | \
631 MGA_CLIPDIS)
632
633 /* Simple idle test.
634 */
mga_is_idle(drm_mga_private_t * dev_priv)635 static inline int mga_is_idle( drm_mga_private_t *dev_priv )
636 {
637 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
638 return ( status == MGA_ENDPRDMASTS );
639 }
640
641 #endif
642