1 /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef MDDIHOSTI_H 14 #define MDDIHOSTI_H 15 16 #include "msm_fb.h" 17 #include "mddihost.h" 18 #include <linux/clk.h> 19 20 /* Register offsets in MDDI, applies to both msm_pmdh_base and 21 * (u32)msm_emdh_base. */ 22 #define MDDI_CMD 0x0000 23 #define MDDI_VERSION 0x0004 24 #define MDDI_PRI_PTR 0x0008 25 #define MDDI_BPS 0x0010 26 #define MDDI_SPM 0x0014 27 #define MDDI_INT 0x0018 28 #define MDDI_INTEN 0x001c 29 #define MDDI_REV_PTR 0x0020 30 #define MDDI_REV_SIZE 0x0024 31 #define MDDI_STAT 0x0028 32 #define MDDI_REV_RATE_DIV 0x002c 33 #define MDDI_REV_CRC_ERR 0x0030 34 #define MDDI_TA1_LEN 0x0034 35 #define MDDI_TA2_LEN 0x0038 36 #define MDDI_TEST 0x0040 37 #define MDDI_REV_PKT_CNT 0x0044 38 #define MDDI_DRIVE_HI 0x0048 39 #define MDDI_DRIVE_LO 0x004c 40 #define MDDI_DISP_WAKE 0x0050 41 #define MDDI_REV_ENCAP_SZ 0x0054 42 #define MDDI_RTD_VAL 0x0058 43 #define MDDI_PAD_CTL 0x0068 44 #define MDDI_DRIVER_START_CNT 0x006c 45 #define MDDI_CORE_VER 0x008c 46 #define MDDI_FIFO_ALLOC 0x0090 47 #define MDDI_PAD_IO_CTL 0x00a0 48 #define MDDI_PAD_CAL 0x00a4 49 50 extern u32 mddi_msg_level; 51 52 /* No longer need to write to clear these registers */ 53 #define xxxx_mddi_host_reg_outm(reg, mask, val) \ 54 do { \ 55 if (host_idx == MDDI_HOST_PRIM) \ 56 mddi_host_reg_outm_pmdh(reg, mask, val); \ 57 else \ 58 mddi_host_reg_outm_emdh(reg, mask, val); \ 59 } while (0) 60 61 #define mddi_host_reg_outm(reg, mask, val) \ 62 do { \ 63 unsigned long __addr; \ 64 if (host_idx == MDDI_HOST_PRIM) \ 65 __addr = (u32)msm_pmdh_base + MDDI_##reg; \ 66 else \ 67 __addr = (u32)msm_emdh_base + MDDI_##reg; \ 68 writel((readl(__addr) & ~(mask)) | ((val) & (mask)), __addr); \ 69 } while (0) 70 71 #define xxxx_mddi_host_reg_out(reg, val) \ 72 do { \ 73 if (host_idx == MDDI_HOST_PRIM) \ 74 mddi_host_reg_out_pmdh(reg, val); \ 75 else \ 76 mddi_host_reg_out_emdh(reg, val); \ 77 } while (0) 78 79 #define mddi_host_reg_out(reg, val) \ 80 do { \ 81 if (host_idx == MDDI_HOST_PRIM) \ 82 writel(val, (u32)msm_pmdh_base + MDDI_##reg); \ 83 else \ 84 writel(val, (u32)msm_emdh_base + MDDI_##reg); \ 85 } while (0) 86 87 #define xxxx_mddi_host_reg_in(reg) \ 88 ((host_idx) ? \ 89 mddi_host_reg_in_emdh(reg) : mddi_host_reg_in_pmdh(reg)); 90 91 #define mddi_host_reg_in(reg) \ 92 ((host_idx) ? \ 93 readl((u32)msm_emdh_base + MDDI_##reg) : \ 94 readl((u32)msm_pmdh_base + MDDI_##reg)) \ 95 96 #define xxxx_mddi_host_reg_inm(reg, mask) \ 97 ((host_idx) ? \ 98 mddi_host_reg_inm_emdh(reg, mask) : \ 99 mddi_host_reg_inm_pmdh(reg, mask);) 100 101 #define mddi_host_reg_inm(reg, mask) \ 102 ((host_idx) ? \ 103 readl((u32)msm_emdh_base + MDDI_##reg) & (mask) : \ 104 readl((u32)msm_pmdh_base + MDDI_##reg) & (mask)) \ 105 106 /* Using non-cacheable pmem, so do nothing */ 107 #define mddi_invalidate_cache_lines(addr_start, num_bytes) 108 /* 109 * Using non-cacheable pmem, so do nothing with cache 110 * but, ensure write goes out to memory 111 */ 112 #define mddi_flush_cache_lines(addr_start, num_bytes) \ 113 (void) addr_start; \ 114 (void) num_bytes; \ 115 memory_barrier() 116 117 /* Since this translates to Remote Procedure Calls to check on clock status 118 * just use a local variable to keep track of io_clock */ 119 #define MDDI_HOST_IS_IO_CLOCK_ON mddi_host_io_clock_on 120 #define MDDI_HOST_ENABLE_IO_CLOCK 121 #define MDDI_HOST_DISABLE_IO_CLOCK 122 #define MDDI_HOST_IS_HCLK_ON mddi_host_hclk_on 123 #define MDDI_HOST_ENABLE_HCLK 124 #define MDDI_HOST_DISABLE_HCLK 125 #define FEATURE_MDDI_HOST_IO_CLOCK_CONTROL_DISABLE 126 #define FEATURE_MDDI_HOST_HCLK_CONTROL_DISABLE 127 128 #define TRAMP_MDDI_HOST_ISR TRAMP_MDDI_PRI_ISR 129 #define TRAMP_MDDI_HOST_EXT_ISR TRAMP_MDDI_EXT_ISR 130 #define MDP_LINE_COUNT_BMSK 0x3ff 131 #define MDP_SYNC_STATUS 0x000c 132 #define MDP_LINE_COUNT \ 133 (readl(msm_mdp_base + MDP_SYNC_STATUS) & MDP_LINE_COUNT_BMSK) 134 135 /* MDP sends 256 pixel packets, so lower value hibernates more without 136 * significantly increasing latency of waiting for next subframe */ 137 #define MDDI_HOST_BYTES_PER_SUBFRAME 0x3C00 138 139 #if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40) 140 #define MDDI_HOST_TA2_LEN 0x001a 141 #define MDDI_HOST_REV_RATE_DIV 0x0004 142 #else 143 #define MDDI_HOST_TA2_LEN 0x000c 144 #define MDDI_HOST_REV_RATE_DIV 0x0002 145 #endif 146 147 #define MDDI_MSG_EMERG(msg, ...) \ 148 if (mddi_msg_level > 0) \ 149 printk(KERN_EMERG msg, ## __VA_ARGS__); 150 #define MDDI_MSG_ALERT(msg, ...) \ 151 if (mddi_msg_level > 1) \ 152 printk(KERN_ALERT msg, ## __VA_ARGS__); 153 #define MDDI_MSG_CRIT(msg, ...) \ 154 if (mddi_msg_level > 2) \ 155 printk(KERN_CRIT msg, ## __VA_ARGS__); 156 #define MDDI_MSG_ERR(msg, ...) \ 157 if (mddi_msg_level > 3) \ 158 printk(KERN_ERR msg, ## __VA_ARGS__); 159 #define MDDI_MSG_WARNING(msg, ...) \ 160 if (mddi_msg_level > 4) \ 161 printk(KERN_WARNING msg, ## __VA_ARGS__); 162 #define MDDI_MSG_NOTICE(msg, ...) \ 163 if (mddi_msg_level > 5) \ 164 printk(KERN_NOTICE msg, ## __VA_ARGS__); 165 #define MDDI_MSG_INFO(msg, ...) \ 166 if (mddi_msg_level > 6) \ 167 printk(KERN_INFO msg, ## __VA_ARGS__); 168 #define MDDI_MSG_DEBUG(msg, ...) \ 169 if (mddi_msg_level > 7) \ 170 printk(KERN_DEBUG msg, ## __VA_ARGS__); 171 172 #define GCC_PACKED __attribute__((packed)) 173 typedef struct GCC_PACKED { 174 uint16 packet_length; 175 /* total # of bytes in the packet not including 176 the packet_length field. */ 177 178 uint16 packet_type; 179 /* A Packet Type of 70 identifies the packet as 180 a Client status Packet. */ 181 182 uint16 bClient_ID; 183 /* This field is reserved for future use and shall 184 be set to zero. */ 185 186 } mddi_rev_packet_type; 187 188 typedef struct GCC_PACKED { 189 uint16 packet_length; 190 /* total # of bytes in the packet not including 191 the packet_length field. */ 192 193 uint16 packet_type; 194 /* A Packet Type of 70 identifies the packet as 195 a Client status Packet. */ 196 197 uint16 bClient_ID; 198 /* This field is reserved for future use and shall 199 be set to zero. */ 200 201 uint16 reverse_link_request; 202 /* 16 bit unsigned integer with number of bytes client 203 needs in the * reverse encapsulation message 204 to transmit data. */ 205 206 uint8 crc_error_count; 207 uint8 capability_change; 208 uint16 graphics_busy_flags; 209 210 uint16 parameter_CRC; 211 /* 16-bit CRC of all the bytes in the packet 212 including Packet Length. */ 213 214 } mddi_client_status_type; 215 216 typedef struct GCC_PACKED { 217 uint16 packet_length; 218 /* total # of bytes in the packet not including 219 the packet_length field. */ 220 221 uint16 packet_type; 222 /* A Packet Type of 66 identifies the packet as 223 a Client Capability Packet. */ 224 225 uint16 bClient_ID; 226 /* This field is reserved for future use and 227 shall be set to zero. */ 228 229 uint16 Protocol_Version; 230 uint16 Minimum_Protocol_Version; 231 uint16 Data_Rate_Capability; 232 uint8 Interface_Type_Capability; 233 uint8 Number_of_Alt_Displays; 234 uint16 PostCal_Data_Rate; 235 uint16 Bitmap_Width; 236 uint16 Bitmap_Height; 237 uint16 Display_Window_Width; 238 uint16 Display_Window_Height; 239 uint32 Color_Map_Size; 240 uint16 Color_Map_RGB_Width; 241 uint16 RGB_Capability; 242 uint8 Monochrome_Capability; 243 uint8 Reserved_1; 244 uint16 Y_Cb_Cr_Capability; 245 uint16 Bayer_Capability; 246 uint16 Alpha_Cursor_Image_Planes; 247 uint32 Client_Feature_Capability_Indicators; 248 uint8 Maximum_Video_Frame_Rate_Capability; 249 uint8 Minimum_Video_Frame_Rate_Capability; 250 uint16 Minimum_Sub_frame_Rate; 251 uint16 Audio_Buffer_Depth; 252 uint16 Audio_Channel_Capability; 253 uint16 Audio_Sample_Rate_Capability; 254 uint8 Audio_Sample_Resolution; 255 uint8 Mic_Audio_Sample_Resolution; 256 uint16 Mic_Sample_Rate_Capability; 257 uint8 Keyboard_Data_Format; 258 uint8 pointing_device_data_format; 259 uint16 content_protection_type; 260 uint16 Mfr_Name; 261 uint16 Product_Code; 262 uint16 Reserved_3; 263 uint32 Serial_Number; 264 uint8 Week_of_Manufacture; 265 uint8 Year_of_Manufacture; 266 267 uint16 parameter_CRC; 268 /* 16-bit CRC of all the bytes in the packet including Packet Length. */ 269 270 } mddi_client_capability_type; 271 272 typedef struct GCC_PACKED { 273 uint16 packet_length; 274 /* total # of bytes in the packet not including the packet_length field. */ 275 276 uint16 packet_type; 277 /* A Packet Type of 16 identifies the packet as a Video Stream Packet. */ 278 279 uint16 bClient_ID; 280 /* This field is reserved for future use and shall be set to zero. */ 281 282 uint16 video_data_format_descriptor; 283 /* format of each pixel in the Pixel Data in the present stream in the 284 * present packet. 285 * If bits [15:13] = 000 monochrome 286 * If bits [15:13] = 001 color pixels (palette). 287 * If bits [15:13] = 010 color pixels in raw RGB 288 * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format 289 * If bits [15:13] = 100 Bayer pixels 290 */ 291 292 uint16 pixel_data_attributes; 293 /* interpreted as follows: 294 * Bits [1:0] = 11 pixel data is displayed to both eyes 295 * Bits [1:0] = 10 pixel data is routed to the left eye only. 296 * Bits [1:0] = 01 pixel data is routed to the right eye only. 297 * Bits [1:0] = 00 pixel data is routed to the alternate display. 298 * Bit 2 is 0 Pixel Data is in the standard progressive format. 299 * Bit 2 is 1 Pixel Data is in interlace format. 300 * Bit 3 is 0 Pixel Data is in the standard progressive format. 301 * Bit 3 is 1 Pixel Data is in alternate pixel format. 302 * Bit 4 is 0 Pixel Data is to or from the display frame buffer. 303 * Bit 4 is 1 Pixel Data is to or from the camera. 304 * Bit 5 is 0 pixel data contains the next consecutive row of pixels. 305 * Bit 5 is 1 X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge, 306 * X Start, and Y Start parameters are not defined and 307 * shall be ignored by the client. 308 * Bits [7:6] = 01 Pixel data is written to the offline image buffer. 309 * Bits [7:6] = 00 Pixel data is written to the buffer to refresh display. 310 * Bits [7:6] = 11 Pixel data is written to all image buffers. 311 * Bits [7:6] = 10 Invalid. Reserved for future use. 312 * Bits 8 through 11 alternate display number. 313 * Bits 12 through 14 are reserved for future use and shall be set to zero. 314 * Bit 15 is 1 the row of pixels is the last row of pixels in a frame. 315 */ 316 317 uint16 x_left_edge; 318 uint16 y_top_edge; 319 /* X,Y coordinate of the top left edge of the screen window */ 320 321 uint16 x_right_edge; 322 uint16 y_bottom_edge; 323 /* X,Y coordinate of the bottom right edge of the window being updated. */ 324 325 uint16 x_start; 326 uint16 y_start; 327 /* (X Start, Y Start) is the first pixel in the Pixel Data field below. */ 328 329 uint16 pixel_count; 330 /* number of pixels in the Pixel Data field below. */ 331 332 uint16 parameter_CRC; 333 /* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */ 334 335 uint16 reserved; 336 /* 16-bit variable to make structure align on 4 byte boundary */ 337 338 } mddi_video_stream_packet_type; 339 340 typedef struct GCC_PACKED { 341 uint16 packet_length; 342 /* total # of bytes in the packet not including the packet_length field. */ 343 344 uint16 packet_type; 345 /* A Packet Type of 146 identifies the packet as a Register Access Packet. */ 346 347 uint16 bClient_ID; 348 /* This field is reserved for future use and shall be set to zero. */ 349 350 uint16 read_write_info; 351 /* Bits 13:0 a 14-bit unsigned integer that specifies the number of 352 * 32-bit Register Data List items to be transferred in the 353 * Register Data List field. 354 * Bits[15:14] = 00 Write to register(s); 355 * Bits[15:14] = 10 Read from register(s); 356 * Bits[15:14] = 11 Response to a Read. 357 * Bits[15:14] = 01 this value is reserved for future use. */ 358 359 uint32 register_address; 360 /* the register address that is to be written to or read from. */ 361 362 uint16 parameter_CRC; 363 /* 16-bit CRC of all bytes from the Packet Length to the Register Address. */ 364 365 uint32 register_data_list; 366 /* list of 4-byte register data values for/from client registers */ 367 368 } mddi_register_access_packet_type; 369 370 typedef union GCC_PACKED { 371 mddi_video_stream_packet_type video_pkt; 372 mddi_register_access_packet_type register_pkt; 373 /* add 48 byte pad to ensure 64 byte llist struct, that can be 374 * manipulated easily with cache */ 375 uint32 alignment_pad[12]; /* 48 bytes */ 376 } mddi_packet_header_type; 377 378 typedef struct GCC_PACKED mddi_host_llist_struct { 379 uint16 link_controller_flags; 380 uint16 packet_header_count; 381 uint16 packet_data_count; 382 void *packet_data_pointer; 383 struct mddi_host_llist_struct *next_packet_pointer; 384 uint16 reserved; 385 mddi_packet_header_type packet_header; 386 } mddi_linked_list_type; 387 388 typedef struct { 389 struct completion done_comp; 390 mddi_llist_done_cb_type done_cb; 391 uint16 next_idx; 392 boolean waiting; 393 boolean in_use; 394 } mddi_linked_list_notify_type; 395 396 #define MDDI_LLIST_POOL_SIZE 0x1000 397 #define MDDI_MAX_NUM_LLIST_ITEMS (MDDI_LLIST_POOL_SIZE / \ 398 sizeof(mddi_linked_list_type)) 399 #define UNASSIGNED_INDEX MDDI_MAX_NUM_LLIST_ITEMS 400 #define MDDI_FIRST_DYNAMIC_LLIST_IDX 0 401 402 /* Static llist items can be used for applications that frequently send 403 * the same set of packets using the linked list interface. */ 404 /* Here we configure for 6 static linked list items: 405 * The 1st is used for a the adaptive backlight setting. 406 * and the remaining 5 are used for sending window adjustments for 407 * MDDI clients that need windowing info sent separate from video 408 * packets. */ 409 #define MDDI_NUM_STATIC_ABL_ITEMS 1 410 #define MDDI_NUM_STATIC_WINDOW_ITEMS 5 411 #define MDDI_NUM_STATIC_LLIST_ITEMS (MDDI_NUM_STATIC_ABL_ITEMS + \ 412 MDDI_NUM_STATIC_WINDOW_ITEMS) 413 #define MDDI_NUM_DYNAMIC_LLIST_ITEMS (MDDI_MAX_NUM_LLIST_ITEMS - \ 414 MDDI_NUM_STATIC_LLIST_ITEMS) 415 416 #define MDDI_FIRST_STATIC_LLIST_IDX MDDI_NUM_DYNAMIC_LLIST_ITEMS 417 #define MDDI_FIRST_STATIC_ABL_IDX MDDI_FIRST_STATIC_LLIST_IDX 418 #define MDDI_FIRST_STATIC_WINDOW_IDX (MDDI_FIRST_STATIC_LLIST_IDX + \ 419 MDDI_NUM_STATIC_ABL_ITEMS) 420 421 /* GPIO registers */ 422 #define VSYNC_WAKEUP_REG 0x80 423 #define GPIO_REG 0x81 424 #define GPIO_OUTPUT_REG 0x82 425 #define GPIO_INTERRUPT_REG 0x83 426 #define GPIO_INTERRUPT_ENABLE_REG 0x84 427 #define GPIO_POLARITY_REG 0x85 428 429 /* Interrupt Bits */ 430 #define MDDI_INT_PRI_PTR_READ 0x0001 431 #define MDDI_INT_SEC_PTR_READ 0x0002 432 #define MDDI_INT_REV_DATA_AVAIL 0x0004 433 #define MDDI_INT_DISP_REQ 0x0008 434 #define MDDI_INT_PRI_UNDERFLOW 0x0010 435 #define MDDI_INT_SEC_UNDERFLOW 0x0020 436 #define MDDI_INT_REV_OVERFLOW 0x0040 437 #define MDDI_INT_CRC_ERROR 0x0080 438 #define MDDI_INT_MDDI_IN 0x0100 439 #define MDDI_INT_PRI_OVERWRITE 0x0200 440 #define MDDI_INT_SEC_OVERWRITE 0x0400 441 #define MDDI_INT_REV_OVERWRITE 0x0800 442 #define MDDI_INT_DMA_FAILURE 0x1000 443 #define MDDI_INT_LINK_ACTIVE 0x2000 444 #define MDDI_INT_IN_HIBERNATION 0x4000 445 #define MDDI_INT_PRI_LINK_LIST_DONE 0x8000 446 #define MDDI_INT_SEC_LINK_LIST_DONE 0x10000 447 #define MDDI_INT_NO_CMD_PKTS_PEND 0x20000 448 #define MDDI_INT_RTD_FAILURE 0x40000 449 450 #define MDDI_INT_ERROR_CONDITIONS ( \ 451 MDDI_INT_PRI_UNDERFLOW | MDDI_INT_SEC_UNDERFLOW | \ 452 MDDI_INT_REV_OVERFLOW | MDDI_INT_CRC_ERROR | \ 453 MDDI_INT_PRI_OVERWRITE | MDDI_INT_SEC_OVERWRITE | \ 454 MDDI_INT_RTD_FAILURE | \ 455 MDDI_INT_REV_OVERWRITE | MDDI_INT_DMA_FAILURE) 456 457 #define MDDI_INT_LINK_STATE_CHANGES ( \ 458 MDDI_INT_LINK_ACTIVE | MDDI_INT_IN_HIBERNATION) 459 460 /* Status Bits */ 461 #define MDDI_STAT_LINK_ACTIVE 0x0001 462 #define MDDI_STAT_NEW_REV_PTR 0x0002 463 #define MDDI_STAT_NEW_PRI_PTR 0x0004 464 #define MDDI_STAT_NEW_SEC_PTR 0x0008 465 #define MDDI_STAT_IN_HIBERNATION 0x0010 466 #define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020 467 #define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040 468 #define MDDI_STAT_PENDING_TIMING_PKT 0x0080 469 #define MDDI_STAT_PENDING_REV_ENCAP 0x0100 470 #define MDDI_STAT_PENDING_POWERDOWN 0x0200 471 #define MDDI_STAT_RTD_MEAS_FAIL 0x0800 472 #define MDDI_STAT_CLIENT_WAKEUP_REQ 0x1000 473 474 /* Command Bits */ 475 #define MDDI_CMD_POWERDOWN 0x0100 476 #define MDDI_CMD_POWERUP 0x0200 477 #define MDDI_CMD_HIBERNATE 0x0300 478 #define MDDI_CMD_RESET 0x0400 479 #define MDDI_CMD_DISP_IGNORE 0x0501 480 #define MDDI_CMD_DISP_LISTEN 0x0500 481 #define MDDI_CMD_SEND_REV_ENCAP 0x0600 482 #define MDDI_CMD_GET_CLIENT_CAP 0x0601 483 #define MDDI_CMD_GET_CLIENT_STATUS 0x0602 484 #define MDDI_CMD_SEND_RTD 0x0700 485 #define MDDI_CMD_LINK_ACTIVE 0x0900 486 #define MDDI_CMD_PERIODIC_REV_ENCAP 0x0A00 487 488 extern void mddi_host_init(mddi_host_type host); 489 extern void mddi_host_powerdown(mddi_host_type host); 490 extern uint16 mddi_get_next_free_llist_item(mddi_host_type host, boolean wait); 491 extern uint16 mddi_get_reg_read_llist_item(mddi_host_type host, boolean wait); 492 extern void mddi_queue_forward_packets(uint16 first_llist_idx, 493 uint16 last_llist_idx, 494 boolean wait, 495 mddi_llist_done_cb_type llist_done_cb, 496 mddi_host_type host); 497 498 extern void mddi_host_write_pix_attr_reg(uint32 value); 499 extern void mddi_client_lcd_gpio_poll(uint32 poll_reg_val); 500 extern void mddi_client_lcd_vsync_detected(boolean detected); 501 extern void mddi_host_disable_hibernation(boolean disable); 502 503 extern mddi_linked_list_type *llist_extern[]; 504 extern mddi_linked_list_type *llist_dma_extern[]; 505 extern mddi_linked_list_notify_type *llist_extern_notify[]; 506 extern struct timer_list mddi_host_timer; 507 508 typedef struct { 509 uint16 transmitting_start_idx; 510 uint16 transmitting_end_idx; 511 uint16 waiting_start_idx; 512 uint16 waiting_end_idx; 513 uint16 reg_read_idx; 514 uint16 next_free_idx; 515 boolean reg_read_waiting; 516 } mddi_llist_info_type; 517 518 extern mddi_llist_info_type mddi_llist; 519 520 #define MDDI_GPIO_DEFAULT_POLLING_INTERVAL 200 521 typedef struct { 522 uint32 polling_reg; 523 uint32 polling_val; 524 uint32 polling_interval; 525 boolean polling_enabled; 526 } mddi_gpio_info_type; 527 528 uint32 mddi_get_client_id(void); 529 void mddi_mhctl_remove(mddi_host_type host_idx); 530 void mddi_host_timer_service(unsigned long data); 531 #endif /* MDDIHOSTI_H */ 532