1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT76_CONNAC_MCU_H
5 #define __MT76_CONNAC_MCU_H
6
7 #include "mt76_connac.h"
8
9 #define FW_FEATURE_SET_ENCRYPT BIT(0)
10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1)
11 #define FW_FEATURE_ENCRY_MODE BIT(4)
12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5)
13 #define FW_FEATURE_NON_DL BIT(6)
14
15 #define DL_MODE_ENCRYPT BIT(0)
16 #define DL_MODE_KEY_IDX GENMASK(2, 1)
17 #define DL_MODE_RESET_SEC_IV BIT(3)
18 #define DL_MODE_WORKING_PDA_CR4 BIT(4)
19 #define DL_MODE_VALID_RAM_ENTRY BIT(5)
20 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6)
21 #define DL_MODE_NEED_RSP BIT(31)
22
23 #define FW_START_OVERRIDE BIT(0)
24 #define FW_START_WORKING_PDA_CR4 BIT(2)
25
26 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0)
27 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0)
28 #define PATCH_SEC_TYPE_INFO 0x2
29
30 #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24)
31 #define PATCH_SEC_ENC_TYPE_PLAIN 0x00
32 #define PATCH_SEC_ENC_TYPE_AES 0x01
33 #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02
34 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0)
35 #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0)
36
37 enum {
38 FW_TYPE_DEFAULT = 0,
39 FW_TYPE_CLC = 2,
40 FW_TYPE_MAX_NUM = 255
41 };
42
43 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
44 #define MCU_PKT_ID 0xa0
45
46 struct mt76_connac2_mcu_txd {
47 __le32 txd[8];
48
49 __le16 len;
50 __le16 pq_id;
51
52 u8 cid;
53 u8 pkt_type;
54 u8 set_query; /* FW don't care */
55 u8 seq;
56
57 u8 uc_d2b0_rev;
58 u8 ext_cid;
59 u8 s2d_index;
60 u8 ext_cid_ack;
61
62 u32 rsv[5];
63 } __packed __aligned(4);
64
65 /**
66 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for firmware v3
67 * @txd: hardware descriptor
68 * @len: total length not including txd
69 * @cid: command identifier
70 * @pkt_type: must be 0xa0 (cmd packet by long format)
71 * @frag_n: fragment number
72 * @seq: sequence number
73 * @checksum: 0 mean there is no checksum
74 * @s2d_index: index for command source and destination
75 * Definition | value | note
76 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM
77 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM
78 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA
79 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM
80 *
81 * @option: command option
82 * BIT[0]: UNI_CMD_OPT_BIT_ACK
83 * set to 1 to request a fw reply
84 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
85 * is set, mcu firmware will send response event EID = 0x01
86 * (UNI_EVENT_ID_CMD_RESULT) to the host.
87 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
88 * 0: original command
89 * 1: unified command
90 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
91 * 0: QUERY command
92 * 1: SET command
93 */
94 struct mt76_connac2_mcu_uni_txd {
95 __le32 txd[8];
96
97 /* DW1 */
98 __le16 len;
99 __le16 cid;
100
101 /* DW2 */
102 u8 rsv;
103 u8 pkt_type;
104 u8 frag_n;
105 u8 seq;
106
107 /* DW3 */
108 __le16 checksum;
109 u8 s2d_index;
110 u8 option;
111
112 /* DW4 */
113 u8 rsv1[4];
114 } __packed __aligned(4);
115
116 struct mt76_connac2_mcu_rxd {
117 __le32 rxd[6];
118
119 __le16 len;
120 __le16 pkt_type_id;
121
122 u8 eid;
123 u8 seq;
124 u8 rsv[2];
125
126 u8 ext_eid;
127 u8 rsv1[2];
128 u8 s2d_index;
129 };
130
131 struct mt76_connac2_patch_hdr {
132 char build_date[16];
133 char platform[4];
134 __be32 hw_sw_ver;
135 __be32 patch_ver;
136 __be16 checksum;
137 u16 rsv;
138 struct {
139 __be32 patch_ver;
140 __be32 subsys;
141 __be32 feature;
142 __be32 n_region;
143 __be32 crc;
144 u32 rsv[11];
145 } desc;
146 } __packed;
147
148 struct mt76_connac2_patch_sec {
149 __be32 type;
150 __be32 offs;
151 __be32 size;
152 union {
153 __be32 spec[13];
154 struct {
155 __be32 addr;
156 __be32 len;
157 __be32 sec_key_idx;
158 __be32 align_len;
159 u32 rsv[9];
160 } info;
161 };
162 } __packed;
163
164 struct mt76_connac2_fw_trailer {
165 u8 chip_id;
166 u8 eco_code;
167 u8 n_region;
168 u8 format_ver;
169 u8 format_flag;
170 u8 rsv[2];
171 char fw_ver[10];
172 char build_date[15];
173 __le32 crc;
174 } __packed;
175
176 struct mt76_connac2_fw_region {
177 __le32 decomp_crc;
178 __le32 decomp_len;
179 __le32 decomp_blk_sz;
180 u8 rsv[4];
181 __le32 addr;
182 __le32 len;
183 u8 feature_set;
184 u8 type;
185 u8 rsv1[14];
186 } __packed;
187
188 struct tlv {
189 __le16 tag;
190 __le16 len;
191 } __packed;
192
193 struct bss_info_omac {
194 __le16 tag;
195 __le16 len;
196 u8 hw_bss_idx;
197 u8 omac_idx;
198 u8 band_idx;
199 u8 rsv0;
200 __le32 conn_type;
201 u32 rsv1;
202 } __packed;
203
204 struct bss_info_basic {
205 __le16 tag;
206 __le16 len;
207 __le32 network_type;
208 u8 active;
209 u8 rsv0;
210 __le16 bcn_interval;
211 u8 bssid[ETH_ALEN];
212 u8 wmm_idx;
213 u8 dtim_period;
214 u8 bmc_wcid_lo;
215 u8 cipher;
216 u8 phy_mode;
217 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
218 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
219 u8 bmc_wcid_hi; /* high Byte and version */
220 u8 rsv[2];
221 } __packed;
222
223 struct bss_info_rf_ch {
224 __le16 tag;
225 __le16 len;
226 u8 pri_ch;
227 u8 center_ch0;
228 u8 center_ch1;
229 u8 bw;
230 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
231 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
232 u8 rsv[2];
233 } __packed;
234
235 struct bss_info_ext_bss {
236 __le16 tag;
237 __le16 len;
238 __le32 mbss_tsf_offset; /* in unit of us */
239 u8 rsv[8];
240 } __packed;
241
242 enum {
243 BSS_INFO_OMAC,
244 BSS_INFO_BASIC,
245 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
246 BSS_INFO_PM, /* sta only */
247 BSS_INFO_UAPSD, /* sta only */
248 BSS_INFO_ROAM_DETECT, /* obsoleted */
249 BSS_INFO_LQ_RM, /* obsoleted */
250 BSS_INFO_EXT_BSS,
251 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
252 BSS_INFO_SYNC_MODE, /* obsoleted */
253 BSS_INFO_RA,
254 BSS_INFO_HW_AMSDU,
255 BSS_INFO_BSS_COLOR,
256 BSS_INFO_HE_BASIC,
257 BSS_INFO_PROTECT_INFO,
258 BSS_INFO_OFFLOAD,
259 BSS_INFO_11V_MBSSID,
260 BSS_INFO_MAX_NUM
261 };
262
263 /* sta_rec */
264
265 struct sta_ntlv_hdr {
266 u8 rsv[2];
267 __le16 tlv_num;
268 } __packed;
269
270 struct sta_req_hdr {
271 u8 bss_idx;
272 u8 wlan_idx_lo;
273 __le16 tlv_num;
274 u8 is_tlv_append;
275 u8 muar_idx;
276 u8 wlan_idx_hi;
277 u8 rsv;
278 } __packed;
279
280 struct sta_rec_basic {
281 __le16 tag;
282 __le16 len;
283 __le32 conn_type;
284 u8 conn_state;
285 u8 qos;
286 __le16 aid;
287 u8 peer_addr[ETH_ALEN];
288 #define EXTRA_INFO_VER BIT(0)
289 #define EXTRA_INFO_NEW BIT(1)
290 __le16 extra_info;
291 } __packed;
292
293 struct sta_rec_ht {
294 __le16 tag;
295 __le16 len;
296 __le16 ht_cap;
297 u16 rsv;
298 } __packed;
299
300 struct sta_rec_vht {
301 __le16 tag;
302 __le16 len;
303 __le32 vht_cap;
304 __le16 vht_rx_mcs_map;
305 __le16 vht_tx_mcs_map;
306 /* mt7915 - mt7921 */
307 u8 rts_bw_sig;
308 u8 rsv[3];
309 } __packed;
310
311 struct sta_rec_uapsd {
312 __le16 tag;
313 __le16 len;
314 u8 dac_map;
315 u8 tac_map;
316 u8 max_sp;
317 u8 rsv0;
318 __le16 listen_interval;
319 u8 rsv1[2];
320 } __packed;
321
322 struct sta_rec_ba {
323 __le16 tag;
324 __le16 len;
325 u8 tid;
326 u8 ba_type;
327 u8 amsdu;
328 u8 ba_en;
329 __le16 ssn;
330 __le16 winsize;
331 } __packed;
332
333 struct sta_rec_he {
334 __le16 tag;
335 __le16 len;
336
337 __le32 he_cap;
338
339 u8 t_frame_dur;
340 u8 max_ampdu_exp;
341 u8 bw_set;
342 u8 device_class;
343 u8 dcm_tx_mode;
344 u8 dcm_tx_max_nss;
345 u8 dcm_rx_mode;
346 u8 dcm_rx_max_nss;
347 u8 dcm_max_ru;
348 u8 punc_pream_rx;
349 u8 pkt_ext;
350 u8 rsv1;
351
352 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
353
354 u8 rsv2[2];
355 } __packed;
356
357 struct sta_rec_amsdu {
358 __le16 tag;
359 __le16 len;
360 u8 max_amsdu_num;
361 u8 max_mpdu_size;
362 u8 amsdu_en;
363 u8 rsv;
364 } __packed;
365
366 struct sta_rec_state {
367 __le16 tag;
368 __le16 len;
369 __le32 flags;
370 u8 state;
371 u8 vht_opmode;
372 u8 action;
373 u8 rsv[1];
374 } __packed;
375
376 #define RA_LEGACY_OFDM GENMASK(13, 6)
377 #define RA_LEGACY_CCK GENMASK(3, 0)
378 #define HT_MCS_MASK_NUM 10
379 struct sta_rec_ra_info {
380 __le16 tag;
381 __le16 len;
382 __le16 legacy;
383 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
384 } __packed;
385
386 struct sta_rec_phy {
387 __le16 tag;
388 __le16 len;
389 __le16 basic_rate;
390 u8 phy_type;
391 u8 ampdu;
392 u8 rts_policy;
393 u8 rcpi;
394 u8 rsv[2];
395 } __packed;
396
397 struct sta_rec_he_6g_capa {
398 __le16 tag;
399 __le16 len;
400 __le16 capa;
401 u8 rsv[2];
402 } __packed;
403
404 struct sec_key {
405 u8 cipher_id;
406 u8 cipher_len;
407 u8 key_id;
408 u8 key_len;
409 u8 key[32];
410 } __packed;
411
412 struct sta_rec_sec {
413 __le16 tag;
414 __le16 len;
415 u8 add;
416 u8 n_cipher;
417 u8 rsv[2];
418
419 struct sec_key key[2];
420 } __packed;
421
422 struct sta_rec_bf {
423 __le16 tag;
424 __le16 len;
425
426 __le16 pfmu; /* 0xffff: no access right for PFMU */
427 bool su_mu; /* 0: SU, 1: MU */
428 u8 bf_cap; /* 0: iBF, 1: eBF */
429 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
430 u8 ndpa_rate;
431 u8 ndp_rate;
432 u8 rept_poll_rate;
433 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
434 u8 ncol;
435 u8 nrow;
436 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
437
438 u8 mem_total;
439 u8 mem_20m;
440 struct {
441 u8 row;
442 u8 col: 6, row_msb: 2;
443 } mem[4];
444
445 __le16 smart_ant;
446 u8 se_idx;
447 u8 auto_sounding; /* b7: low traffic indicator
448 * b6: Stop sounding for this entry
449 * b5 ~ b0: postpone sounding
450 */
451 u8 ibf_timeout;
452 u8 ibf_dbw;
453 u8 ibf_ncol;
454 u8 ibf_nrow;
455 u8 nrow_bw160;
456 u8 ncol_bw160;
457 u8 ru_start_idx;
458 u8 ru_end_idx;
459
460 bool trigger_su;
461 bool trigger_mu;
462 bool ng16_su;
463 bool ng16_mu;
464 bool codebook42_su;
465 bool codebook75_mu;
466
467 u8 he_ltf;
468 u8 rsv[3];
469 } __packed;
470
471 struct sta_rec_bfee {
472 __le16 tag;
473 __le16 len;
474 bool fb_identity_matrix; /* 1: feedback identity matrix */
475 bool ignore_feedback; /* 1: ignore */
476 u8 rsv[2];
477 } __packed;
478
479 struct sta_rec_muru {
480 __le16 tag;
481 __le16 len;
482
483 struct {
484 bool ofdma_dl_en;
485 bool ofdma_ul_en;
486 bool mimo_dl_en;
487 bool mimo_ul_en;
488 u8 rsv[4];
489 } cfg;
490
491 struct {
492 u8 punc_pream_rx;
493 bool he_20m_in_40m_2g;
494 bool he_20m_in_160m;
495 bool he_80m_in_160m;
496 bool lt16_sigb;
497 bool rx_su_comp_sigb;
498 bool rx_su_non_comp_sigb;
499 u8 rsv;
500 } ofdma_dl;
501
502 struct {
503 u8 t_frame_dur;
504 u8 mu_cascading;
505 u8 uo_ra;
506 u8 he_2x996_tone;
507 u8 rx_t_frame_11ac;
508 u8 rsv[3];
509 } ofdma_ul;
510
511 struct {
512 bool vht_mu_bfee;
513 bool partial_bw_dl_mimo;
514 u8 rsv[2];
515 } mimo_dl;
516
517 struct {
518 bool full_ul_mimo;
519 bool partial_ul_mimo;
520 u8 rsv[2];
521 } mimo_ul;
522 } __packed;
523
524 struct sta_phy {
525 u8 type;
526 u8 flag;
527 u8 stbc;
528 u8 sgi;
529 u8 bw;
530 u8 ldpc;
531 u8 mcs;
532 u8 nss;
533 u8 he_ltf;
534 };
535
536 struct sta_rec_ra {
537 __le16 tag;
538 __le16 len;
539
540 u8 valid;
541 u8 auto_rate;
542 u8 phy_mode;
543 u8 channel;
544 u8 bw;
545 u8 disable_cck;
546 u8 ht_mcs32;
547 u8 ht_gf;
548 u8 ht_mcs[4];
549 u8 mmps_mode;
550 u8 gband_256;
551 u8 af;
552 u8 auth_wapi_mode;
553 u8 rate_len;
554
555 u8 supp_mode;
556 u8 supp_cck_rate;
557 u8 supp_ofdm_rate;
558 __le32 supp_ht_mcs;
559 __le16 supp_vht_mcs[4];
560
561 u8 op_mode;
562 u8 op_vht_chan_width;
563 u8 op_vht_rx_nss;
564 u8 op_vht_rx_nss_type;
565
566 __le32 sta_cap;
567
568 struct sta_phy phy;
569 } __packed;
570
571 struct sta_rec_ra_fixed {
572 __le16 tag;
573 __le16 len;
574
575 __le32 field;
576 u8 op_mode;
577 u8 op_vht_chan_width;
578 u8 op_vht_rx_nss;
579 u8 op_vht_rx_nss_type;
580
581 struct sta_phy phy;
582
583 u8 spe_en;
584 u8 short_preamble;
585 u8 is_5g;
586 u8 mmps_mode;
587 } __packed;
588
589 /* wtbl_rec */
590
591 struct wtbl_req_hdr {
592 u8 wlan_idx_lo;
593 u8 operation;
594 __le16 tlv_num;
595 u8 wlan_idx_hi;
596 u8 rsv[3];
597 } __packed;
598
599 struct wtbl_generic {
600 __le16 tag;
601 __le16 len;
602 u8 peer_addr[ETH_ALEN];
603 u8 muar_idx;
604 u8 skip_tx;
605 u8 cf_ack;
606 u8 qos;
607 u8 mesh;
608 u8 adm;
609 __le16 partial_aid;
610 u8 baf_en;
611 u8 aad_om;
612 } __packed;
613
614 struct wtbl_rx {
615 __le16 tag;
616 __le16 len;
617 u8 rcid;
618 u8 rca1;
619 u8 rca2;
620 u8 rv;
621 u8 rsv[4];
622 } __packed;
623
624 struct wtbl_ht {
625 __le16 tag;
626 __le16 len;
627 u8 ht;
628 u8 ldpc;
629 u8 af;
630 u8 mm;
631 u8 rsv[4];
632 } __packed;
633
634 struct wtbl_vht {
635 __le16 tag;
636 __le16 len;
637 u8 ldpc;
638 u8 dyn_bw;
639 u8 vht;
640 u8 txop_ps;
641 u8 rsv[4];
642 } __packed;
643
644 struct wtbl_tx_ps {
645 __le16 tag;
646 __le16 len;
647 u8 txps;
648 u8 rsv[3];
649 } __packed;
650
651 struct wtbl_hdr_trans {
652 __le16 tag;
653 __le16 len;
654 u8 to_ds;
655 u8 from_ds;
656 u8 no_rx_trans;
657 u8 rsv;
658 } __packed;
659
660 struct wtbl_ba {
661 __le16 tag;
662 __le16 len;
663 /* common */
664 u8 tid;
665 u8 ba_type;
666 u8 rsv0[2];
667 /* originator only */
668 __le16 sn;
669 u8 ba_en;
670 u8 ba_winsize_idx;
671 /* originator & recipient */
672 __le16 ba_winsize;
673 /* recipient only */
674 u8 peer_addr[ETH_ALEN];
675 u8 rst_ba_tid;
676 u8 rst_ba_sel;
677 u8 rst_ba_sb;
678 u8 band_idx;
679 u8 rsv1[4];
680 } __packed;
681
682 struct wtbl_smps {
683 __le16 tag;
684 __le16 len;
685 u8 smps;
686 u8 rsv[3];
687 } __packed;
688
689 /* mt7615 only */
690
691 struct wtbl_bf {
692 __le16 tag;
693 __le16 len;
694 u8 ibf;
695 u8 ebf;
696 u8 ibf_vht;
697 u8 ebf_vht;
698 u8 gid;
699 u8 pfmu_idx;
700 u8 rsv[2];
701 } __packed;
702
703 struct wtbl_pn {
704 __le16 tag;
705 __le16 len;
706 u8 pn[6];
707 u8 rsv[2];
708 } __packed;
709
710 struct wtbl_spe {
711 __le16 tag;
712 __le16 len;
713 u8 spe_idx;
714 u8 rsv[3];
715 } __packed;
716
717 struct wtbl_raw {
718 __le16 tag;
719 __le16 len;
720 u8 wtbl_idx;
721 u8 dw;
722 u8 rsv[2];
723 __le32 msk;
724 __le32 val;
725 } __packed;
726
727 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
728 sizeof(struct wtbl_generic) + \
729 sizeof(struct wtbl_rx) + \
730 sizeof(struct wtbl_ht) + \
731 sizeof(struct wtbl_vht) + \
732 sizeof(struct wtbl_tx_ps) + \
733 sizeof(struct wtbl_hdr_trans) +\
734 sizeof(struct wtbl_ba) + \
735 sizeof(struct wtbl_bf) + \
736 sizeof(struct wtbl_smps) + \
737 sizeof(struct wtbl_pn) + \
738 sizeof(struct wtbl_spe))
739
740 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
741 sizeof(struct sta_rec_basic) + \
742 sizeof(struct sta_rec_bf) + \
743 sizeof(struct sta_rec_ht) + \
744 sizeof(struct sta_rec_he) + \
745 sizeof(struct sta_rec_ba) + \
746 sizeof(struct sta_rec_vht) + \
747 sizeof(struct sta_rec_uapsd) + \
748 sizeof(struct sta_rec_amsdu) + \
749 sizeof(struct sta_rec_muru) + \
750 sizeof(struct sta_rec_bfee) + \
751 sizeof(struct sta_rec_ra) + \
752 sizeof(struct sta_rec_sec) + \
753 sizeof(struct sta_rec_ra_fixed) + \
754 sizeof(struct sta_rec_he_6g_capa) + \
755 sizeof(struct tlv) + \
756 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
757
758 enum {
759 STA_REC_BASIC,
760 STA_REC_RA,
761 STA_REC_RA_CMM_INFO,
762 STA_REC_RA_UPDATE,
763 STA_REC_BF,
764 STA_REC_AMSDU,
765 STA_REC_BA,
766 STA_REC_STATE,
767 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
768 STA_REC_HT,
769 STA_REC_VHT,
770 STA_REC_APPS,
771 STA_REC_KEY,
772 STA_REC_WTBL,
773 STA_REC_HE,
774 STA_REC_HW_AMSDU,
775 STA_REC_WTBL_AADOM,
776 STA_REC_KEY_V2,
777 STA_REC_MURU,
778 STA_REC_MUEDCA,
779 STA_REC_BFEE,
780 STA_REC_PHY = 0x15,
781 STA_REC_HE_6G = 0x17,
782 STA_REC_MAX_NUM
783 };
784
785 enum {
786 WTBL_GENERIC,
787 WTBL_RX,
788 WTBL_HT,
789 WTBL_VHT,
790 WTBL_PEER_PS, /* not used */
791 WTBL_TX_PS,
792 WTBL_HDR_TRANS,
793 WTBL_SEC_KEY,
794 WTBL_BA,
795 WTBL_RDG, /* obsoleted */
796 WTBL_PROTECT, /* not used */
797 WTBL_CLEAR, /* not used */
798 WTBL_BF,
799 WTBL_SMPS,
800 WTBL_RAW_DATA, /* debug only */
801 WTBL_PN,
802 WTBL_SPE,
803 WTBL_MAX_NUM
804 };
805
806 #define STA_TYPE_STA BIT(0)
807 #define STA_TYPE_AP BIT(1)
808 #define STA_TYPE_ADHOC BIT(2)
809 #define STA_TYPE_WDS BIT(4)
810 #define STA_TYPE_BC BIT(5)
811
812 #define NETWORK_INFRA BIT(16)
813 #define NETWORK_P2P BIT(17)
814 #define NETWORK_IBSS BIT(18)
815 #define NETWORK_WDS BIT(21)
816
817 #define SCAN_FUNC_RANDOM_MAC BIT(0)
818 #define SCAN_FUNC_SPLIT_SCAN BIT(5)
819
820 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
821 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
822 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
823 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
824 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
825 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
826 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
827
828 #define CONN_STATE_DISCONNECT 0
829 #define CONN_STATE_CONNECT 1
830 #define CONN_STATE_PORT_SECURE 2
831
832 /* HE MAC */
833 #define STA_REC_HE_CAP_HTC BIT(0)
834 #define STA_REC_HE_CAP_BQR BIT(1)
835 #define STA_REC_HE_CAP_BSR BIT(2)
836 #define STA_REC_HE_CAP_OM BIT(3)
837 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
838 /* HE PHY */
839 #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
840 #define STA_REC_HE_CAP_LDPC BIT(6)
841 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
842 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
843 /* STBC */
844 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
845 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
846 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
847 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
848 /* GI */
849 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
850 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
851 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
852 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
853 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
854 /* 242 TONE */
855 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
856 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
857 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
858
859 #define PHY_MODE_A BIT(0)
860 #define PHY_MODE_B BIT(1)
861 #define PHY_MODE_G BIT(2)
862 #define PHY_MODE_GN BIT(3)
863 #define PHY_MODE_AN BIT(4)
864 #define PHY_MODE_AC BIT(5)
865 #define PHY_MODE_AX_24G BIT(6)
866 #define PHY_MODE_AX_5G BIT(7)
867
868 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */
869
870 #define MODE_CCK BIT(0)
871 #define MODE_OFDM BIT(1)
872 #define MODE_HT BIT(2)
873 #define MODE_VHT BIT(3)
874 #define MODE_HE BIT(4)
875
876 #define STA_CAP_WMM BIT(0)
877 #define STA_CAP_SGI_20 BIT(4)
878 #define STA_CAP_SGI_40 BIT(5)
879 #define STA_CAP_TX_STBC BIT(6)
880 #define STA_CAP_RX_STBC BIT(7)
881 #define STA_CAP_VHT_SGI_80 BIT(16)
882 #define STA_CAP_VHT_SGI_160 BIT(17)
883 #define STA_CAP_VHT_TX_STBC BIT(18)
884 #define STA_CAP_VHT_RX_STBC BIT(19)
885 #define STA_CAP_VHT_LDPC BIT(23)
886 #define STA_CAP_LDPC BIT(24)
887 #define STA_CAP_HT BIT(26)
888 #define STA_CAP_VHT BIT(27)
889 #define STA_CAP_HE BIT(28)
890
891 enum {
892 PHY_TYPE_HR_DSSS_INDEX = 0,
893 PHY_TYPE_ERP_INDEX,
894 PHY_TYPE_ERP_P2P_INDEX,
895 PHY_TYPE_OFDM_INDEX,
896 PHY_TYPE_HT_INDEX,
897 PHY_TYPE_VHT_INDEX,
898 PHY_TYPE_HE_INDEX,
899 PHY_TYPE_INDEX_NUM
900 };
901
902 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
903 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
904 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
905 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
906 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
907 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
908
909 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
910 #define MT_WTBL_RATE_MCS GENMASK(5, 0)
911 #define MT_WTBL_RATE_NSS GENMASK(12, 10)
912 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
913 #define MT_WTBL_RATE_GI GENMASK(3, 0)
914
915 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
916 #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
917 #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
918 #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
919 #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
920 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
921 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
922 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
923 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
924
925 enum {
926 WTBL_RESET_AND_SET = 1,
927 WTBL_SET,
928 WTBL_QUERY,
929 WTBL_RESET_ALL
930 };
931
932 enum {
933 MT_BA_TYPE_INVALID,
934 MT_BA_TYPE_ORIGINATOR,
935 MT_BA_TYPE_RECIPIENT
936 };
937
938 enum {
939 RST_BA_MAC_TID_MATCH,
940 RST_BA_MAC_MATCH,
941 RST_BA_NO_MATCH
942 };
943
944 enum {
945 DEV_INFO_ACTIVE,
946 DEV_INFO_MAX_NUM
947 };
948
949 /* event table */
950 enum {
951 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
952 MCU_EVENT_FW_START = 0x01,
953 MCU_EVENT_GENERIC = 0x01,
954 MCU_EVENT_ACCESS_REG = 0x02,
955 MCU_EVENT_MT_PATCH_SEM = 0x04,
956 MCU_EVENT_REG_ACCESS = 0x05,
957 MCU_EVENT_LP_INFO = 0x07,
958 MCU_EVENT_SCAN_DONE = 0x0d,
959 MCU_EVENT_TX_DONE = 0x0f,
960 MCU_EVENT_ROC = 0x10,
961 MCU_EVENT_BSS_ABSENCE = 0x11,
962 MCU_EVENT_BSS_BEACON_LOSS = 0x13,
963 MCU_EVENT_CH_PRIVILEGE = 0x18,
964 MCU_EVENT_SCHED_SCAN_DONE = 0x23,
965 MCU_EVENT_DBG_MSG = 0x27,
966 MCU_EVENT_TXPWR = 0xd0,
967 MCU_EVENT_EXT = 0xed,
968 MCU_EVENT_RESTART_DL = 0xef,
969 MCU_EVENT_COREDUMP = 0xf0,
970 };
971
972 /* ext event table */
973 enum {
974 MCU_EXT_EVENT_PS_SYNC = 0x5,
975 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
976 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
977 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
978 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
979 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
980 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
981 MCU_EXT_EVENT_MURU_CTRL = 0x9f,
982 };
983
984 enum {
985 MCU_Q_QUERY,
986 MCU_Q_SET,
987 MCU_Q_RESERVED,
988 MCU_Q_NA
989 };
990
991 enum {
992 MCU_S2D_H2N,
993 MCU_S2D_C2N,
994 MCU_S2D_H2C,
995 MCU_S2D_H2CN
996 };
997
998 enum {
999 PATCH_NOT_DL_SEM_FAIL,
1000 PATCH_IS_DL,
1001 PATCH_NOT_DL_SEM_SUCCESS,
1002 PATCH_REL_SEM_SUCCESS
1003 };
1004
1005 enum {
1006 FW_STATE_INITIAL,
1007 FW_STATE_FW_DOWNLOAD,
1008 FW_STATE_NORMAL_OPERATION,
1009 FW_STATE_NORMAL_TRX,
1010 FW_STATE_RDY = 7
1011 };
1012
1013 enum {
1014 CH_SWITCH_NORMAL = 0,
1015 CH_SWITCH_SCAN = 3,
1016 CH_SWITCH_MCC = 4,
1017 CH_SWITCH_DFS = 5,
1018 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1019 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1020 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1021 CH_SWITCH_SCAN_BYPASS_DPD = 9
1022 };
1023
1024 enum {
1025 THERMAL_SENSOR_TEMP_QUERY,
1026 THERMAL_SENSOR_MANUAL_CTRL,
1027 THERMAL_SENSOR_INFO_QUERY,
1028 THERMAL_SENSOR_TASK_CTRL,
1029 };
1030
1031 enum mcu_cipher_type {
1032 MCU_CIPHER_NONE = 0,
1033 MCU_CIPHER_WEP40,
1034 MCU_CIPHER_WEP104,
1035 MCU_CIPHER_WEP128,
1036 MCU_CIPHER_TKIP,
1037 MCU_CIPHER_AES_CCMP,
1038 MCU_CIPHER_CCMP_256,
1039 MCU_CIPHER_GCMP,
1040 MCU_CIPHER_GCMP_256,
1041 MCU_CIPHER_WAPI,
1042 MCU_CIPHER_BIP_CMAC_128,
1043 };
1044
1045 enum {
1046 EE_MODE_EFUSE,
1047 EE_MODE_BUFFER,
1048 };
1049
1050 enum {
1051 EE_FORMAT_BIN,
1052 EE_FORMAT_WHOLE,
1053 EE_FORMAT_MULTIPLE,
1054 };
1055
1056 enum {
1057 MCU_PHY_STATE_TX_RATE,
1058 MCU_PHY_STATE_RX_RATE,
1059 MCU_PHY_STATE_RSSI,
1060 MCU_PHY_STATE_CONTENTION_RX_RATE,
1061 MCU_PHY_STATE_OFDMLQ_CNINFO,
1062 };
1063
1064 #define MCU_CMD_ACK BIT(0)
1065 #define MCU_CMD_UNI BIT(1)
1066 #define MCU_CMD_QUERY BIT(2)
1067
1068 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
1069 MCU_CMD_QUERY)
1070
1071 #define __MCU_CMD_FIELD_ID GENMASK(7, 0)
1072 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)
1073 #define __MCU_CMD_FIELD_QUERY BIT(16)
1074 #define __MCU_CMD_FIELD_UNI BIT(17)
1075 #define __MCU_CMD_FIELD_CE BIT(18)
1076 #define __MCU_CMD_FIELD_WA BIT(19)
1077
1078 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \
1079 MCU_CMD_##_t)
1080 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \
1081 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1082 MCU_EXT_CMD_##_t))
1083 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1084 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \
1085 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1086 MCU_UNI_CMD_##_t))
1087 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \
1088 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1089 MCU_CE_CMD_##_t))
1090 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1091
1092 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
1093 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
1094 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \
1095 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1096 MCU_WA_PARAM_CMD_##_t))
1097
1098 enum {
1099 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
1100 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
1101 MCU_EXT_CMD_RF_TEST = 0x04,
1102 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
1103 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
1104 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
1105 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
1106 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
1107 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
1108 MCU_EXT_CMD_THERMAL_PROT = 0x23,
1109 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
1110 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
1111 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
1112 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
1113 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
1114 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
1115 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
1116 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
1117 MCU_EXT_CMD_ATE_CTRL = 0x3d,
1118 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
1119 MCU_EXT_CMD_DBDC_CTRL = 0x45,
1120 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
1121 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
1122 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
1123 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
1124 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
1125 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
1126 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
1127 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
1128 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
1129 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
1130 MCU_EXT_CMD_TXDPD_CAL = 0x60,
1131 MCU_EXT_CMD_CAL_CACHE = 0x67,
1132 MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
1133 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
1134 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
1135 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
1136 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
1137 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
1138 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
1139 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
1140 MCU_EXT_CMD_MURU_CTRL = 0x9f,
1141 MCU_EXT_CMD_SET_SPR = 0xa8,
1142 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
1143 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
1144 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
1145 };
1146
1147 enum {
1148 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
1149 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
1150 MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
1151 MCU_UNI_CMD_SUSPEND = 0x05,
1152 MCU_UNI_CMD_OFFLOAD = 0x06,
1153 MCU_UNI_CMD_HIF_CTRL = 0x07,
1154 MCU_UNI_CMD_SNIFFER = 0x24,
1155 };
1156
1157 enum {
1158 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1159 MCU_CMD_FW_START_REQ = 0x02,
1160 MCU_CMD_INIT_ACCESS_REG = 0x3,
1161 MCU_CMD_NIC_POWER_CTRL = 0x4,
1162 MCU_CMD_PATCH_START_REQ = 0x05,
1163 MCU_CMD_PATCH_FINISH_REQ = 0x07,
1164 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1165 MCU_CMD_WA_PARAM = 0xc4,
1166 MCU_CMD_EXT_CID = 0xed,
1167 MCU_CMD_FW_SCATTER = 0xee,
1168 MCU_CMD_RESTART_DL_REQ = 0xef,
1169 };
1170
1171 /* offload mcu commands */
1172 enum {
1173 MCU_CE_CMD_TEST_CTRL = 0x01,
1174 MCU_CE_CMD_START_HW_SCAN = 0x03,
1175 MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1176 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1177 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1178 MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1179 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1180 MCU_CE_CMD_SET_ROC = 0x1c,
1181 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1182 MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1183 MCU_CE_CMD_SET_CLC = 0x5c,
1184 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1185 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1186 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1187 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1188 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1189 MCU_CE_CMD_REG_WRITE = 0xc0,
1190 MCU_CE_CMD_REG_READ = 0xc0,
1191 MCU_CE_CMD_CHIP_CONFIG = 0xca,
1192 MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1193 MCU_CE_CMD_GET_WTBL = 0xcd,
1194 MCU_CE_CMD_GET_TXPWR = 0xd0,
1195 };
1196
1197 enum {
1198 PATCH_SEM_RELEASE,
1199 PATCH_SEM_GET
1200 };
1201
1202 enum {
1203 UNI_BSS_INFO_BASIC = 0,
1204 UNI_BSS_INFO_RLM = 2,
1205 UNI_BSS_INFO_BSS_COLOR = 4,
1206 UNI_BSS_INFO_HE_BASIC = 5,
1207 UNI_BSS_INFO_BCN_CONTENT = 7,
1208 UNI_BSS_INFO_QBSS = 15,
1209 UNI_BSS_INFO_UAPSD = 19,
1210 UNI_BSS_INFO_PS = 21,
1211 UNI_BSS_INFO_BCNFT = 22,
1212 };
1213
1214 enum {
1215 UNI_OFFLOAD_OFFLOAD_ARP,
1216 UNI_OFFLOAD_OFFLOAD_ND,
1217 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1218 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1219 };
1220
1221 enum {
1222 MT_NIC_CAP_TX_RESOURCE,
1223 MT_NIC_CAP_TX_EFUSE_ADDR,
1224 MT_NIC_CAP_COEX,
1225 MT_NIC_CAP_SINGLE_SKU,
1226 MT_NIC_CAP_CSUM_OFFLOAD,
1227 MT_NIC_CAP_HW_VER,
1228 MT_NIC_CAP_SW_VER,
1229 MT_NIC_CAP_MAC_ADDR,
1230 MT_NIC_CAP_PHY,
1231 MT_NIC_CAP_MAC,
1232 MT_NIC_CAP_FRAME_BUF,
1233 MT_NIC_CAP_BEAM_FORM,
1234 MT_NIC_CAP_LOCATION,
1235 MT_NIC_CAP_MUMIMO,
1236 MT_NIC_CAP_BUFFER_MODE_INFO,
1237 MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1238 MT_NIC_CAP_ANTSWP = 0x16,
1239 MT_NIC_CAP_WFDMA_REALLOC,
1240 MT_NIC_CAP_6G,
1241 };
1242
1243 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
1244 #define UNI_WOW_DETECT_TYPE_ANY BIT(1)
1245 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2)
1246 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3)
1247 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4)
1248 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5)
1249 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6)
1250
1251 enum {
1252 UNI_SUSPEND_MODE_SETTING,
1253 UNI_SUSPEND_WOW_CTRL,
1254 UNI_SUSPEND_WOW_GPIO_PARAM,
1255 UNI_SUSPEND_WOW_WAKEUP_PORT,
1256 UNI_SUSPEND_WOW_PATTERN,
1257 };
1258
1259 enum {
1260 WOW_USB = 1,
1261 WOW_PCIE = 2,
1262 WOW_GPIO = 3,
1263 };
1264
1265 struct mt76_connac_bss_basic_tlv {
1266 __le16 tag;
1267 __le16 len;
1268 u8 active;
1269 u8 omac_idx;
1270 u8 hw_bss_idx;
1271 u8 band_idx;
1272 __le32 conn_type;
1273 u8 conn_state;
1274 u8 wmm_idx;
1275 u8 bssid[ETH_ALEN];
1276 __le16 bmc_tx_wlan_idx;
1277 __le16 bcn_interval;
1278 u8 dtim_period;
1279 u8 phymode; /* bit(0): A
1280 * bit(1): B
1281 * bit(2): G
1282 * bit(3): GN
1283 * bit(4): AN
1284 * bit(5): AC
1285 * bit(6): AX2
1286 * bit(7): AX5
1287 * bit(8): AX6
1288 */
1289 __le16 sta_idx;
1290 __le16 nonht_basic_phy;
1291 u8 phymode_ext; /* bit(0) AX_6G */
1292 u8 pad[1];
1293 } __packed;
1294
1295 struct mt76_connac_bss_qos_tlv {
1296 __le16 tag;
1297 __le16 len;
1298 u8 qos;
1299 u8 pad[3];
1300 } __packed;
1301
1302 struct mt76_connac_beacon_loss_event {
1303 u8 bss_idx;
1304 u8 reason;
1305 u8 pad[2];
1306 } __packed;
1307
1308 struct mt76_connac_mcu_bss_event {
1309 u8 bss_idx;
1310 u8 is_absent;
1311 u8 free_quota;
1312 u8 pad;
1313 } __packed;
1314
1315 struct mt76_connac_mcu_scan_ssid {
1316 __le32 ssid_len;
1317 u8 ssid[IEEE80211_MAX_SSID_LEN];
1318 } __packed;
1319
1320 struct mt76_connac_mcu_scan_channel {
1321 u8 band; /* 1: 2.4GHz
1322 * 2: 5.0GHz
1323 * Others: Reserved
1324 */
1325 u8 channel_num;
1326 } __packed;
1327
1328 struct mt76_connac_mcu_scan_match {
1329 __le32 rssi_th;
1330 u8 ssid[IEEE80211_MAX_SSID_LEN];
1331 u8 ssid_len;
1332 u8 rsv[3];
1333 } __packed;
1334
1335 struct mt76_connac_hw_scan_req {
1336 u8 seq_num;
1337 u8 bss_idx;
1338 u8 scan_type; /* 0: PASSIVE SCAN
1339 * 1: ACTIVE SCAN
1340 */
1341 u8 ssid_type; /* BIT(0) wildcard SSID
1342 * BIT(1) P2P wildcard SSID
1343 * BIT(2) specified SSID + wildcard SSID
1344 * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1345 */
1346 u8 ssids_num;
1347 u8 probe_req_num; /* Number of probe request for each SSID */
1348 u8 scan_func; /* BIT(0) Enable random MAC scan
1349 * BIT(1) Disable DBDC scan type 1~3.
1350 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1351 */
1352 u8 version; /* 0: Not support fields after ies.
1353 * 1: Support fields after ies.
1354 */
1355 struct mt76_connac_mcu_scan_ssid ssids[4];
1356 __le16 probe_delay_time;
1357 __le16 channel_dwell_time; /* channel Dwell interval */
1358 __le16 timeout_value;
1359 u8 channel_type; /* 0: Full channels
1360 * 1: Only 2.4GHz channels
1361 * 2: Only 5GHz channels
1362 * 3: P2P social channel only (channel #1, #6 and #11)
1363 * 4: Specified channels
1364 * Others: Reserved
1365 */
1366 u8 channels_num; /* valid when channel_type is 4 */
1367 /* valid when channels_num is set */
1368 struct mt76_connac_mcu_scan_channel channels[32];
1369 __le16 ies_len;
1370 u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1371 /* following fields are valid if version > 0 */
1372 u8 ext_channels_num;
1373 u8 ext_ssids_num;
1374 __le16 channel_min_dwell_time;
1375 struct mt76_connac_mcu_scan_channel ext_channels[32];
1376 struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1377 u8 bssid[ETH_ALEN];
1378 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1379 u8 pad[63];
1380 u8 ssid_type_ext;
1381 } __packed;
1382
1383 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
1384
1385 struct mt76_connac_hw_scan_done {
1386 u8 seq_num;
1387 u8 sparse_channel_num;
1388 struct mt76_connac_mcu_scan_channel sparse_channel;
1389 u8 complete_channel_num;
1390 u8 current_state;
1391 u8 version;
1392 u8 pad;
1393 __le32 beacon_scan_num;
1394 u8 pno_enabled;
1395 u8 pad2[3];
1396 u8 sparse_channel_valid_num;
1397 u8 pad3[3];
1398 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1399 /* idle format for channel_idle_time
1400 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1401 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1402 * 2: dwell time (16us)
1403 */
1404 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1405 /* beacon and probe response count */
1406 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1407 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1408 __le32 beacon_2g_num;
1409 __le32 beacon_5g_num;
1410 } __packed;
1411
1412 struct mt76_connac_sched_scan_req {
1413 u8 version;
1414 u8 seq_num;
1415 u8 stop_on_match;
1416 u8 ssids_num;
1417 u8 match_num;
1418 u8 pad;
1419 __le16 ie_len;
1420 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1421 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1422 u8 channel_type;
1423 u8 channels_num;
1424 u8 intervals_num;
1425 u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1426 struct mt76_connac_mcu_scan_channel channels[64];
1427 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1428 union {
1429 struct {
1430 u8 random_mac[ETH_ALEN];
1431 u8 pad2[58];
1432 } mt7663;
1433 struct {
1434 u8 bss_idx;
1435 u8 pad1[3];
1436 __le32 delay;
1437 u8 pad2[12];
1438 u8 random_mac[ETH_ALEN];
1439 u8 pad3[38];
1440 } mt7921;
1441 };
1442 } __packed;
1443
1444 struct mt76_connac_sched_scan_done {
1445 u8 seq_num;
1446 u8 status; /* 0: ssid found */
1447 __le16 pad;
1448 } __packed;
1449
1450 struct bss_info_uni_bss_color {
1451 __le16 tag;
1452 __le16 len;
1453 u8 enable;
1454 u8 bss_color;
1455 u8 rsv[2];
1456 } __packed;
1457
1458 struct bss_info_uni_he {
1459 __le16 tag;
1460 __le16 len;
1461 __le16 he_rts_thres;
1462 u8 he_pe_duration;
1463 u8 su_disable;
1464 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1465 u8 rsv[2];
1466 } __packed;
1467
1468 struct mt76_connac_gtk_rekey_tlv {
1469 __le16 tag;
1470 __le16 len;
1471 u8 kek[NL80211_KEK_LEN];
1472 u8 kck[NL80211_KCK_LEN];
1473 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1474 u8 rekey_mode; /* 0: rekey offload enable
1475 * 1: rekey offload disable
1476 * 2: rekey update
1477 */
1478 u8 keyid;
1479 u8 option; /* 1: rekey data update without enabling offload */
1480 u8 pad[1];
1481 __le32 proto; /* WPA-RSN-WAPI-OPSN */
1482 __le32 pairwise_cipher;
1483 __le32 group_cipher;
1484 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1485 __le32 mgmt_group_cipher;
1486 u8 reserverd[4];
1487 } __packed;
1488
1489 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16
1490 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
1491
1492 struct mt76_connac_wow_pattern_tlv {
1493 __le16 tag;
1494 __le16 len;
1495 u8 index; /* pattern index */
1496 u8 enable; /* 0: disable
1497 * 1: enable
1498 */
1499 u8 data_len; /* pattern length */
1500 u8 pad;
1501 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1502 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1503 u8 rsv[4];
1504 } __packed;
1505
1506 struct mt76_connac_wow_ctrl_tlv {
1507 __le16 tag;
1508 __le16 len;
1509 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1510 * 0x2: PM_WOWLAN_REQ_STOP
1511 * 0x3: PM_WOWLAN_PARAM_CLEAR
1512 */
1513 u8 trigger; /* 0: NONE
1514 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1515 * BIT(1): NL80211_WOWLAN_TRIG_ANY
1516 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1517 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1518 * BIT(4): BEACON_LOST
1519 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1520 */
1521 u8 wakeup_hif; /* 0x0: HIF_SDIO
1522 * 0x1: HIF_USB
1523 * 0x2: HIF_PCIE
1524 * 0x3: HIF_GPIO
1525 */
1526 u8 pad;
1527 u8 rsv[4];
1528 } __packed;
1529
1530 struct mt76_connac_wow_gpio_param_tlv {
1531 __le16 tag;
1532 __le16 len;
1533 u8 gpio_pin;
1534 u8 trigger_lvl;
1535 u8 pad[2];
1536 __le32 gpio_interval;
1537 u8 rsv[4];
1538 } __packed;
1539
1540 struct mt76_connac_arpns_tlv {
1541 __le16 tag;
1542 __le16 len;
1543 u8 mode;
1544 u8 ips_num;
1545 u8 option;
1546 u8 pad[1];
1547 } __packed;
1548
1549 struct mt76_connac_suspend_tlv {
1550 __le16 tag;
1551 __le16 len;
1552 u8 enable; /* 0: suspend mode disabled
1553 * 1: suspend mode enabled
1554 */
1555 u8 mdtim; /* LP parameter */
1556 u8 wow_suspend; /* 0: update by origin policy
1557 * 1: update by wow dtim
1558 */
1559 u8 pad[5];
1560 } __packed;
1561
1562 enum mt76_sta_info_state {
1563 MT76_STA_INFO_STATE_NONE,
1564 MT76_STA_INFO_STATE_AUTH,
1565 MT76_STA_INFO_STATE_ASSOC
1566 };
1567
1568 struct mt76_sta_cmd_info {
1569 struct ieee80211_sta *sta;
1570 struct mt76_wcid *wcid;
1571
1572 struct ieee80211_vif *vif;
1573
1574 bool offload_fw;
1575 bool enable;
1576 bool newly;
1577 int cmd;
1578 u8 rcpi;
1579 u8 state;
1580 };
1581
1582 #define MT_SKU_POWER_LIMIT 161
1583
1584 struct mt76_connac_sku_tlv {
1585 u8 channel;
1586 s8 pwr_limit[MT_SKU_POWER_LIMIT];
1587 } __packed;
1588
1589 struct mt76_connac_tx_power_limit_tlv {
1590 /* DW0 - common info*/
1591 u8 ver;
1592 u8 pad0;
1593 __le16 len;
1594 /* DW1 - cmd hint */
1595 u8 n_chan; /* # channel */
1596 u8 band; /* 2.4GHz - 5GHz - 6GHz */
1597 u8 last_msg;
1598 u8 pad1;
1599 /* DW3 */
1600 u8 alpha2[4]; /* regulatory_request.alpha2 */
1601 u8 pad2[32];
1602 } __packed;
1603
1604 struct mt76_connac_config {
1605 __le16 id;
1606 u8 type;
1607 u8 resp_type;
1608 __le16 data_size;
1609 __le16 resv;
1610 u8 data[320];
1611 } __packed;
1612
1613 static inline enum mcu_cipher_type
mt76_connac_mcu_get_cipher(int cipher)1614 mt76_connac_mcu_get_cipher(int cipher)
1615 {
1616 switch (cipher) {
1617 case WLAN_CIPHER_SUITE_WEP40:
1618 return MCU_CIPHER_WEP40;
1619 case WLAN_CIPHER_SUITE_WEP104:
1620 return MCU_CIPHER_WEP104;
1621 case WLAN_CIPHER_SUITE_TKIP:
1622 return MCU_CIPHER_TKIP;
1623 case WLAN_CIPHER_SUITE_AES_CMAC:
1624 return MCU_CIPHER_BIP_CMAC_128;
1625 case WLAN_CIPHER_SUITE_CCMP:
1626 return MCU_CIPHER_AES_CCMP;
1627 case WLAN_CIPHER_SUITE_CCMP_256:
1628 return MCU_CIPHER_CCMP_256;
1629 case WLAN_CIPHER_SUITE_GCMP:
1630 return MCU_CIPHER_GCMP;
1631 case WLAN_CIPHER_SUITE_GCMP_256:
1632 return MCU_CIPHER_GCMP_256;
1633 case WLAN_CIPHER_SUITE_SMS4:
1634 return MCU_CIPHER_WAPI;
1635 default:
1636 return MCU_CIPHER_NONE;
1637 }
1638 }
1639
1640 static inline u32
mt76_connac_mcu_gen_dl_mode(struct mt76_dev * dev,u8 feature_set,bool is_wa)1641 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1642 {
1643 u32 ret = 0;
1644
1645 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1646 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1647 if (is_mt7921(dev))
1648 ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1649 DL_CONFIG_ENCRY_MODE_SEL : 0;
1650 ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1651 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1652 ret |= DL_MODE_NEED_RSP;
1653 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1654
1655 return ret;
1656 }
1657
1658 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1659 #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
1660
1661 static inline void
mt76_connac_mcu_get_wlan_idx(struct mt76_dev * dev,struct mt76_wcid * wcid,u8 * wlan_idx_lo,u8 * wlan_idx_hi)1662 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1663 u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1664 {
1665 *wlan_idx_hi = 0;
1666
1667 if (!is_connac_v1(dev)) {
1668 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1669 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1670 } else {
1671 *wlan_idx_lo = wcid ? wcid->idx : 0;
1672 }
1673 }
1674
1675 struct sk_buff *
1676 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1677 struct mt76_wcid *wcid, int len);
1678 static inline struct sk_buff *
mt76_connac_mcu_alloc_sta_req(struct mt76_dev * dev,struct mt76_vif * mvif,struct mt76_wcid * wcid)1679 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1680 struct mt76_wcid *wcid)
1681 {
1682 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1683 MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1684 }
1685
1686 struct wtbl_req_hdr *
1687 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1688 int cmd, void *sta_wtbl, struct sk_buff **skb);
1689 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1690 int len, void *sta_ntlv,
1691 void *sta_wtbl);
1692 static inline struct tlv *
mt76_connac_mcu_add_tlv(struct sk_buff * skb,int tag,int len)1693 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1694 {
1695 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1696 }
1697
1698 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1699 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1700 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
1701 struct ieee80211_vif *vif,
1702 struct ieee80211_sta *sta, bool enable,
1703 bool newly);
1704 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1705 struct ieee80211_vif *vif,
1706 struct ieee80211_sta *sta, void *sta_wtbl,
1707 void *wtbl_tlv);
1708 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1709 struct ieee80211_vif *vif,
1710 struct mt76_wcid *wcid,
1711 void *sta_wtbl, void *wtbl_tlv);
1712 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1713 struct ieee80211_vif *vif,
1714 struct mt76_wcid *wcid, int cmd);
1715 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
1716 struct ieee80211_vif *vif,
1717 struct ieee80211_sta *sta);
1718 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1719 struct ieee80211_sta *sta,
1720 struct ieee80211_vif *vif,
1721 u8 rcpi, u8 state);
1722 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1723 struct ieee80211_sta *sta, void *sta_wtbl,
1724 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
1725 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1726 struct ieee80211_ampdu_params *params,
1727 bool enable, bool tx, void *sta_wtbl,
1728 void *wtbl_tlv);
1729 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1730 struct ieee80211_ampdu_params *params,
1731 bool enable, bool tx);
1732 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1733 struct ieee80211_vif *vif,
1734 struct mt76_wcid *wcid,
1735 bool enable);
1736 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1737 struct ieee80211_ampdu_params *params,
1738 int cmd, bool enable, bool tx);
1739 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1740 struct ieee80211_vif *vif,
1741 struct mt76_wcid *wcid,
1742 bool enable);
1743 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1744 struct mt76_sta_cmd_info *info);
1745 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1746 struct ieee80211_vif *vif);
1747 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1748 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1749 bool hdr_trans);
1750 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1751 u32 mode);
1752 int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1753 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1754 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1755 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy);
1756
1757 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1758 struct ieee80211_scan_request *scan_req);
1759 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1760 struct ieee80211_vif *vif);
1761 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1762 struct ieee80211_vif *vif,
1763 struct cfg80211_sched_scan_request *sreq);
1764 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1765 struct ieee80211_vif *vif,
1766 bool enable);
1767 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1768 struct mt76_vif *vif,
1769 struct ieee80211_bss_conf *info);
1770 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1771 struct ieee80211_vif *vif,
1772 struct cfg80211_gtk_rekey_data *key);
1773 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1774 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1775 struct ieee80211_vif *vif);
1776 int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1777 enum ieee80211_sta_state old_state,
1778 enum ieee80211_sta_state new_state);
1779 int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1780 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1781 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1782 struct mt76_connac_coredump *coredump);
1783 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1784 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1785 struct ieee80211_vif *vif);
1786 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1787 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1788
1789 const struct ieee80211_sta_he_cap *
1790 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1791 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
1792 enum nl80211_band band, struct ieee80211_sta *sta);
1793
1794 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
1795 struct mt76_connac_sta_key_conf *sta_key_conf,
1796 struct ieee80211_key_conf *key, int mcu_cmd,
1797 struct mt76_wcid *wcid, enum set_key_cmd cmd);
1798
1799 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif);
1800 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
1801 struct ieee80211_vif *vif);
1802 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
1803 struct ieee80211_vif *vif,
1804 struct ieee80211_sta *sta,
1805 struct mt76_phy *phy, u16 wlan_idx,
1806 bool enable);
1807 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
1808 struct ieee80211_sta *sta);
1809 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
1810 struct ieee80211_sta *sta,
1811 void *sta_wtbl, void *wtbl_tlv);
1812 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
1813 int mt76_connac_mcu_restart(struct mt76_dev *dev);
1814 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
1815 u8 rx_sel, u8 val);
1816 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm,
1817 const char *fw_wa);
1818 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name);
1819 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
1820 int cmd, int *wait_seq);
1821 #endif /* __MT76_CONNAC_MCU_H */
1822