1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * drivers/net/ethernet/ibm/emac/mal.h
4  *
5  * Memory Access Layer (MAL) support
6  *
7  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
8  *                <benh@kernel.crashing.org>
9  *
10  * Based on the arch/ppc version of the driver:
11  *
12  * Copyright (c) 2004, 2005 Zultys Technologies.
13  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14  *
15  * Based on original work by
16  *      Armin Kuster <akuster@mvista.com>
17  *      Copyright 2002 MontaVista Softare Inc.
18  */
19 #ifndef __IBM_NEWEMAC_MAL_H
20 #define __IBM_NEWEMAC_MAL_H
21 
22 /*
23  * There are some variations on the MAL, we express them in this driver as
24  * MAL Version 1 and 2 though that doesn't match any IBM terminology.
25  *
26  * We call MAL 1 the version in 405GP, 405GPR, 405EP, 440EP, 440GR and
27  * NP405H.
28  *
29  * We call MAL 2 the version in 440GP, 440GX, 440SP, 440SPE and Axon
30  *
31  * The driver expects a "version" property in the emac node containing
32  * a number 1 or 2. New device-trees for EMAC capable platforms are thus
33  * required to include that when porting to arch/powerpc.
34  */
35 
36 /* MALx DCR registers */
37 #define	MAL_CFG			0x00
38 #define	  MAL_CFG_SR		0x80000000
39 #define   MAL_CFG_PLBB		0x00004000
40 #define   MAL_CFG_OPBBL		0x00000080
41 #define   MAL_CFG_EOPIE		0x00000004
42 #define   MAL_CFG_LEA		0x00000002
43 #define   MAL_CFG_SD		0x00000001
44 
45 /* MAL V1 CFG bits */
46 #define   MAL1_CFG_PLBP_MASK	0x00c00000
47 #define   MAL1_CFG_PLBP_10	0x00800000
48 #define   MAL1_CFG_GA		0x00200000
49 #define   MAL1_CFG_OA		0x00100000
50 #define   MAL1_CFG_PLBLE	0x00080000
51 #define   MAL1_CFG_PLBT_MASK	0x00078000
52 #define   MAL1_CFG_DEFAULT	(MAL1_CFG_PLBP_10 | MAL1_CFG_PLBT_MASK)
53 
54 /* MAL V2 CFG bits */
55 #define   MAL2_CFG_RPP_MASK	0x00c00000
56 #define   MAL2_CFG_RPP_10	0x00800000
57 #define   MAL2_CFG_RMBS_MASK	0x00300000
58 #define   MAL2_CFG_WPP_MASK	0x000c0000
59 #define   MAL2_CFG_WPP_10	0x00080000
60 #define   MAL2_CFG_WMBS_MASK	0x00030000
61 #define   MAL2_CFG_PLBLE	0x00008000
62 #define   MAL2_CFG_DEFAULT	(MAL2_CFG_RMBS_MASK | MAL2_CFG_WMBS_MASK | \
63 				 MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10)
64 
65 #define MAL_ESR			0x01
66 #define   MAL_ESR_EVB		0x80000000
67 #define   MAL_ESR_CIDT		0x40000000
68 #define   MAL_ESR_CID_MASK	0x3e000000
69 #define   MAL_ESR_CID_SHIFT	25
70 #define   MAL_ESR_DE		0x00100000
71 #define   MAL_ESR_OTE		0x00040000
72 #define   MAL_ESR_OSE		0x00020000
73 #define   MAL_ESR_PEIN		0x00010000
74 #define   MAL_ESR_DEI		0x00000010
75 #define   MAL_ESR_OTEI		0x00000004
76 #define   MAL_ESR_OSEI		0x00000002
77 #define   MAL_ESR_PBEI		0x00000001
78 
79 /* MAL V1 ESR bits */
80 #define   MAL1_ESR_ONE		0x00080000
81 #define   MAL1_ESR_ONEI		0x00000008
82 
83 /* MAL V2 ESR bits */
84 #define   MAL2_ESR_PTE		0x00800000
85 #define   MAL2_ESR_PRE		0x00400000
86 #define   MAL2_ESR_PWE		0x00200000
87 #define   MAL2_ESR_PTEI		0x00000080
88 #define   MAL2_ESR_PREI		0x00000040
89 #define   MAL2_ESR_PWEI		0x00000020
90 
91 
92 #define MAL_IER			0x02
93 /* MAL IER bits */
94 #define   MAL_IER_DE		0x00000010
95 #define   MAL_IER_OTE		0x00000004
96 #define   MAL_IER_OE		0x00000002
97 #define   MAL_IER_PE		0x00000001
98 
99 /* PLB read/write/timeout errors */
100 #define   MAL_IER_PTE		0x00000080
101 #define   MAL_IER_PRE		0x00000040
102 #define   MAL_IER_PWE		0x00000020
103 
104 #define   MAL_IER_SOC_EVENTS	(MAL_IER_PTE | MAL_IER_PRE | MAL_IER_PWE)
105 #define   MAL_IER_EVENTS	(MAL_IER_SOC_EVENTS | MAL_IER_DE | \
106 				 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
107 
108 #define MAL_TXCASR		0x04
109 #define MAL_TXCARR		0x05
110 #define MAL_TXEOBISR		0x06
111 #define MAL_TXDEIR		0x07
112 #define MAL_RXCASR		0x10
113 #define MAL_RXCARR		0x11
114 #define MAL_RXEOBISR		0x12
115 #define MAL_RXDEIR		0x13
116 #define MAL_TXCTPR(n)		((n) + 0x20)
117 #define MAL_RXCTPR(n)		((n) + 0x40)
118 #define MAL_RCBS(n)		((n) + 0x60)
119 
120 /* In reality MAL can handle TX buffers up to 4095 bytes long,
121  * but this isn't a good round number :) 		 --ebs
122  */
123 #define MAL_MAX_TX_SIZE		4080
124 #define MAL_MAX_RX_SIZE		4080
125 
mal_rx_size(int len)126 static inline int mal_rx_size(int len)
127 {
128 	len = (len + 0xf) & ~0xf;
129 	return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
130 }
131 
mal_tx_chunks(int len)132 static inline int mal_tx_chunks(int len)
133 {
134 	return DIV_ROUND_UP(len, MAL_MAX_TX_SIZE);
135 }
136 
137 #define MAL_CHAN_MASK(n)	(0x80000000 >> (n))
138 
139 /* MAL Buffer Descriptor structure */
140 struct mal_descriptor {
141 	u16 ctrl;		/* MAL / Commac status control bits */
142 	u16 data_len;		/* Max length is 4K-1 (12 bits)     */
143 	u32 data_ptr;		/* pointer to actual data buffer    */
144 };
145 
146 /* the following defines are for the MadMAL status and control registers. */
147 /* MADMAL transmit and receive status/control bits  */
148 #define MAL_RX_CTRL_EMPTY	0x8000
149 #define MAL_RX_CTRL_WRAP	0x4000
150 #define MAL_RX_CTRL_CM		0x2000
151 #define MAL_RX_CTRL_LAST	0x1000
152 #define MAL_RX_CTRL_FIRST	0x0800
153 #define MAL_RX_CTRL_INTR	0x0400
154 #define MAL_RX_CTRL_SINGLE	(MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
155 #define MAL_IS_SINGLE_RX(ctrl)	(((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
156 
157 #define MAL_TX_CTRL_READY	0x8000
158 #define MAL_TX_CTRL_WRAP	0x4000
159 #define MAL_TX_CTRL_CM		0x2000
160 #define MAL_TX_CTRL_LAST	0x1000
161 #define MAL_TX_CTRL_INTR	0x0400
162 
163 struct mal_commac_ops {
164 	void	(*poll_tx) (void *dev);
165 	int	(*poll_rx) (void *dev, int budget);
166 	int	(*peek_rx) (void *dev);
167 	void	(*rxde) (void *dev);
168 };
169 
170 struct mal_commac {
171 	struct mal_commac_ops	*ops;
172 	void			*dev;
173 	struct list_head	poll_list;
174 	long       		flags;
175 #define MAL_COMMAC_RX_STOPPED		0
176 #define MAL_COMMAC_POLL_DISABLED	1
177 	u32			tx_chan_mask;
178 	u32			rx_chan_mask;
179 	struct list_head	list;
180 };
181 
182 struct mal_instance {
183 	int			version;
184 	dcr_host_t		dcr_host;
185 
186 	int			num_tx_chans;	/* Number of TX channels */
187 	int			num_rx_chans;	/* Number of RX channels */
188 	int 			txeob_irq;	/* TX End Of Buffer IRQ  */
189 	int 			rxeob_irq;	/* RX End Of Buffer IRQ  */
190 	int			txde_irq;	/* TX Descriptor Error IRQ */
191 	int			rxde_irq;	/* RX Descriptor Error IRQ */
192 	int			serr_irq;	/* MAL System Error IRQ    */
193 
194 	struct list_head	poll_list;
195 	struct napi_struct	napi;
196 
197 	struct list_head	list;
198 	u32			tx_chan_mask;
199 	u32			rx_chan_mask;
200 
201 	dma_addr_t		bd_dma;
202 	struct mal_descriptor	*bd_virt;
203 
204 	struct platform_device	*ofdev;
205 	int			index;
206 	spinlock_t		lock;
207 
208 	struct net_device	dummy_dev;
209 
210 	unsigned int features;
211 };
212 
get_mal_dcrn(struct mal_instance * mal,int reg)213 static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
214 {
215 	return dcr_read(mal->dcr_host, reg);
216 }
217 
set_mal_dcrn(struct mal_instance * mal,int reg,u32 val)218 static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
219 {
220 	dcr_write(mal->dcr_host, reg, val);
221 }
222 
223 /* Features of various MAL implementations */
224 
225 /* Set if you have interrupt coalescing and you have to clear the SDR
226  * register for TXEOB and RXEOB interrupts to work
227  */
228 #define MAL_FTR_CLEAR_ICINTSTAT	0x00000001
229 
230 /* Set if your MAL has SERR, TXDE, and RXDE OR'd into a single UIC
231  * interrupt
232  */
233 #define MAL_FTR_COMMON_ERR_INT	0x00000002
234 
235 enum {
236 	MAL_FTRS_ALWAYS = 0,
237 
238 	MAL_FTRS_POSSIBLE =
239 #ifdef CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT
240 		MAL_FTR_CLEAR_ICINTSTAT |
241 #endif
242 #ifdef CONFIG_IBM_EMAC_MAL_COMMON_ERR
243 		MAL_FTR_COMMON_ERR_INT |
244 #endif
245 		0,
246 };
247 
mal_has_feature(struct mal_instance * dev,unsigned long feature)248 static inline int mal_has_feature(struct mal_instance *dev,
249 		unsigned long feature)
250 {
251 	return (MAL_FTRS_ALWAYS & feature) ||
252 		(MAL_FTRS_POSSIBLE & dev->features & feature);
253 }
254 
255 /* Register MAL devices */
256 int mal_init(void);
257 void mal_exit(void);
258 
259 int mal_register_commac(struct mal_instance *mal,
260 			struct mal_commac *commac);
261 void mal_unregister_commac(struct mal_instance *mal,
262 			   struct mal_commac *commac);
263 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size);
264 
265 /* Returns BD ring offset for a particular channel
266    (in 'struct mal_descriptor' elements)
267 */
268 int mal_tx_bd_offset(struct mal_instance *mal, int channel);
269 int mal_rx_bd_offset(struct mal_instance *mal, int channel);
270 
271 void mal_enable_tx_channel(struct mal_instance *mal, int channel);
272 void mal_disable_tx_channel(struct mal_instance *mal, int channel);
273 void mal_enable_rx_channel(struct mal_instance *mal, int channel);
274 void mal_disable_rx_channel(struct mal_instance *mal, int channel);
275 
276 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac);
277 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac);
278 
279 /* Add/remove EMAC to/from MAL polling list */
280 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac);
281 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac);
282 
283 /* Ethtool MAL registers */
284 struct mal_regs {
285 	u32 tx_count;
286 	u32 rx_count;
287 
288 	u32 cfg;
289 	u32 esr;
290 	u32 ier;
291 	u32 tx_casr;
292 	u32 tx_carr;
293 	u32 tx_eobisr;
294 	u32 tx_deir;
295 	u32 rx_casr;
296 	u32 rx_carr;
297 	u32 rx_eobisr;
298 	u32 rx_deir;
299 	u32 tx_ctpr[32];
300 	u32 rx_ctpr[32];
301 	u32 rcbs[32];
302 };
303 
304 int mal_get_regs_len(struct mal_instance *mal);
305 void *mal_dump_regs(struct mal_instance *mal, void *buf);
306 
307 #endif /* __IBM_NEWEMAC_MAL_H */
308