1 #ifndef _INC_LIBSBEW_H_
2 #define _INC_LIBSBEW_H_
3 
4 /*-----------------------------------------------------------------------------
5  * libsbew.h - common library elements, charge across mulitple boards
6  *
7  *   This file contains common Ioctl structures and contents definitions.
8  *
9  * Copyright (C) 2004-2005  SBE, Inc.
10  *
11  *   This program is free software; you can redistribute it and/or modify
12  *   it under the terms of the GNU General Public License as published by
13  *   the Free Software Foundation; either version 2 of the License, or
14  *   (at your option) any later version.
15  *
16  *   This program is distributed in the hope that it will be useful,
17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  *   GNU General Public License for more details.
20  *
21  * For further information, contact via email: support@sbei.com
22  * SBE, Inc.  San Ramon, California  U.S.A.
23  *-----------------------------------------------------------------------------
24  */
25 
26 /********************************/
27 /**  set driver logging level  **/
28 /********************************/
29 
30 /* routine/ioctl: wancfg_set_loglevel() - SBE_IOC_SET_LOGLEVEL */
31 
32 #define LOG_NONE          0
33 #define LOG_ERROR         1
34 #define LOG_SBEBUG3       3     /* hidden, for development/debug usage */
35 #define LOG_LSCHANGE      5     /* line state change logging */
36 #define LOG_LSIMMEDIATE   6     /* line state change logging w/o hysterisis */
37 #define LOG_WARN          8
38 #define LOG_MONITOR      10
39 #define LOG_SBEBUG12     12     /* hidden, for development/debug usage */
40 #define LOG_MONITOR2     14     /* hidden, for development/debug usage */
41 #define LOG_DEBUG        16
42 
43     /* TEMPORARY DEFINES *//* RLD DEBUG */
44 #define c4_LOG_NONE      LOG_NONE
45 #define c4_LOG_ERROR     LOG_ERROR
46 #define c4_LOG_WARN      LOG_WARN
47 #define c4_LOG_sTrace    LOG_MONITOR    /* do some trace logging into
48                                          * functions */
49 #define c4_LOG_DEBUG     LOG_DEBUG
50 #define c4_LOG_MAX       LOG_DEBUG
51 
52 
53 
54 /******************************/
55 /**  get driver information  **/
56 /******************************/
57 
58 /* routine/ioctl: wancfg_get_drvinfo() - SBE_IOC_GET_DRVINFO */
59 
60 #define REL_STRLEN   80
61     struct sbe_drv_info
62     {
63         int         rel_strlen;
64         char        release[REL_STRLEN];
65     };
66 
67 
68 /*****************************/
69 /**  get board information  **/
70 /*****************************/
71 
72 /* routine/ioctl: wancfg_get_brdinfo() - SBE_IOC_GET_BRDINFO */
73 
74 #define CHNM_STRLEN   16
75     struct sbe_brd_info
76     {
77         u_int32_t brd_id;       /* SBE's unique PCI VENDOR/DEVID */
78         u_int32_t   brd_sn;
79         int         brd_chan_cnt;       /* number of channels being used */
80         int         brd_port_cnt;       /* number of ports being used */
81         unsigned char brdno;    /* our board number */
82         unsigned char brd_pci_speed;    /* PCI speed, 33/66Mhz */
83                     u_int8_t brd_mac_addr[6];
84         char        first_iname[CHNM_STRLEN];   /* first assigned channel's
85                                                  * interface name */
86         char        last_iname[CHNM_STRLEN];    /* last assigned channel's
87                                                  * interface name */
88         u_int8_t    brd_hdw_id; /* on/board unique hdw ID */
89         u_int8_t    reserved8[3];       /* alignment preservation */
90         u_int32_t   reserved32[3];      /* size preservation */
91     };
92 
93 /* These IDs are sometimes available thru pci_ids.h, but not currently. */
94 
95 #define PCI_VENDOR_ID_SBE              0x1176
96 #define PCI_DEVICE_ID_WANPMC_C4T1E1    0x0701   /* BID 0x0X, BTYP 0x0X */
97 #define PCI_DEVICE_ID_WANPTMC_C4T1E1   0x0702   /* BID 0x41 */
98 #define PCI_DEVICE_ID_WANADAPT_HC4T1E1 0x0703   /* BID 0x44 */
99 #define PCI_DEVICE_ID_WANPTMC_256T3_T1 0x0704   /* BID 0x42 (T1 Version) */
100 #define PCI_DEVICE_ID_WANPCI_C4T1E1    0x0705   /* BID 0x1X, BTYP 0x0X */
101 #define PCI_DEVICE_ID_WANPMC_C1T3      0x0706   /* BID 0x45 */
102 #define PCI_DEVICE_ID_WANPCI_C2T1E1    0x0707   /* BID 0x1X, BTYP 0x2X */
103 #define PCI_DEVICE_ID_WANPCI_C1T1E1    0x0708   /* BID 0x1X, BTYP 0x1X */
104 #define PCI_DEVICE_ID_WANPMC_C2T1E1    0x0709   /* BID 0x0X, BTYP 0x2X */
105 #define PCI_DEVICE_ID_WANPMC_C1T1E1    0x070A   /* BID 0x0X, BTYP 0x1X */
106 #define PCI_DEVICE_ID_WANPTMC_256T3_E1 0x070B   /* BID 0x46 (E1 Version) */
107 #define PCI_DEVICE_ID_WANPTMC_C24TE1   0x070C   /* BID 0x47 */
108 #define PCI_DEVICE_ID_WANPMC_C4T1E1_L  0x070D   /* BID 0x2X, BTYPE 0x0X w/FP
109                                                  * LEDs */
110 #define PCI_DEVICE_ID_WANPMC_C2T1E1_L  0x070E   /* BID 0x2X, BTYPE 0x2X w/FP
111                                                  * LEDs */
112 #define PCI_DEVICE_ID_WANPMC_C1T1E1_L  0x070F   /* BID 0x2X, BTYPE 0x1X w/FP
113                                                  * LEDs */
114 #define PCI_DEVICE_ID_WANPMC_2SSI      0x0801
115 #define PCI_DEVICE_ID_WANPCI_4SSI      0x0802
116 #define PCI_DEVICE_ID_WANPMC_2T3E3     0x0900   /* BID 0x43 */
117 #define SBE_BOARD_ID(v,id)           ((v<<16) | id)
118 
119 #define BINFO_PCI_SPEED_unk     0
120 #define BINFO_PCI_SPEED_33      1
121 #define BINFO_PCI_SPEED_66      2
122 
123 /***************************/
124 /**  obtain interface ID  **/
125 /***************************/
126 
127 /* routine/ioctl: wancfg_get_iid() - SBE_IOC_IID_GET */
128 
129     struct sbe_iid_info
130     {
131         u_int32_t   channum;    /* channel requested */
132         char        iname[CHNM_STRLEN]; /* channel's interface name */
133     };
134 
135 /**************************************/
136 /**  get board address information  **/
137 /**************************************/
138 
139 /* routine/ioctl: wancfg_get_brdaddr() - SBE_IOC_BRDADDR_GET */
140 
141     struct sbe_brd_addr
142     {
143         unsigned char func;     /* select PCI address space function */
144         unsigned char brdno;    /* returns brdno requested */
145         unsigned char irq;
146         unsigned char size;     /* returns size of address */
147 #define BRDADDR_SIZE_64  1
148 #define BRDADDR_SIZE_32  2
149         int         reserved1;  /* mod64 align, reserved for future use */
150 
151         union
152         {
153             unsigned long virt64;       /* virtual/mapped address */
154             u_int32_t   virt32[2];
155         }           v;
156         union
157         {
158             unsigned long phys64;       /* physical bus address */
159             u_int32_t   phys32[2];
160         }           p;
161         int         reserved2[4];       /* reserved for future use */
162     };
163 
164 /**********************************/
165 /**  read/write board registers  **/
166 /**********************************/
167 
168 /* routine/ioctl: wancfg_read_vec() - SBE_IOC_READ_VEC */
169 /* routine/ioctl: wancfg_write_vec() - SBE_IOC_WRITE_VEC */
170 
171     struct sbecom_wrt_vec
172     {
173         u_int32_t   reg;
174         u_int32_t   data;
175     };
176 
177 #define C1T3_CHIP_MSCC_32        0x01000000
178 #define C1T3_CHIP_TECT3_8        0x02000000
179 #define C1T3_CHIP_CPLD_8         0x03000000
180 #define C1T3_CHIP_EEPROM_8       0x04000000
181 
182 #define W256T3_CHIP_MUSYCC_32    0x02000000
183 #define W256T3_CHIP_TEMUX_8      0x10000000
184 #define W256T3_CHIP_T8110_8      0x20000000
185 #define W256T3_CHIP_T8110_32     0x22000000
186 #define W256T3_CHIP_CPLD_8       0x30000000
187 #define W256T3_CHIP_EEPROM_8     0x40000000
188 
189 
190 /**********************************/
191 /**  read write port parameters  **/
192 /**********************************/
193 
194 /* routine/ioctl: wancfg_getset_port_param() - SBE_IOC_PORT_GET */
195 /* routine/ioctl: wancfg_set_port_param() - SBE_IOC_PORT_SET */
196 
197 /* NOTE: this structure supports hardware which supports individual per/port control */
198 
199 struct sbecom_port_param
200 {
201     u_int8_t    portnum;
202     u_int8_t    port_mode;           /* variations of T1 or E1 mode */
203     u_int8_t    portStatus;
204     u_int8_t    portP;          /* more port parameters (clock source - 0x80;
205                                  * and LBO - 0xf; */
206                                 /* bits 0x70 are reserved for future use ) */
207 #ifdef SBE_PMCC4_ENABLE
208 	u_int32_t   hypersize;  /* RLD DEBUG - add this in until I learn how to make this entry obsolete */
209 #endif
210     int         reserved[3-1];    /* reserved for future use */
211     int    _res[4];
212 };
213 
214 #define CFG_CLK_PORT_MASK      0x80     /* Loop timing */
215 #define CFG_CLK_PORT_INTERNAL  0x80     /* Loop timing */
216 #define CFG_CLK_PORT_EXTERNAL  0x00     /* Loop timing */
217 
218 #define CFG_LBO_MASK      0x0F
219 #define CFG_LBO_unk       0     /* <not defined> */
220 #define CFG_LBO_LH0       1     /* T1 Long Haul (default) */
221 #define CFG_LBO_LH7_5     2     /* T1 Long Haul */
222 #define CFG_LBO_LH15      3     /* T1 Long Haul */
223 #define CFG_LBO_LH22_5    4     /* T1 Long Haul */
224 #define CFG_LBO_SH110     5     /* T1 Short Haul */
225 #define CFG_LBO_SH220     6     /* T1 Short Haul */
226 #define CFG_LBO_SH330     7     /* T1 Short Haul */
227 #define CFG_LBO_SH440     8     /* T1 Short Haul */
228 #define CFG_LBO_SH550     9     /* T1 Short Haul */
229 #define CFG_LBO_SH660     10    /* T1 Short Haul */
230 #define CFG_LBO_E75       11    /* E1 75 Ohm */
231 #define CFG_LBO_E120      12    /* E1 120 Ohm (default) */
232 
233 
234 /*************************************/
235 /**  read write channel parameters  **/
236 /*************************************/
237 
238 /* routine/ioctl: wancfg_getset_chan_param() - SBE_IOC_CHAN_GET */
239 /* routine/ioctl: wancfg_set_chan_param() - SBE_IOC_CHAN_SET */
240 
241 /* NOTE: this structure supports hardware which supports individual per/channel control */
242 
243     struct sbecom_chan_param
244     {
245         u_int32_t   channum;    /* 0: */
246 #ifdef SBE_PMCC4_ENABLE
247 	u_int32_t   card;  /* RLD DEBUG - add this in until I learn how to make this entry obsolete */
248 	u_int32_t   port;  /* RLD DEBUG - add this in until I learn how to make this entry obsolete */
249 	u_int8_t bitmask[32];
250 #endif
251         u_int32_t   intr_mask;  /* 4: interrupt mask, specify ored
252                                  * (SS7_)INTR_* to disable */
253         u_int8_t    status;     /* 8: channel transceiver status (TX_ENABLED,
254                                  * RX_ENABLED) */
255         u_int8_t    chan_mode;  /* 9: protocol mode */
256         u_int8_t    idlecode;   /* A: idle code, in (FLAG_7E, FLAG_FF,
257                                  * FLAG_00) */
258         u_int8_t    pad_fill_count;     /* B: pad fill count (1-127), 0 - pad
259                                          * fill disabled */
260         u_int8_t    data_inv;   /* C: channel data inversion selection */
261         u_int8_t    mode_56k;   /* D: 56kbps mode */
262         u_int8_t    reserved[2 + 8];    /* E: */
263     };
264 
265 /* SS7 interrupt signals <intr_mask> */
266 #define SS7_INTR_SFILT      0x00000020
267 #define SS7_INTR_SDEC       0x00000040
268 #define SS7_INTR_SINC       0x00000080
269 #define SS7_INTR_SUERR      0x00000100
270 /* Other interrupts that can be masked */
271 #define INTR_BUFF           0x00000002
272 #define INTR_EOM            0x00000004
273 #define INTR_MSG            0x00000008
274 #define INTR_IDLE           0x00000010
275 
276 /* transceiver status flags <status> */
277 #define TX_ENABLED          0x01
278 #define RX_ENABLED          0x02
279 
280 /* Protocol modes <mode> */
281 #define CFG_CH_PROTO_TRANS         0
282 #define CFG_CH_PROTO_SS7           1
283 #define CFG_CH_PROTO_HDLC_FCS16    2
284 #define CFG_CH_PROTO_HDLC_FCS32    3
285 #define CFG_CH_PROTO_ISLP_MODE     4
286 
287 /* Possible idle code assignments <idlecode> */
288 #define CFG_CH_FLAG_7E      0
289 #define CFG_CH_FLAG_FF      1
290 #define CFG_CH_FLAG_00      2
291 
292 /* data inversion selection <data_inv> */
293 #define CFG_CH_DINV_NONE    0x00
294 #define CFG_CH_DINV_RX      0x01
295 #define CFG_CH_DINV_TX      0x02
296 
297 
298 /* Possible resettable chipsets/functions */
299 #define RESET_DEV_TEMUX     1
300 #define RESET_DEV_TECT3     RESET_DEV_TEMUX
301 #define RESET_DEV_PLL       2
302 
303 
304 /*********************************************/
305 /**  read reset channel thruput statistics  **/
306 /*********************************************/
307 
308 /* routine/ioctl: wancfg_get_chan_stats() - SBE_IOC_CHAN_GET_STAT */
309 /* routine/ioctl: wancfg_del_chan_stats() - SBE_IOC_CHAN_DEL_STAT */
310 /* routine/ioctl: wancfg_get_card_chan_stats() - SBE_IOC_CARD_CHAN_STAT */
311 
312     struct sbecom_chan_stats
313     {
314         unsigned long rx_packets;       /* total packets received       */
315         unsigned long tx_packets;       /* total packets transmitted    */
316         unsigned long rx_bytes; /* total bytes received         */
317         unsigned long tx_bytes; /* total bytes transmitted      */
318         unsigned long rx_errors;/* bad packets received         */
319         unsigned long tx_errors;/* packet transmit problems     */
320         unsigned long rx_dropped;       /* no space in linux buffers    */
321         unsigned long tx_dropped;       /* no space available in linux  */
322 
323         /* detailed rx_errors: */
324         unsigned long rx_length_errors;
325         unsigned long rx_over_errors;   /* receiver ring buff overflow  */
326         unsigned long rx_crc_errors;    /* recved pkt with crc error    */
327         unsigned long rx_frame_errors;  /* recv'd frame alignment error */
328         unsigned long rx_fifo_errors;   /* recv'r fifo overrun          */
329         unsigned long rx_missed_errors; /* receiver missed packet       */
330 
331         /* detailed tx_errors */
332         unsigned long tx_aborted_errors;
333         unsigned long tx_fifo_errors;
334         unsigned long tx_pending;
335     };
336 
337 
338 /****************************************/
339 /**  read write card level parameters  **/
340 /****************************************/
341 
342  /* NOTE: this structure supports hardware which supports per/card control */
343 
344     struct sbecom_card_param
345     {
346         u_int8_t    framing_type;       /* 0: CBP or M13 */
347         u_int8_t    loopback;   /* 1: one of LOOPBACK_* */
348         u_int8_t    line_build_out;     /* 2: boolean */
349         u_int8_t    receive_eq; /* 3: boolean */
350         u_int8_t    transmit_ones;      /* 4: boolean */
351         u_int8_t    clock;      /* 5: 0 - internal, i>0 - external (recovered
352                                  * from framer i) */
353         u_int8_t    h110enable; /* 6: */
354         u_int8_t    disable_leds;       /* 7: */
355         u_int8_t    reserved1;  /* 8: available - old 256t3 hypersized, but
356                                  * never used */
357         u_int8_t    rear_io;    /* 9: rear I/O off/on */
358         u_int8_t    disable_tx; /* A: disable TX off/on */
359         u_int8_t    mute_los;   /* B: mute LOS off/on */
360         u_int8_t    los_threshold;      /* C: LOS threshold norm/low
361                                          * (default: norm) */
362         u_int8_t    ds1_mode;   /* D: DS1 mode T1/E1 (default: T1) */
363         u_int8_t    ds3_unchan; /* E: DS3 unchannelized mode off/on */
364         u_int8_t    reserved[1 + 16];   /* reserved for expansion - must be
365                                          * ZERO filled */
366     };
367 
368 /* framing types <framing_type> */
369 #define FRAMING_M13                0
370 #define FRAMING_CBP                1
371 
372 /* card level loopback options <loopback> */
373 #define CFG_CARD_LOOPBACK_NONE     0x00
374 #define CFG_CARD_LOOPBACK_DIAG     0x01
375 #define CFG_CARD_LOOPBACK_LINE     0x02
376 #define CFG_CARD_LOOPBACK_PAYLOAD  0x03
377 
378 /* line level loopback options <loopback> */
379 #define CFG_LIU_LOOPBACK_NONE      0x00
380 #define CFG_LIU_LOOPBACK_ANALOG    0x10
381 #define CFG_LIU_LOOPBACK_DIGITAL   0x11
382 #define CFG_LIU_LOOPBACK_REMOTE    0x12
383 
384 /* card level clock options <clock> */
385 #define CFG_CLK_INTERNAL           0x00
386 #define CFG_CLK_EXTERNAL           0x01
387 
388 /* legacy 256T3 loopback values */
389 #define LOOPBACK_NONE              0
390 #define LOOPBACK_LIU_ANALOG        1
391 #define LOOPBACK_LIU_DIGITAL       2
392 #define LOOPBACK_FRAMER_DS3        3
393 #define LOOPBACK_FRAMER_T1         4
394 #define LOOPBACK_LIU_REMOTE        5
395 
396 /* DS1 mode <ds1_mode> */
397 #define CFG_DS1_MODE_MASK          0x0f
398 #define CFG_DS1_MODE_T1            0x00
399 #define CFG_DS1_MODE_E1            0x01
400 #define CFG_DS1_MODE_CHANGE        0x80
401 
402 /* DS3 unchannelized values <ds1_unchan> */
403 #define CFG_DS3_UNCHAN_MASK        0x01
404 #define CFG_DS3_UNCHAN_OFF         0x00
405 #define CFG_DS3_UNCHAN_ON          0x01
406 
407 
408 /************************************/
409 /**  read write framer parameters  **/
410 /************************************/
411 
412 /* routine/ioctl: wancfg_get_framer() - SBE_IOC_FRAMER_GET */
413 /* routine/ioctl: wancfg_set_framer() - SBE_IOC_FRAMER_SET */
414 
415     struct sbecom_framer_param
416     {
417         u_int8_t    framer_num;
418         u_int8_t    frame_type; /* SF, ESF, E1PLAIN, E1CAS, E1CRC, E1CRC+CAS */
419         u_int8_t    loopback_type;      /* DIGITAL, LINE, PAYLOAD */
420         u_int8_t    auto_alarms;/* auto alarms */
421         u_int8_t    reserved[12];       /* reserved for expansion - must be
422                                          * ZERO filled */
423     };
424 
425 /* frame types <frame_type> */
426 #define CFG_FRAME_NONE             0
427 #define CFG_FRAME_SF               1    /* T1 B8ZS */
428 #define CFG_FRAME_ESF              2    /* T1 B8ZS */
429 #define CFG_FRAME_E1PLAIN          3    /* HDB3 w/o CAS,CRC */
430 #define CFG_FRAME_E1CAS            4    /* HDB3 */
431 #define CFG_FRAME_E1CRC            5    /* HDB3 */
432 #define CFG_FRAME_E1CRC_CAS        6    /* HDB3 */
433 #define CFG_FRAME_SF_AMI           7    /* T1 AMI */
434 #define CFG_FRAME_ESF_AMI          8    /* T1 AMI */
435 #define CFG_FRAME_E1PLAIN_AMI      9    /* E1 AMI w/o CAS,CRC */
436 #define CFG_FRAME_E1CAS_AMI       10    /* E1 AMI */
437 #define CFG_FRAME_E1CRC_AMI       11    /* E1 AMI */
438 #define CFG_FRAME_E1CRC_CAS_AMI   12    /* E1 AMI */
439 
440 #define IS_FRAME_ANY_T1(field) \
441                     (((field) == CFG_FRAME_NONE) || \
442                      ((field) == CFG_FRAME_SF)   || \
443                      ((field) == CFG_FRAME_ESF)  || \
444                      ((field) == CFG_FRAME_SF_AMI) || \
445                      ((field) == CFG_FRAME_ESF_AMI))
446 
447 #define IS_FRAME_ANY_T1ESF(field) \
448                     (((field) == CFG_FRAME_ESF) || \
449                      ((field) == CFG_FRAME_ESF_AMI))
450 
451 #define IS_FRAME_ANY_E1(field) \
452                     (((field) == CFG_FRAME_E1PLAIN) || \
453                      ((field) == CFG_FRAME_E1CAS)   || \
454                      ((field) == CFG_FRAME_E1CRC)   || \
455                      ((field) == CFG_FRAME_E1CRC_CAS) || \
456                      ((field) == CFG_FRAME_E1PLAIN_AMI) || \
457                      ((field) == CFG_FRAME_E1CAS_AMI) || \
458                      ((field) == CFG_FRAME_E1CRC_AMI) || \
459                      ((field) == CFG_FRAME_E1CRC_CAS_AMI))
460 
461 #define IS_FRAME_ANY_AMI(field) \
462                     (((field) == CFG_FRAME_SF_AMI) || \
463                      ((field) == CFG_FRAME_ESF_AMI) || \
464                      ((field) == CFG_FRAME_E1PLAIN_AMI) || \
465                      ((field) == CFG_FRAME_E1CAS_AMI) || \
466                      ((field) == CFG_FRAME_E1CRC_AMI) || \
467                      ((field) == CFG_FRAME_E1CRC_CAS_AMI))
468 
469 /* frame level loopback options <loopback_type> */
470 #define CFG_FRMR_LOOPBACK_NONE     0
471 #define CFG_FRMR_LOOPBACK_DIAG     1
472 #define CFG_FRMR_LOOPBACK_LINE     2
473 #define CFG_FRMR_LOOPBACK_PAYLOAD  3
474 
475 
476 /****************************************/
477 /**  read reset card error statistics  **/
478 /****************************************/
479 
480 /* routine/ioctl: wancfg_get_card_stats() - SBE_IOC_CARD_GET_STAT */
481 /* routine/ioctl: wancfg_del_card_stats() - SBE_IOC_CARD_DEL_STAT */
482 
483     struct temux_card_stats
484     {
485         struct temux_stats
486         {
487             /* TEMUX DS3 PMON counters */
488             u_int32_t   lcv;
489             u_int32_t   err_framing;
490             u_int32_t   febe;
491             u_int32_t   err_cpbit;
492             u_int32_t   err_parity;
493             /* TEMUX DS3 FRMR status */
494             u_int8_t    los;
495             u_int8_t    oof;
496             u_int8_t    red;
497             u_int8_t    yellow;
498             u_int8_t    idle;
499             u_int8_t    ais;
500             u_int8_t    cbit;
501             /* TEMUX DS3 FEAC receiver */
502             u_int8_t    feac;
503             u_int8_t    feac_last;
504         }           t;
505         u_int32_t   tx_pending; /* total */
506     };
507 
508 /**************************************************************/
509 
510     struct wancfg
511     {
512         int         cs, ds;
513         char       *p;
514     };
515     typedef struct wancfg wcfg_t;
516 
517     extern wcfg_t *wancfg_init (char *, char *);
518     extern int  wancfg_card_blink (wcfg_t *, int);
519     extern int  wancfg_ctl (wcfg_t *, int, void *, int, void *, int);
520     extern int  wancfg_del_card_stats (wcfg_t *);
521     extern int  wancfg_del_chan_stats (wcfg_t *, int);
522     extern int  wancfg_enable_ports (wcfg_t *, int);
523     extern int  wancfg_free (wcfg_t *);
524     extern int  wancfg_get_brdaddr (wcfg_t *, struct sbe_brd_addr *);
525     extern int  wancfg_get_brdinfo (wcfg_t *, struct sbe_brd_info *);
526     extern int  wancfg_get_card (wcfg_t *, struct sbecom_card_param *);
527     extern int  wancfg_get_card_chan_stats (wcfg_t *, struct sbecom_chan_stats *);
528     extern int  wancfg_get_card_sn (wcfg_t *);
529     extern int  wancfg_get_card_stats (wcfg_t *, struct temux_card_stats *);
530     extern int  wancfg_get_chan (wcfg_t *, int, struct sbecom_chan_param *);
531     extern int  wancfg_get_chan_stats (wcfg_t *, int, struct sbecom_chan_stats *);
532     extern int  wancfg_get_drvinfo (wcfg_t *, int, struct sbe_drv_info *);
533     extern int  wancfg_get_framer (wcfg_t *, int, struct sbecom_framer_param *);
534     extern int  wancfg_get_iid (wcfg_t *, int, struct sbe_iid_info *);
535     extern int  wancfg_get_sn (wcfg_t *, unsigned int *);
536     extern int  wancfg_read (wcfg_t *, int, struct sbecom_wrt_vec *);
537     extern int  wancfg_reset_device (wcfg_t *, int);
538     extern int  wancfg_set_card (wcfg_t *, struct sbecom_card_param *);
539     extern int  wancfg_set_chan (wcfg_t *, int, struct sbecom_chan_param *);
540     extern int  wancfg_set_framer (wcfg_t *, int, struct sbecom_framer_param *);
541     extern int  wancfg_set_loglevel (wcfg_t *, uint);
542     extern int  wancfg_write (wcfg_t *, int, struct sbecom_wrt_vec *);
543 
544 #ifdef NOT_YET_COMMON
545     extern int  wancfg_get_tsioc (wcfg_t *, struct wanc1t3_ts_hdr *, struct wanc1t3_ts_param *);
546     extern int  wancfg_set_tsioc (wcfg_t *, struct wanc1t3_ts_param *);
547 #endif
548 
549 #endif                          /*** _INC_LIBSBEW_H_ ***/
550