1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Lochnagar2 register definitions 4 * 5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 * 8 * Author: Charles Keepax <ckeepax@opensource.cirrus.com> 9 */ 10 11 #ifndef LOCHNAGAR2_REGISTERS_H 12 #define LOCHNAGAR2_REGISTERS_H 13 14 /* Register Addresses */ 15 #define LOCHNAGAR2_CDC_AIF1_CTRL 0x000D 16 #define LOCHNAGAR2_CDC_AIF2_CTRL 0x000E 17 #define LOCHNAGAR2_CDC_AIF3_CTRL 0x000F 18 #define LOCHNAGAR2_DSP_AIF1_CTRL 0x0010 19 #define LOCHNAGAR2_DSP_AIF2_CTRL 0x0011 20 #define LOCHNAGAR2_PSIA1_CTRL 0x0012 21 #define LOCHNAGAR2_PSIA2_CTRL 0x0013 22 #define LOCHNAGAR2_GF_AIF3_CTRL 0x0014 23 #define LOCHNAGAR2_GF_AIF4_CTRL 0x0015 24 #define LOCHNAGAR2_GF_AIF1_CTRL 0x0016 25 #define LOCHNAGAR2_GF_AIF2_CTRL 0x0017 26 #define LOCHNAGAR2_SPDIF_AIF_CTRL 0x0018 27 #define LOCHNAGAR2_USB_AIF1_CTRL 0x0019 28 #define LOCHNAGAR2_USB_AIF2_CTRL 0x001A 29 #define LOCHNAGAR2_ADAT_AIF_CTRL 0x001B 30 #define LOCHNAGAR2_CDC_MCLK1_CTRL 0x001E 31 #define LOCHNAGAR2_CDC_MCLK2_CTRL 0x001F 32 #define LOCHNAGAR2_DSP_CLKIN_CTRL 0x0020 33 #define LOCHNAGAR2_PSIA1_MCLK_CTRL 0x0021 34 #define LOCHNAGAR2_PSIA2_MCLK_CTRL 0x0022 35 #define LOCHNAGAR2_SPDIF_MCLK_CTRL 0x0023 36 #define LOCHNAGAR2_GF_CLKOUT1_CTRL 0x0024 37 #define LOCHNAGAR2_GF_CLKOUT2_CTRL 0x0025 38 #define LOCHNAGAR2_ADAT_MCLK_CTRL 0x0026 39 #define LOCHNAGAR2_SOUNDCARD_MCLK_CTRL 0x0027 40 #define LOCHNAGAR2_GPIO_FPGA_GPIO1 0x0031 41 #define LOCHNAGAR2_GPIO_FPGA_GPIO2 0x0032 42 #define LOCHNAGAR2_GPIO_FPGA_GPIO3 0x0033 43 #define LOCHNAGAR2_GPIO_FPGA_GPIO4 0x0034 44 #define LOCHNAGAR2_GPIO_FPGA_GPIO5 0x0035 45 #define LOCHNAGAR2_GPIO_FPGA_GPIO6 0x0036 46 #define LOCHNAGAR2_GPIO_CDC_GPIO1 0x0037 47 #define LOCHNAGAR2_GPIO_CDC_GPIO2 0x0038 48 #define LOCHNAGAR2_GPIO_CDC_GPIO3 0x0039 49 #define LOCHNAGAR2_GPIO_CDC_GPIO4 0x003A 50 #define LOCHNAGAR2_GPIO_CDC_GPIO5 0x003B 51 #define LOCHNAGAR2_GPIO_CDC_GPIO6 0x003C 52 #define LOCHNAGAR2_GPIO_CDC_GPIO7 0x003D 53 #define LOCHNAGAR2_GPIO_CDC_GPIO8 0x003E 54 #define LOCHNAGAR2_GPIO_DSP_GPIO1 0x003F 55 #define LOCHNAGAR2_GPIO_DSP_GPIO2 0x0040 56 #define LOCHNAGAR2_GPIO_DSP_GPIO3 0x0041 57 #define LOCHNAGAR2_GPIO_DSP_GPIO4 0x0042 58 #define LOCHNAGAR2_GPIO_DSP_GPIO5 0x0043 59 #define LOCHNAGAR2_GPIO_DSP_GPIO6 0x0044 60 #define LOCHNAGAR2_GPIO_GF_GPIO2 0x0045 61 #define LOCHNAGAR2_GPIO_GF_GPIO3 0x0046 62 #define LOCHNAGAR2_GPIO_GF_GPIO7 0x0047 63 #define LOCHNAGAR2_GPIO_CDC_AIF1_BCLK 0x0048 64 #define LOCHNAGAR2_GPIO_CDC_AIF1_RXDAT 0x0049 65 #define LOCHNAGAR2_GPIO_CDC_AIF1_LRCLK 0x004A 66 #define LOCHNAGAR2_GPIO_CDC_AIF1_TXDAT 0x004B 67 #define LOCHNAGAR2_GPIO_CDC_AIF2_BCLK 0x004C 68 #define LOCHNAGAR2_GPIO_CDC_AIF2_RXDAT 0x004D 69 #define LOCHNAGAR2_GPIO_CDC_AIF2_LRCLK 0x004E 70 #define LOCHNAGAR2_GPIO_CDC_AIF2_TXDAT 0x004F 71 #define LOCHNAGAR2_GPIO_CDC_AIF3_BCLK 0x0050 72 #define LOCHNAGAR2_GPIO_CDC_AIF3_RXDAT 0x0051 73 #define LOCHNAGAR2_GPIO_CDC_AIF3_LRCLK 0x0052 74 #define LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT 0x0053 75 #define LOCHNAGAR2_GPIO_DSP_AIF1_BCLK 0x0054 76 #define LOCHNAGAR2_GPIO_DSP_AIF1_RXDAT 0x0055 77 #define LOCHNAGAR2_GPIO_DSP_AIF1_LRCLK 0x0056 78 #define LOCHNAGAR2_GPIO_DSP_AIF1_TXDAT 0x0057 79 #define LOCHNAGAR2_GPIO_DSP_AIF2_BCLK 0x0058 80 #define LOCHNAGAR2_GPIO_DSP_AIF2_RXDAT 0x0059 81 #define LOCHNAGAR2_GPIO_DSP_AIF2_LRCLK 0x005A 82 #define LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT 0x005B 83 #define LOCHNAGAR2_GPIO_PSIA1_BCLK 0x005C 84 #define LOCHNAGAR2_GPIO_PSIA1_RXDAT 0x005D 85 #define LOCHNAGAR2_GPIO_PSIA1_LRCLK 0x005E 86 #define LOCHNAGAR2_GPIO_PSIA1_TXDAT 0x005F 87 #define LOCHNAGAR2_GPIO_PSIA2_BCLK 0x0060 88 #define LOCHNAGAR2_GPIO_PSIA2_RXDAT 0x0061 89 #define LOCHNAGAR2_GPIO_PSIA2_LRCLK 0x0062 90 #define LOCHNAGAR2_GPIO_PSIA2_TXDAT 0x0063 91 #define LOCHNAGAR2_GPIO_GF_AIF3_BCLK 0x0064 92 #define LOCHNAGAR2_GPIO_GF_AIF3_RXDAT 0x0065 93 #define LOCHNAGAR2_GPIO_GF_AIF3_LRCLK 0x0066 94 #define LOCHNAGAR2_GPIO_GF_AIF3_TXDAT 0x0067 95 #define LOCHNAGAR2_GPIO_GF_AIF4_BCLK 0x0068 96 #define LOCHNAGAR2_GPIO_GF_AIF4_RXDAT 0x0069 97 #define LOCHNAGAR2_GPIO_GF_AIF4_LRCLK 0x006A 98 #define LOCHNAGAR2_GPIO_GF_AIF4_TXDAT 0x006B 99 #define LOCHNAGAR2_GPIO_GF_AIF1_BCLK 0x006C 100 #define LOCHNAGAR2_GPIO_GF_AIF1_RXDAT 0x006D 101 #define LOCHNAGAR2_GPIO_GF_AIF1_LRCLK 0x006E 102 #define LOCHNAGAR2_GPIO_GF_AIF1_TXDAT 0x006F 103 #define LOCHNAGAR2_GPIO_GF_AIF2_BCLK 0x0070 104 #define LOCHNAGAR2_GPIO_GF_AIF2_RXDAT 0x0071 105 #define LOCHNAGAR2_GPIO_GF_AIF2_LRCLK 0x0072 106 #define LOCHNAGAR2_GPIO_GF_AIF2_TXDAT 0x0073 107 #define LOCHNAGAR2_GPIO_DSP_UART1_RX 0x0074 108 #define LOCHNAGAR2_GPIO_DSP_UART1_TX 0x0075 109 #define LOCHNAGAR2_GPIO_DSP_UART2_RX 0x0076 110 #define LOCHNAGAR2_GPIO_DSP_UART2_TX 0x0077 111 #define LOCHNAGAR2_GPIO_GF_UART2_RX 0x0078 112 #define LOCHNAGAR2_GPIO_GF_UART2_TX 0x0079 113 #define LOCHNAGAR2_GPIO_USB_UART_RX 0x007A 114 #define LOCHNAGAR2_GPIO_CDC_PDMCLK1 0x007C 115 #define LOCHNAGAR2_GPIO_CDC_PDMDAT1 0x007D 116 #define LOCHNAGAR2_GPIO_CDC_PDMCLK2 0x007E 117 #define LOCHNAGAR2_GPIO_CDC_PDMDAT2 0x007F 118 #define LOCHNAGAR2_GPIO_CDC_DMICCLK1 0x0080 119 #define LOCHNAGAR2_GPIO_CDC_DMICDAT1 0x0081 120 #define LOCHNAGAR2_GPIO_CDC_DMICCLK2 0x0082 121 #define LOCHNAGAR2_GPIO_CDC_DMICDAT2 0x0083 122 #define LOCHNAGAR2_GPIO_CDC_DMICCLK3 0x0084 123 #define LOCHNAGAR2_GPIO_CDC_DMICDAT3 0x0085 124 #define LOCHNAGAR2_GPIO_CDC_DMICCLK4 0x0086 125 #define LOCHNAGAR2_GPIO_CDC_DMICDAT4 0x0087 126 #define LOCHNAGAR2_GPIO_DSP_DMICCLK1 0x0088 127 #define LOCHNAGAR2_GPIO_DSP_DMICDAT1 0x0089 128 #define LOCHNAGAR2_GPIO_DSP_DMICCLK2 0x008A 129 #define LOCHNAGAR2_GPIO_DSP_DMICDAT2 0x008B 130 #define LOCHNAGAR2_GPIO_I2C2_SCL 0x008C 131 #define LOCHNAGAR2_GPIO_I2C2_SDA 0x008D 132 #define LOCHNAGAR2_GPIO_I2C3_SCL 0x008E 133 #define LOCHNAGAR2_GPIO_I2C3_SDA 0x008F 134 #define LOCHNAGAR2_GPIO_I2C4_SCL 0x0090 135 #define LOCHNAGAR2_GPIO_I2C4_SDA 0x0091 136 #define LOCHNAGAR2_GPIO_DSP_STANDBY 0x0092 137 #define LOCHNAGAR2_GPIO_CDC_MCLK1 0x0093 138 #define LOCHNAGAR2_GPIO_CDC_MCLK2 0x0094 139 #define LOCHNAGAR2_GPIO_DSP_CLKIN 0x0095 140 #define LOCHNAGAR2_GPIO_PSIA1_MCLK 0x0096 141 #define LOCHNAGAR2_GPIO_PSIA2_MCLK 0x0097 142 #define LOCHNAGAR2_GPIO_GF_GPIO1 0x0098 143 #define LOCHNAGAR2_GPIO_GF_GPIO5 0x0099 144 #define LOCHNAGAR2_GPIO_DSP_GPIO20 0x009A 145 #define LOCHNAGAR2_GPIO_CHANNEL1 0x00B9 146 #define LOCHNAGAR2_GPIO_CHANNEL2 0x00BA 147 #define LOCHNAGAR2_GPIO_CHANNEL3 0x00BB 148 #define LOCHNAGAR2_GPIO_CHANNEL4 0x00BC 149 #define LOCHNAGAR2_GPIO_CHANNEL5 0x00BD 150 #define LOCHNAGAR2_GPIO_CHANNEL6 0x00BE 151 #define LOCHNAGAR2_GPIO_CHANNEL7 0x00BF 152 #define LOCHNAGAR2_GPIO_CHANNEL8 0x00C0 153 #define LOCHNAGAR2_GPIO_CHANNEL9 0x00C1 154 #define LOCHNAGAR2_GPIO_CHANNEL10 0x00C2 155 #define LOCHNAGAR2_GPIO_CHANNEL11 0x00C3 156 #define LOCHNAGAR2_GPIO_CHANNEL12 0x00C4 157 #define LOCHNAGAR2_GPIO_CHANNEL13 0x00C5 158 #define LOCHNAGAR2_GPIO_CHANNEL14 0x00C6 159 #define LOCHNAGAR2_GPIO_CHANNEL15 0x00C7 160 #define LOCHNAGAR2_GPIO_CHANNEL16 0x00C8 161 #define LOCHNAGAR2_MINICARD_RESETS 0x00DF 162 #define LOCHNAGAR2_ANALOGUE_PATH_CTRL1 0x00E3 163 #define LOCHNAGAR2_ANALOGUE_PATH_CTRL2 0x00E4 164 #define LOCHNAGAR2_COMMS_CTRL4 0x00F0 165 #define LOCHNAGAR2_SPDIF_CTRL 0x00FE 166 #define LOCHNAGAR2_IMON_CTRL1 0x0108 167 #define LOCHNAGAR2_IMON_CTRL2 0x0109 168 #define LOCHNAGAR2_IMON_CTRL3 0x010A 169 #define LOCHNAGAR2_IMON_CTRL4 0x010B 170 #define LOCHNAGAR2_IMON_DATA1 0x010C 171 #define LOCHNAGAR2_IMON_DATA2 0x010D 172 #define LOCHNAGAR2_POWER_CTRL 0x0116 173 #define LOCHNAGAR2_MICVDD_CTRL1 0x0119 174 #define LOCHNAGAR2_MICVDD_CTRL2 0x011B 175 #define LOCHNAGAR2_VDDCORE_CDC_CTRL1 0x011E 176 #define LOCHNAGAR2_VDDCORE_CDC_CTRL2 0x0120 177 #define LOCHNAGAR2_SOUNDCARD_AIF_CTRL 0x0180 178 179 /* (0x000D-0x001B, 0x0180) CDC_AIF1_CTRL - SOUNCARD_AIF_CTRL */ 180 #define LOCHNAGAR2_AIF_ENA_MASK 0x8000 181 #define LOCHNAGAR2_AIF_ENA_SHIFT 15 182 #define LOCHNAGAR2_AIF_LRCLK_DIR_MASK 0x4000 183 #define LOCHNAGAR2_AIF_LRCLK_DIR_SHIFT 14 184 #define LOCHNAGAR2_AIF_BCLK_DIR_MASK 0x2000 185 #define LOCHNAGAR2_AIF_BCLK_DIR_SHIFT 13 186 #define LOCHNAGAR2_AIF_SRC_MASK 0x00FF 187 #define LOCHNAGAR2_AIF_SRC_SHIFT 0 188 189 /* (0x001E - 0x0027) CDC_MCLK1_CTRL - SOUNDCARD_MCLK_CTRL */ 190 #define LOCHNAGAR2_CLK_ENA_MASK 0x8000 191 #define LOCHNAGAR2_CLK_ENA_SHIFT 15 192 #define LOCHNAGAR2_CLK_SRC_MASK 0x00FF 193 #define LOCHNAGAR2_CLK_SRC_SHIFT 0 194 195 /* (0x0031 - 0x009A) GPIO_FPGA_GPIO1 - GPIO_DSP_GPIO20 */ 196 #define LOCHNAGAR2_GPIO_SRC_MASK 0x00FF 197 #define LOCHNAGAR2_GPIO_SRC_SHIFT 0 198 199 /* (0x00B9 - 0x00C8) GPIO_CHANNEL1 - GPIO_CHANNEL16 */ 200 #define LOCHNAGAR2_GPIO_CHANNEL_STS_MASK 0x8000 201 #define LOCHNAGAR2_GPIO_CHANNEL_STS_SHIFT 15 202 #define LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK 0x00FF 203 #define LOCHNAGAR2_GPIO_CHANNEL_SRC_SHIFT 0 204 205 /* (0x00DF) MINICARD_RESETS */ 206 #define LOCHNAGAR2_DSP_RESET_MASK 0x0002 207 #define LOCHNAGAR2_DSP_RESET_SHIFT 1 208 #define LOCHNAGAR2_CDC_RESET_MASK 0x0001 209 #define LOCHNAGAR2_CDC_RESET_SHIFT 0 210 211 /* (0x00E3) ANALOGUE_PATH_CTRL1 */ 212 #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK 0x8000 213 #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_SHIFT 15 214 #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK 0x4000 215 #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_SHIFT 14 216 217 /* (0x00E4) ANALOGUE_PATH_CTRL2 */ 218 #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK 0x0080 219 #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_SHIFT 7 220 #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK 0x0040 221 #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_SHIFT 6 222 #define LOCHNAGAR2_P2_MICBIAS_SRC_MASK 0x0038 223 #define LOCHNAGAR2_P2_MICBIAS_SRC_SHIFT 3 224 #define LOCHNAGAR2_P1_MICBIAS_SRC_MASK 0x0007 225 #define LOCHNAGAR2_P1_MICBIAS_SRC_SHIFT 0 226 227 /* (0x00F0) COMMS_CTRL4 */ 228 #define LOCHNAGAR2_CDC_CIF1MODE_MASK 0x0001 229 #define LOCHNAGAR2_CDC_CIF1MODE_SHIFT 0 230 231 /* (0x00FE) SPDIF_CTRL */ 232 #define LOCHNAGAR2_SPDIF_HWMODE_MASK 0x0008 233 #define LOCHNAGAR2_SPDIF_HWMODE_SHIFT 3 234 #define LOCHNAGAR2_SPDIF_RESET_MASK 0x0001 235 #define LOCHNAGAR2_SPDIF_RESET_SHIFT 0 236 237 /* (0x0108) IMON_CTRL1 */ 238 #define LOCHNAGAR2_IMON_ENA_MASK 0x8000 239 #define LOCHNAGAR2_IMON_ENA_SHIFT 15 240 #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_MASK 0x03FC 241 #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_SHIFT 2 242 #define LOCHNAGAR2_IMON_MODE_SEL_MASK 0x0003 243 #define LOCHNAGAR2_IMON_MODE_SEL_SHIFT 0 244 245 /* (0x0109) IMON_CTRL2 */ 246 #define LOCHNAGAR2_IMON_FSR_MASK 0x03FF 247 #define LOCHNAGAR2_IMON_FSR_SHIFT 0 248 249 /* (0x010A) IMON_CTRL3 */ 250 #define LOCHNAGAR2_IMON_DONE_MASK 0x0004 251 #define LOCHNAGAR2_IMON_DONE_SHIFT 2 252 #define LOCHNAGAR2_IMON_CONFIGURE_MASK 0x0002 253 #define LOCHNAGAR2_IMON_CONFIGURE_SHIFT 1 254 #define LOCHNAGAR2_IMON_MEASURE_MASK 0x0001 255 #define LOCHNAGAR2_IMON_MEASURE_SHIFT 0 256 257 /* (0x010B) IMON_CTRL4 */ 258 #define LOCHNAGAR2_IMON_DATA_REQ_MASK 0x0080 259 #define LOCHNAGAR2_IMON_DATA_REQ_SHIFT 7 260 #define LOCHNAGAR2_IMON_CH_SEL_MASK 0x0070 261 #define LOCHNAGAR2_IMON_CH_SEL_SHIFT 4 262 #define LOCHNAGAR2_IMON_DATA_RDY_MASK 0x0008 263 #define LOCHNAGAR2_IMON_DATA_RDY_SHIFT 3 264 #define LOCHNAGAR2_IMON_CH_SRC_MASK 0x0007 265 #define LOCHNAGAR2_IMON_CH_SRC_SHIFT 0 266 267 /* (0x010C, 0x010D) IMON_DATA1, IMON_DATA2 */ 268 #define LOCHNAGAR2_IMON_DATA_MASK 0xFFFF 269 #define LOCHNAGAR2_IMON_DATA_SHIFT 0 270 271 /* (0x0116) POWER_CTRL */ 272 #define LOCHNAGAR2_PWR_ENA_MASK 0x0001 273 #define LOCHNAGAR2_PWR_ENA_SHIFT 0 274 275 /* (0x0119) MICVDD_CTRL1 */ 276 #define LOCHNAGAR2_MICVDD_REG_ENA_MASK 0x8000 277 #define LOCHNAGAR2_MICVDD_REG_ENA_SHIFT 15 278 279 /* (0x011B) MICVDD_CTRL2 */ 280 #define LOCHNAGAR2_MICVDD_VSEL_MASK 0x001F 281 #define LOCHNAGAR2_MICVDD_VSEL_SHIFT 0 282 283 /* (0x011E) VDDCORE_CDC_CTRL1 */ 284 #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_MASK 0x8000 285 #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_SHIFT 15 286 287 /* (0x0120) VDDCORE_CDC_CTRL2 */ 288 #define LOCHNAGAR2_VDDCORE_CDC_VSEL_MASK 0x007F 289 #define LOCHNAGAR2_VDDCORE_CDC_VSEL_SHIFT 0 290 291 #endif 292