1 /* Copyright(c) 2000, Compaq Computer Corporation 2 * Fibre Channel Host Bus Adapter 64-bit, 66MHz PCI 3 * Originally developed and tested on: 4 * (front): [chip] Tachyon TS HPFC-5166A/1.2 L2C1090 ... 5 * SP# P225CXCBFIEL6T, Rev XC 6 * SP# 161290-001, Rev XD 7 * (back): Board No. 010008-001 A/W Rev X5, FAB REV X5 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2, or (at your option) any 12 * later version. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * Written by Don Zimmerman 19 */ 20 21 #ifndef CPQFCTSSTRUCTS_H 22 #define CPQFCTSSTRUCTS_H 23 24 #include <linux/timer.h> // timer declaration in our host data 25 #include <linux/tqueue.h> // task queue sched 26 #include <asm/atomic.h> 27 #include "cpqfcTSioctl.h" 28 29 /* FIXME - this is crap */ 30 #define DbgDelay(secs) { int wait_time; printk( " DbgDelay %ds ", secs); \ 31 for( wait_time=jiffies + (secs*HZ); \ 32 time_before(jiffies, wait_time) ;) ; } 33 34 #define CPQFCTS_DRIVER_VER(maj,min,submin) ((maj<<16)|(min<<8)|(submin)) 35 /* don't forget to also change MODULE_DESCRIPTION in cpqfcTSinit.c */ 36 #define VER_MAJOR 2 37 #define VER_MINOR 1 38 #define VER_SUBMINOR 2 39 40 /* 41 * Macros for kernel (esp. SMP) tracing using a PCI analyzer 42 * (e.g. x86). 43 */ 44 45 //#define PCI_KERNEL_TRACE 46 #ifdef PCI_KERNEL_TRACE 47 #define PCI_TRACE(x) inl( fcChip->Registers.IOBaseL +x); 48 #define PCI_TRACEO(x,y) outl( x, (fcChip->Registers.IOBaseL +y)); 49 #else 50 51 #define PCI_TRACE(x) 52 #define PCI_TRACEO(x,y) 53 #endif 54 55 56 //#define DEBUG_CMND 1 // debug output for Linux Scsi CDBs 57 //#define DUMMYCMND_DBG 1 58 59 //#define DEBUG_CPQFCTS 1 60 //#undef DEBUG_CPQFCTS 61 #ifdef DEBUG_CPQFCTS 62 #define ENTER(x) printk("cpqfcts : entering %s()\n", x); 63 #define LEAVE(x) printk("cpqfcts : leaving %s()\n", x); 64 #define DEBUG(x) x 65 #else 66 #define ENTER(x) 67 #define LEAVE(x) 68 #define DEBUG(x) 69 #endif /* DEBUG_CPQFCTS */ 70 71 //#define DEBUG_CPQFCTS_PCI 1 72 //#undef DEBUG_CPQFCTS_PCI 73 #if DEBUG_CPQFCTS_PCI 74 #define DEBUG_PCI(x) x 75 #else 76 #define DEBUG_PCI(x) 77 #endif /* DEBUG_CPQFCTS_PCI */ 78 79 #define STACHLITE66_TS12 "Compaq FibreChannel HBA Tachyon TS HPFC-5166A/1.2" 80 #define STACHLITE66_TS13 "Compaq FibreChannel HBA Tachyon TS HPFC-5166A/1.3" 81 #define STACHLITE_UNKNOWN "Compaq FibreChannel HBA Tachyon Chip/Board Ver??" 82 #define SAGILENT_XL2_21 "Agilent FC HBA, Tachyon XL2 HPFC-5200B/2.1" 83 84 // PDA is Peripheral Device Address, VSA is Volume Set Addressing 85 // Linux SCSI parameters 86 #define CPQFCTS_MAX_TARGET_ID 64 87 88 // Note, changing CPQFCTS_MAX_LUN to less than 32 (e.g, 8) will result in 89 // strange behavior if a box with more than, e.g. 8, is on the loop. 90 #define CPQFCTS_MAX_LUN 32 // The RA-4x00 supports 32 (Linux SCSI supports 8) 91 #define CPQFCTS_MAX_CHANNEL 0 // One FC port on cpqfcTS HBA 92 93 #define CPQFCTS_CMD_PER_LUN 15 // power of 2 -1, must be >0 94 #define CPQFCTS_REQ_QUEUE_LEN (TACH_SEST_LEN/2) // must be < TACH_SEST_LEN 95 96 /* FIMXME - these are crpa too */ 97 #define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s)) 98 #ifndef DECLARE_MUTEX_LOCKED 99 #define DECLARE_MUTEX_LOCKED(sem) struct semaphore sem = MUTEX_LOCKED 100 #endif 101 102 #define DEV_NAME "cpqfcTS" 103 104 struct SupportedPCIcards { 105 __u16 vendor_id; 106 __u16 device_id; 107 }; 108 109 /* 110 * nn:nn denotes bit field 111 * TachyonHeader struct def. 112 * the fields shared with ODB 113 * need to have same value 114 */ 115 116 /* 117 * macro for FC-PH reject codes 118 * payload format for LS_RJT (FC payloads are big endian): 119 * byte 0 1 2 3 (MSB) 120 * DWORD 0 01 00 00 00 121 * DWORD 1 resvd code expl. vendor 122 */ 123 #define LS_RJT_REASON( code, expl) (( code<<8) | (expl <<16)) 124 125 #define TachLiteSTATUS 0x12 126 127 /* 128 * Fibre Channel EXCHANGE status codes for Tachyon chips/ driver software 129 * 32-bit ERROR word defines 130 */ 131 #define INVALID_ARGS 0x1 132 #define LNKDWN_OSLS 0x2 133 #define LNKDWN_LASER 0x4 134 #define OUTQUE_FULL 0x8 135 #define DRIVERQ_FULL 0x10 136 #define SEST_FULL 0x20 137 #define BAD_ALPA 0x40 138 #define OVERFLOW 0x80 // inbound CM 139 #define COUNT_ERROR 0x100 // inbound CM 140 #define LINKFAIL_RX 0x200 // inbound CM 141 #define ABORTSEQ_NOTIFY 0x400 // outbound CM 142 #define LINKFAIL_TX 0x800 // outbound CM 143 #define HOSTPROG_ERR 0x1000 // outbound CM 144 #define FRAME_TO 0x2000 // outbound CM 145 #define INV_ENTRY 0x4000 // outbound CM 146 #define SESTPROG_ERR 0x8000 // outbound CM 147 #define OUTBOUND_TIMEOUT 0x10000L // timeout waiting for Tachyon outbound CM 148 #define INITIATOR_ABORT 0x20000L // initiator exchange timeout or O/S ABORT 149 #define MEMPOOL_FAIL 0x40000L // O/S memory pool allocation failed 150 #define FC2_TIMEOUT 0x80000L // driver timeout for lost frames 151 #define TARGET_ABORT 0x100000L // ABTS received from FC port 152 #define EXCHANGE_QUEUED 0x200000L // e.g. Link State was LDn on fcStart 153 #define PORTID_CHANGED 0x400000L // fc Port address changed 154 #define DEVICE_REMOVED 0x800000L // fc Port address changed 155 /* 156 * Several error scenarios result in SEST Exchange frames 157 * unexpectedly arriving in the SFQ 158 */ 159 #define SFQ_FRAME 0x1000000L // SFQ frames from open Exchange 160 161 /* 162 * Maximum number of Host Bus Adapters (HBA) / controllers supported 163 * only important for mem allocation dimensions - increase as necessary 164 */ 165 166 #define MAX_ADAPTERS 8 167 #define MAX_RX_PAYLOAD 1024 // hardware dependent max frame payload 168 169 /* 170 * Tach header struct defines 171 */ 172 173 #define SOFi3 0x7 174 #define SOFf 0x8 175 #define SOFn3 0xB 176 #define EOFn 0x5 177 #define EOFt 0x6 178 179 // FCP R_CTL defines 180 #define FCP_CMND 0x6 181 #define FCP_XFER_RDY 0x5 182 #define FCP_RSP 0x7 183 #define FCP_RESPONSE 0x777 // (arbitrary #) 184 #define NEED_FCP_RSP 0x77 // (arbitrary #) 185 #define FCP_DATA 0x1 186 187 #define RESET_TACH 0x100 // Reset Tachyon/TachLite 188 #define SCSI_IWE 0x2000 // initiator write entry (for SEST) 189 #define SCSI_IRE 0x3000 // initiator read entry (for SEST) 190 #define SCSI_TRE 0x400 // target read entry (for SEST) 191 #define SCSI_TWE 0x500 // target write entry (for SEST) 192 #define TOGGLE_LASER 0x800 193 #define LIP 0x900 194 #define CLEAR_FCPORTS 99 // (arbitrary #) free mem for Logged in ports 195 #define FMINIT 0x707 // (arbitrary) for Frame Manager Init command 196 197 /* 198 * BLS == Basic Link Service 199 * ELS == Extended Link Service 200 */ 201 202 #define BLS_NOP 4 203 #define BLS_ABTS 0x10 // FC-PH Basic Link Service Abort Sequence 204 #define BLS_ABTS_ACC 0x100 // FC-PH Basic Link Service Abort Sequence Accept 205 #define BLS_ABTS_RJT 0x101 // FC-PH Basic Link Service Abort Sequence Reject 206 #define ELS_PLOGI 0x03 // FC-PH Port Login (arbitrary assign) 207 #define ELS_SCR 0x70 // (arb assign) State Change Registration (Fabric) 208 #define FCS_NSR 0x72 // (arb assign) Name Service Request (Fabric) 209 #define ELS_FLOGI 0x44 // (arb assign) Fabric Login 210 #define ELS_FDISC 0x41 // (arb assign) Fabric Discovery (Login) 211 #define ELS_PDISC 0x50 // FC-PH2 Port Discovery 212 #define ELS_ABTX 0x06 // FC-PH Abort Exchange 213 #define ELS_LOGO 0x05 // FC-PH Port Logout 214 #define ELS_PRLI 0x20 // FCP-SCSI Process Login 215 #define ELS_PRLO 0x21 // FCP-SCSI Process Logout 216 #define ELS_LOGO_ACC 0x07 // {FC-PH} Port Logout Accept 217 #define ELS_PLOGI_ACC 0x08 // {FC-PH} Port Login Accept 218 #define ELS_ACC 0x18 // {FC-PH} (generic) ACCept 219 #define ELS_PRLI_ACC 0x22 // {FCP-SCSI} Process Login Accept 220 #define ELS_RJT 0x1000000 221 #define SCSI_REPORT_LUNS 0x0A0 222 #define FCP_TARGET_RESET 0x200 223 224 #define ELS_LILP_FRAME 0x00000711 // 1st payload word of LILP frame 225 226 #define SFQ_UNASSISTED_FCP 1 // ICM, DWord3, "Type" unassisted FCP 227 #define SFQ_UNKNOWN 0x31 // (arbitrary) ICM, DWord3, "Type" unknown 228 229 /* 230 * These "LINK" bits refer to loop or non-loop 231 */ 232 #define LINKACTIVE 0x2 // fcLinkQ type - LINK UP Tachyon FM 'Lup' bit set 233 #define LINKDOWN 0xf2 // fcLinkQ type - LINK DOWN Tachyon FM 'Ldn' bit set 234 235 //#define VOLUME_SET_ADDRESSING 1 // "channel" or "bus" 1 236 237 typedef struct // 32 bytes hdr ONLY (e.g. FCP_DATA buffer for SEST) 238 { 239 __u32 reserved; // dword 0 (don't use) 240 __u32 sof_eof; 241 __u32 d_id; // dword 2 - 31:24 R_CTL, 23:0 D_ID 242 __u32 s_id; // dword 3 - 31:24 CS_CTL, 23:0 S_ID 243 __u32 f_ctl; // dword 4 - 31:24 Type, 23:0 F_CTL 244 __u32 seq_cnt; // dword 5 - 31:24 SEQ_ID, 23:16 DF_CTL, 15:0 SEQ_CNT 245 __u32 ox_rx_id; // dword 6 - 31:16 OX_ID, 15:0 RX_ID 246 __u32 ro; // dword 7 - relative offset 247 } TachFCHDR; 248 249 // NOTE!! the following struct MUST be 64 bytes. 250 typedef struct // 32 bytes hdr + 32 bytes payload 251 { 252 __u32 reserved; // dword 0 (don't use - must clear to 0) 253 __u32 sof_eof; // dword 1 - 31:24 SOF:EOF, UAM,CLS, LCr, TFV, TimeStamp 254 __u32 d_id; // dword 2 - 31:24 R_CTL, 23:0 D_ID 255 __u32 s_id; // dword 3 - 31:24 CS_CTL, 23:0 S_ID 256 __u32 f_ctl; // dword 4 - 31:24 Type, 23:0 F_CTL 257 __u32 seq_cnt; // dword 5 - 31:24 SEQ_ID, 23:16 DF_CTL, 15:0 SEQ_CNT 258 __u32 ox_rx_id; // dword 6 - 31:16 OX_ID, 15:0 RX_ID 259 __u32 ro; // dword 7 - relative offset 260 //--------- 261 __u32 pl[8]; // dwords 8-15 frame data payload 262 } TachFCHDR_CMND; 263 264 265 typedef struct // 32 bytes hdr + 120 bytes payload 266 { 267 __u32 reserved; // dword 0 (don't use - must clear to 0) 268 __u32 sof_eof; // dword 1 - 31:24 SOF:EOF, UAM,CLS, LCr, TFV, TimeStamp 269 __u32 d_id; // dword 2 - 31:24 R_CTL, 23:0 D_ID 270 __u32 s_id; // dword 3 - 31:24 CS_CTL, 23:0 S_ID 271 __u32 f_ctl; // dword 4 - 31:24 Type, 23:0 F_CTL 272 __u32 seq_cnt; // dword 5 - 31:24 SEQ_ID, 23:16 DF_CTL, 15:0 SEQ_CNT 273 __u32 ox_rx_id; // dword 6 - 31:16 OX_ID, 15:0 RX_ID 274 __u32 ro; // dword 7 - relative offset 275 //--------- 276 __u32 pl[30]; // largest necessary payload (for LOGIN cmnds) 277 } TachFCHDR_GCMND; 278 279 typedef struct // 32 bytes hdr + 64 bytes payload 280 { 281 __u32 reserved; // dword 0 (don't use) 282 __u32 sof_eof; 283 __u32 d_id; // dword 2 - 31:24 R_CTL, 23:0 D_ID 284 __u32 s_id; // dword 3 - 31:24 CS_CTL, 23:0 S_ID 285 __u32 f_ctl; // dword 4 - 31:24 Type, 23:0 F_CTL 286 __u32 seq_cnt; // dword 5 - 31:24 SEQ_ID, 23:16 DF_CTL, 15:0 SEQ_CNT 287 __u32 ox_rx_id; // dword 6 - 31:16 OX_ID, 15:0 RX_ID 288 __u32 ro; // dword 7 - relative offset 289 //--------- 290 __u32 pl[18]; // payload for FCP-RSP (response buffer) RA-4x00 is 72bytes 291 } TachFCHDR_RSP; 292 293 294 295 296 297 298 // Inbound Message Queue structures... 299 typedef struct // each entry 8 words (32 bytes) 300 { 301 __u32 type; // IMQ completion message types 302 __u32 word[7]; // remainder of structure 303 // interpreted by IMQ type 304 } TachyonIMQE; 305 306 307 // Queues for TachLite not in original Tachyon 308 // ERQ - Exchange Request Queue (for outbound commands) 309 // SFQ - Single Frame Queue (for incoming frames) 310 311 // Define Tachyon Outbound Command Que 312 // (Since many Tachyon registers are Read 313 // only, maintain copies for debugging) 314 // most Tach ques need power-of-2 sizes, 315 // where registers are loaded with po2 -1 316 #define TACH_SEST_LEN 512 // TachLite SEST 317 318 #define ELS_EXCHANGES 64 // e.g. PLOGI, RSCN, ... 319 // define the total number of outstanding (simultaneous) exchanges 320 #define TACH_MAX_XID (TACH_SEST_LEN + ELS_EXCHANGES) // ELS exchanges 321 322 #define ERQ_LEN 128 // power of 2, max 4096 323 324 // Inbound Message Queue structures... 325 #define IMQ_LEN 512 // minimum 4 entries [(power of 2) - 1] 326 typedef struct // 8 words - 32 bytes 327 { 328 TachyonIMQE QEntry[IMQ_LEN]; 329 __u32 producerIndex; // IMQ Producer Index register 330 // @32 byte align 331 __u32 consumerIndex; // Consumer Index register (in Tachyon) 332 __u32 length; // Length register 333 __u32 base; 334 } TachyonIMQ; // @ 32 * IMQ_LEN align 335 336 337 338 typedef struct // inbound completion message 339 { 340 __u32 Type; 341 __u32 Index; 342 __u32 TransferLength; 343 } TachyonInbCM; 344 345 346 347 // arbitrary numeric tags for TL structures 348 #define TL_FCHS 1 // TachLite Fibre Channel Header Structure 349 #define TL_IWE 2 // initiator write entry (for SEST) 350 #define TL_TWE 3 // target write entry (for SEST) 351 #define TL_IRE 4 // initiator read entry (for SEST) 352 #define TL_TRE 5 // target read entry (for SEST) 353 #define TL_IRB 6 // I/O request block 354 355 // for INCOMING frames 356 #define SFQ_LEN 32 // minimum 32 entries, max 4096 357 358 typedef struct // Single Frame Que 359 { 360 TachFCHDR_CMND QEntry[SFQ_LEN]; // must be 64 bytes!! 361 __u32 producerIndex; // IMQ Producer Index register 362 // @32 byte align 363 __u32 consumerIndex; // Consumer Index register (in Tachyon) 364 __u32 length; // Length register 365 __u32 base; 366 } TachLiteSFQ; 367 368 369 typedef struct // I/O Request Block flags 370 { 371 __u8 BRD:1; 372 __u8:1; // reserved 373 __u8 SFA:1; 374 __u8 DNC:1; 375 __u8 DIN:1; 376 __u8 DCM:1; 377 __u8 CTS:1; 378 __u8 SBV:1; // IRB entry valid - IRB'B' only 379 } IRBflags; 380 381 typedef struct // I/O Request Block 382 { // Request 'A' 383 __u32 Req_A_SFS_Len; // total frame len (hdr + payload), min 32 384 __u32 Req_A_SFS_Addr; // 32-bit pointer to FCHS struct (to be sent) 385 __u32 Req_A_SFS_D_ID; // 24-bit FC destination (i.e. 8 bit al_pa) 386 __u32 Req_A_Trans_ID; // X_ID (OX_ID or RX_ID) and/or Index in SEST 387 // Request 'B' 388 __u32 Req_B_SFS_Len; // total frame len (hdr + payload), min 32 389 __u32 Req_B_SFS_Addr; // 32-bit pointer to FCHS struct (to be sent) 390 __u32 Req_B_SFS_D_ID; // 24-bit FC destination (i.e. 8 bit al_pa) 391 __u32 Req_B_Trans_ID; // X_ID (OX_ID or RX_ID) and/or Index in SEST 392 } TachLiteIRB; 393 394 395 typedef struct // TachLite placeholder for IRBs 396 { // aligned @sizeof(ERQ) for TachLite 397 // MAX commands is sum of SEST len and ERQ 398 // we know that each SEST entry requires an 399 // IRB (ERQ) entry; in addition, we provide 400 // ERQ_LEN 401 TachLiteIRB QEntry[ERQ_LEN]; // Base register; entries 32 bytes ea. 402 __u32 consumerIndex; // Consumer Index register 403 __u32 producerIndex; // ERQ Producer Index register 404 __u32 length; // Length register 405 __u32 base; // copy of base ptr for debug 406 // struct is sized for largest expected cmnd (LOGIN) 407 } TachLiteERQ; 408 409 // for now, just 32 bit DMA, eventually 40something, with code changes 410 #define CPQFCTS_DMA_MASK ((unsigned long) (0x00000000FFFFFFFF)) 411 412 #define TL_MAX_SG_ELEM_LEN 0x7ffff // Max buffer length a single S/G entry 413 // may represent (a hardware limitation). The 414 // only reason to ever change this is if you 415 // want to exercise very-hard-to-reach code in 416 // cpqfcTSworker.c:build_SEST_sglist(). 417 418 #define TL_DANGER_SGPAGES 7 // arbitrary high water mark for # of S/G pages 419 // we must exceed to elicit a warning indicative 420 // of EXTREMELY large data transfers or 421 // EXTREME memory fragmentation. 422 // (means we just used up 2048 S/G elements, 423 // Never seen this is real life, only in 424 // testing with tricked up driver.) 425 426 #define TL_EXT_SG_PAGE_COUNT 256 // Number of Extended Scatter/Gather a/l PAIRS 427 // Tachyon register (IOBaseU 0x68) 428 // power-of-2 value ONLY! 4 min, 256 max 429 430 // byte len is #Pairs * 2 __u32/Pair * 4 bytes/__u32 431 #define TL_EXT_SG_PAGE_BYTELEN (TL_EXT_SG_PAGE_COUNT *2 *4) 432 433 434 435 // SEST entry types: IWE, IRE, TWE, TRE 436 typedef struct { 437 __u32 Hdr_Len; 438 __u32 Hdr_Addr; 439 __u32 RSP_Len; 440 __u32 RSP_Addr; 441 __u32 Buff_Off; 442 #define USES_EXTENDED_SGLIST(this_sest, x_ID) \ 443 (!((this_sest)->u[ x_ID ].IWE.Buff_Off & 0x80000000)) 444 __u32 Link; 445 __u32 RX_ID; 446 __u32 Data_Len; 447 __u32 Exp_RO; 448 __u32 Exp_Byte_Cnt; 449 // --- extended/local Gather Len/Address pairs 450 __u32 GLen1; 451 __u32 GAddr1; 452 __u32 GLen2; 453 __u32 GAddr2; 454 __u32 GLen3; 455 __u32 GAddr3; 456 } TachLiteIWE; 457 458 459 typedef struct { 460 __u32 Seq_Accum; 461 __u32 reserved; // must clear to 0 462 __u32 RSP_Len; 463 __u32 RSP_Addr; 464 __u32 Buff_Off; 465 __u32 Buff_Index; // __u32 5 466 __u32 Exp_RO; 467 __u32 Byte_Count; 468 __u32 reserved_; // __u32 8 469 __u32 Exp_Byte_Cnt; 470 // --- extended/local Scatter Len/Address pairs 471 __u32 SLen1; 472 __u32 SAddr1; 473 __u32 SLen2; 474 __u32 SAddr2; 475 __u32 SLen3; 476 __u32 SAddr3; 477 } TachLiteIRE; 478 479 480 typedef struct // Target Write Entry 481 { 482 __u32 Seq_Accum; // dword 0 483 __u32 reserved; // dword 1 must clear to 0 484 __u32 Remote_Node_ID; 485 __u32 reserved1; // dword 3 must clear to 0 486 __u32 Buff_Off; 487 __u32 Buff_Index; // __u32 5 488 __u32 Exp_RO; 489 __u32 Byte_Count; 490 __u32 reserved_; // __u32 8 491 __u32 Exp_Byte_Cnt; 492 // --- extended/local Scatter Len/Address pairs 493 __u32 SLen1; 494 __u32 SAddr1; 495 __u32 SLen2; 496 __u32 SAddr2; 497 __u32 SLen3; 498 __u32 SAddr3; 499 } TachLiteTWE; 500 501 typedef struct { 502 __u32 Hdr_Len; 503 __u32 Hdr_Addr; 504 __u32 RSP_Len; // DWord 2 505 __u32 RSP_Addr; 506 __u32 Buff_Off; 507 __u32 Buff_Index; // DWord 5 508 __u32 reserved; 509 __u32 Data_Len; 510 __u32 reserved_; 511 __u32 reserved__; 512 // --- extended/local Gather Len/Address pairs 513 __u32 GLen1; // DWord A 514 __u32 GAddr1; 515 __u32 GLen2; 516 __u32 GAddr2; 517 __u32 GLen3; 518 __u32 GAddr3; 519 } TachLiteTRE; 520 521 typedef struct ext_sg_page_ptr_t *PSGPAGES; 522 typedef struct ext_sg_page_ptr_t { 523 unsigned char page[TL_EXT_SG_PAGE_BYTELEN * 2]; // 2x for alignment 524 dma_addr_t busaddr; // need the bus addresses and 525 unsigned int maplen; // lengths for later pci unmapping. 526 PSGPAGES next; 527 } SGPAGES; // linked list of S/G pairs, by Exchange 528 529 typedef struct // SCSI Exchange State Table 530 { 531 union // Entry can be IWE, IRE, TWE, TRE 532 { // 64 bytes per entry 533 TachLiteIWE IWE; 534 TachLiteIRE IRE; 535 TachLiteTWE TWE; 536 TachLiteTRE TRE; 537 } u[TACH_SEST_LEN]; 538 539 TachFCHDR DataHDR[TACH_SEST_LEN]; // for SEST FCP_DATA frame hdr (no pl) 540 TachFCHDR_RSP RspHDR[TACH_SEST_LEN]; // space for SEST FCP_RSP frame 541 PSGPAGES sgPages[TACH_SEST_LEN]; // head of linked list of Pool-allocations 542 __u32 length; // Length register 543 __u32 base; // copy of base ptr for debug 544 } TachSEST; 545 546 547 548 typedef struct // each register has it's own address 549 // and value (used for write-only regs) 550 { 551 void *address; 552 volatile __u32 value; 553 } FCREGISTER; 554 555 typedef struct // Host copy - TachLite Registers 556 { 557 __u32 IOBaseL, IOBaseU; // I/O port lower and upper TL register addresses 558 __u32 MemBase; // memory mapped register addresses 559 void *ReMapMemBase; // O/S VM reference for MemBase 560 __u32 wwn_hi; // WWN is set once at startup 561 __u32 wwn_lo; 562 __u32 my_al_pa; // al_pa received after LIP() 563 __u32 ROMCTR; // flags for on-board RAM/ROM 564 __u32 RAMBase; // on-board RAM (i.e. some Tachlites) 565 __u32 SROMBase; // on-board EEPROM (some Tachlites) 566 __u32 PCIMCTR; // PCI Master Control Reg (has bus width) 567 568 FCREGISTER INTEN; // copy of interrupt enable mask 569 FCREGISTER INTPEND; // interrupt pending 570 FCREGISTER INTSTAT; // interrupt status 571 FCREGISTER SFQconsumerIndex; 572 FCREGISTER ERQproducerIndex; 573 FCREGISTER TYconfig; // TachYon (chip level) 574 FCREGISTER TYcontrol; 575 FCREGISTER TYstatus; 576 FCREGISTER FMconfig; // Frame Manager (FC loop level) 577 FCREGISTER FMcontrol; 578 FCREGISTER FMstatus; 579 FCREGISTER FMLinkStatus1; 580 FCREGISTER FMLinkStatus2; 581 FCREGISTER FMBB_CreditZero; 582 FCREGISTER status; 583 FCREGISTER ed_tov; // error detect time-out value 584 FCREGISTER rcv_al_pa; // received arb. loop physical address 585 FCREGISTER primitive; // e.g. LIP(), OPN(), ... 586 } TL_REGISTERS; 587 588 589 590 typedef struct { 591 __u32 ok; 592 __u32 invalidArgs; 593 __u32 linkDown; 594 __u32 linkUp; 595 __u32 outQueFull; 596 __u32 SESTFull; 597 __u32 hpe; // host programming err (from Tach) 598 __u32 FC4aborted; // aborts from Application or upper driver layer 599 __u32 FC2aborted; // aborts from our driver's timeouts 600 __u32 timeouts; // our driver timeout (on individual exchanges) 601 __u32 logouts; // explicit - sent LOGO; implicit - device removed 602 __u32 retries; 603 __u32 linkFailTX; 604 __u32 linkFailRX; 605 __u32 CntErrors; // byte count expected != count received (typ. SEST) 606 __u32 e_stores; // elastic store errs 607 __u32 resets; // hard or soft controller resets 608 __u32 FMinits; // TACH Frame Manager Init (e.g. LIPs) 609 __u32 lnkQueFull; // too many LOGIN, loop commands 610 __u32 ScsiQueFull; // too many FCP-SCSI inbound frames 611 __u32 LossofSignal; // FM link status 1 regs 612 __u32 BadRXChar; // FM link status 1 regs 613 __u32 LossofSync; // FM link status 1 regs 614 __u32 Rx_EOFa; // FM link status 2 regs (received EOFa) 615 __u32 Dis_Frm; // FM link status 2 regs (discarded frames) 616 __u32 Bad_CRC; // FM link status 2 regs 617 __u32 BB0_Timer; // FM BB_Credit Zero Timer Reg 618 __u32 loopBreaks; // infinite loop exits 619 __u32 lastBB0timer; // static accum. buffer needed by Tachlite 620 } FCSTATS; 621 622 623 typedef struct // Config Options 624 { // LS Bit first 625 __u16:1; // bit0: 626 __u16 flogi:1; // bit1: We sent FLOGI - wait for Fabric logins 627 __u16 fabric:1; // bit2: Tachyon detected Fabric (FM stat LG) 628 __u16 LILPin:1; // bit3: We can use an FC-AL LILP frame 629 __u16 target:1; // bit4: this Port has SCSI target capability 630 __u16 initiator:1; // bit5: this Port has SCSI initiator capability 631 __u16 extLoopback:1; // bit6: loopback at GBIC 632 __u16 intLoopback:1; // bit7: loopback in HP silicon 633 __u16:1; // bit8: 634 __u16:1; // bit9: 635 __u16:1; // bit10: 636 __u16:1; // bit11: 637 __u16:1; // bit12: 638 __u16:1; // bit13: 639 __u16:1; // bit14: 640 __u16:1; // bit15: 641 } FC_OPTIONS; 642 643 644 645 typedef struct dyn_mem_pair { 646 void *BaseAllocated; // address as allocated from O/S; 647 unsigned long AlignedAddress; // aligned address (used by Tachyon DMA) 648 dma_addr_t dma_handle; 649 size_t size; 650 } ALIGNED_MEM; 651 652 653 654 655 // these structs contain only CRUCIAL (stuff we actually use) parameters 656 // from FC-PH(n) logins. (Don't save entire LOGIN payload to save mem.) 657 658 // Implicit logout happens when the loop goes down - we require PDISC 659 // to restore. Explicit logout is when WE decide never to talk to someone, 660 // or when a target refuses to talk to us, i.e. sends us a LOGO frame or 661 // LS_RJT reject in response to our PLOGI request. 662 663 #define IMPLICIT_LOGOUT 1 664 #define EXPLICIT_LOGOUT 2 665 666 typedef struct { 667 __u8 channel; // SCSI "bus" 668 __u8 target; 669 __u8 InqDeviceType; // byte 0 from SCSI Inquiry response 670 __u8 VolumeSetAddressing; // FCP-SCSI LUN coding (40h for VSA) 671 __u8 LunMasking; // True if selective presentation supported 672 __u8 lun[CPQFCTS_MAX_LUN]; 673 } SCSI_NEXUS; 674 675 676 typedef struct { 677 union { 678 __u8 ucWWN[8]; // a FC 64-bit World Wide Name/ PortID of target 679 // addressing of single target on single loop... 680 u64 liWWN; 681 } u; 682 683 __u32 port_id; // a FC 24-bit address of port (lower 8 bits = al_pa) 684 685 Scsi_Cmnd ScsiCmnd; // command buffer for Report Luns 686 #define REPORT_LUNS_PL 256 687 __u8 ReportLunsPayload[REPORT_LUNS_PL]; 688 689 SCSI_NEXUS ScsiNexus; // LUNs per FC device 690 691 __u32 LOGO_counter; // might try several times before logging out for good 692 __u32 LOGO_timer; // after LIP, ports expecting PDISC must time-out and 693 // LOGOut if successful PDISC not completed in 2 secs 694 695 __u32 concurrent_seq; // must be 1 or greater 696 __u32 rx_data_size; // e.g. 128, 256, 1024, 2048 per FC-PH spec 697 __u32 BB_credit; 698 __u32 EE_credit; 699 700 __u32 fcp_info; // from PRLI (i.e. INITIATOR/ TARGET flags) 701 // flags for login process 702 __u8 Originator; // Login sequence Originated (if false, we 703 // responded to another port's login sequence) 704 __u8 plogi; // PLOGI frame ACCepted (originated or responded) 705 __u8 pdisc; // PDISC frame was ORIGINATED (self-login logic) 706 __u8 prli; // PRLI frame ACCepted (originated or responded) 707 __u8 flogi; // FLOGI frame ACCepted (originated or responded) 708 __u8 logo; // port permanently logged out (invalid login param) 709 __u8 flogiReq; // Fabric login required (set in LIP process) 710 __u8 highest_ver; 711 __u8 lowest_ver; 712 713 714 // when the "target" (actually FC Port) is waiting for login 715 // (e.g. after Link reset), set the device_blocked bit; 716 // after Port completes login, un-block target. 717 __u8 device_blocked; // see Scsi_Device struct 718 719 // define singly-linked list of logged-in ports 720 // once a port_id is identified, it is remembered, 721 // even if the port is removed indefinitely 722 void * pNextPort; // actually, type PFC_LOGGEDIN_PORT; void for Compiler 723 724 } FC_LOGGEDIN_PORT, *PFC_LOGGEDIN_PORT; 725 726 727 728 // This serves as the ESB (Exchange Status Block), 729 // and has timeout counter; used for ABORTs 730 typedef struct { // FC-1 X_IDs 731 __u32 type; // ELS_PLOGI, SCSI_IWE, ... (0 if free) 732 PFC_LOGGEDIN_PORT pLoggedInPort; // FC device on other end of Exchange 733 Scsi_Cmnd *Cmnd; // Linux SCSI command packet includes S/G list 734 __u32 timeOut; // units of ??, DEC by driver, Abort when 0 735 __u32 reTries; // need one or more retries? 736 __u32 status; // flags indicating errors (0 if none) 737 TachLiteIRB IRB; // I/O Request Block, gets copied to ERQ 738 TachFCHDR_GCMND fchs; // location of IRB's Req_A_SFS_Addr 739 } FC_EXCHANGE, *PFC_EXCHANGE; 740 741 // Unfortunately, Linux limits our kmalloc() allocations to 128k. 742 // Because of this and the fact that our ScsiRegister allocation 743 // is also constrained, we move this large structure out for 744 // allocation after Scsi Register. 745 // (In other words, this cumbersome indirection is necessary 746 // because of kernel memory allocation constraints!) 747 748 typedef struct // we will allocate this dynamically 749 { 750 FC_EXCHANGE fcExchange[TACH_MAX_XID]; 751 } FC_EXCHANGES; 752 753 754 755 756 757 758 759 760 761 762 763 typedef struct { 764 char Name[64]; // name of controller ("HP Tachlite TL Rev2.0, 33MHz, 64bit bus") 765 //void * pAdapterDevExt; // back pointer to device object/extension 766 __u32 ChipType; // local numeric key for Tachyon Type / Rev. 767 __u32 status; // our Driver - logical status 768 769 TL_REGISTERS Registers; // reg addresses & host memory copies 770 // FC-4 mapping of 'transaction' to X_IDs 771 __u8 LILPmap[32 * 4]; // Loop Position Map of ALPAs (late FC-AL only) 772 FC_OPTIONS Options; // e.g. Target, Initiator, loopback... 773 __u8 highest_FCPH_ver; // FC-PH version limits 774 __u8 lowest_FCPH_ver; // FC-PH version limits 775 776 FC_EXCHANGES *Exchanges; 777 __u32 fcLsExchangeLRU; // Least Recently Used counter (Link Service) 778 __u32 fcSestExchangeLRU; // Least Recently Used counter (FCP-SCSI) 779 FC_LOGGEDIN_PORT fcPorts; // linked list of every FC port ever seen 780 FCSTATS fcStats; // FC comm err counters 781 782 // Host memory QUEUE pointers 783 TachLiteERQ *ERQ; // Exchange Request Que 784 TachyonIMQ *IMQ; // Inbound Message Que 785 TachLiteSFQ *SFQ; // Single Frame Queue 786 TachSEST *SEST; // SCSI Exchange State Table 787 788 dma_addr_t exch_dma_handle; 789 790 // these function pointers are for "generic" functions, which are 791 // replaced with Host Bus Adapter types at 792 // runtime. 793 int (*CreateTachyonQues) (void *, int); 794 int (*DestroyTachyonQues) (void *, int); 795 int (*LaserControl) (void *, int); // e.g. On/Off 796 int (*ResetTachyon) (void *, int); 797 void (*FreezeTachyon) (void *, int); 798 void (*UnFreezeTachyon) (void *, int); 799 int (*InitializeTachyon) (void *, int, int); 800 int (*InitializeFrameManager) (void *, int); 801 int (*ProcessIMQEntry) (void *); 802 int (*ReadWriteWWN) (void *, int ReadWrite); 803 int (*ReadWriteNVRAM) (void *, void *, int ReadWrite); 804 805 } TACHYON, *PTACHYON; 806 807 808 void cpqfcTSClearLinkStatusCounters(TACHYON * fcChip); 809 810 int CpqTsCreateTachLiteQues(void *pHBA, int opcode); 811 int CpqTsDestroyTachLiteQues(void *, int); 812 int CpqTsInitializeTachLite(void *pHBA, int opcode1, int opcode2); 813 814 int CpqTsProcessIMQEntry(void *pHBA); 815 int CpqTsResetTachLite(void *pHBA, int type); 816 void CpqTsFreezeTachlite(void *pHBA, int type); 817 void CpqTsUnFreezeTachlite(void *pHBA, int type); 818 int CpqTsInitializeFrameManager(void *pHBA, int); 819 int CpqTsLaserControl(void *addrBase, int opcode); 820 int CpqTsReadWriteWWN(void *, int ReadWrite); 821 int CpqTsReadWriteNVRAM(void *, void *data, int ReadWrite); 822 823 void cpqfcTS_WorkTask(struct Scsi_Host *HostAdapter); 824 void cpqfcTSWorkerThread(void *host); 825 826 int cpqfcTS_GetNVRAM_data(__u8 * wwnbuf, __u8 * buf); 827 __u32 cpqfcTS_ReadNVRAM(void *GPIOin, void *GPIOout, __u16 count, __u8 * buf); 828 829 __u8 tl_write_i2c_nvram(void *GPIOin, void *GPIOout, __u16 startOffset, // e.g. 0x2f for WWN start 830 __u16 count, __u8 * buf); 831 832 833 // define misc functions 834 int cpqfcTSGetLPSM(PTACHYON fcChip, char cErrorString[]); 835 int cpqfcTSDecodeGBICtype(PTACHYON fcChip, char cErrorString[]); 836 void *fcMemManager(struct pci_dev *pdev, ALIGNED_MEM * dyn_mem_pair, __u32 n_alloc, __u32 ab, __u32 ulAlignedAddress, dma_addr_t * dma_handle); 837 838 void BigEndianSwap(__u8 * source, __u8 * dest, __u16 cnt); 839 840 //__u32 virt_to_phys( void * virtaddr ); 841 842 843 // Linux interrupt handler 844 void cpqfcTS_intr_handler(int irq, void *dev_id, struct pt_regs *regs); 845 void cpqfcTSheartbeat(unsigned long ptr); 846 847 848 849 // The biggest Q element we deal with is Aborts - we 850 // need 4 bytes for x_ID, and a Scsi_Cmnd (~284 bytes) 851 //#define LINKQ_ITEM_SIZE ((4+sizeof(Scsi_Cmnd)+3)/4) 852 #define LINKQ_ITEM_SIZE (3*16) 853 typedef struct { 854 __u32 Type; // e.g. LINKUP, SFQENTRY, PDISC, BLS_ABTS, ... 855 __u32 ulBuff[LINKQ_ITEM_SIZE]; 856 } LINKQ_ITEM; 857 858 #define FC_LINKQ_DEPTH TACH_MAX_XID 859 typedef struct { 860 __u32 producer; 861 __u32 consumer; // when producer equals consumer, Q empty 862 863 LINKQ_ITEM Qitem[FC_LINKQ_DEPTH]; 864 865 } FC_LINK_QUE, *PFC_LINK_QUE; 866 867 868 // DPC routines post to here on Inbound SCSI frames 869 // User thread processes 870 #define FC_SCSIQ_DEPTH 32 871 872 typedef struct { 873 int Type; // e.g. SCSI 874 __u32 ulBuff[3 * 16]; 875 } SCSIQ_ITEM; 876 877 typedef struct { 878 __u32 producer; 879 __u32 consumer; // when producer equals consumer, Q empty 880 881 SCSIQ_ITEM Qitem[FC_SCSIQ_DEPTH]; 882 883 } FC_SCSI_QUE, *PFC_SCSI_QUE; 884 885 886 887 888 889 #define DYNAMIC_ALLOCATIONS 4 // Tachyon aligned allocations: ERQ,IMQ,SFQ,SEST 890 891 // Linux space allocated per HBA (chip state, etc.) 892 typedef struct { 893 struct Scsi_Host *HostAdapter; // back pointer to Linux Scsi struct 894 895 TACHYON fcChip; // All Tachyon registers, Queues, functions 896 ALIGNED_MEM dynamic_mem[DYNAMIC_ALLOCATIONS]; 897 898 struct pci_dev *PciDev; 899 dma_addr_t fcLQ_dma_handle; 900 901 Scsi_Cmnd *LinkDnCmnd[CPQFCTS_REQ_QUEUE_LEN]; // collects Cmnds during LDn 902 // (for Acceptable targets) 903 Scsi_Cmnd *BoardLockCmnd[CPQFCTS_REQ_QUEUE_LEN]; // SEST was full 904 905 Scsi_Cmnd *BadTargetCmnd[CPQFCTS_MAX_TARGET_ID]; // missing targets 906 907 u_char HBAnum; // 0-based host number 908 909 910 struct timer_list cpqfcTStimer; // FC utility timer for implicit 911 // logouts, FC protocol timeouts, etc. 912 int fcStatsTime; // Statistics delta reporting time 913 914 struct task_struct *worker_thread; // our kernel thread 915 int PortDiscDone; // set by SendLogins(), cleared by LDn 916 917 struct semaphore *TachFrozen; 918 struct semaphore *TYOBcomplete; // handshake for Tach outbound frames 919 struct semaphore *fcQueReady; // FibreChannel work for our kernel thread 920 struct semaphore *notify_wt; // synchronizes kernel thread kill 921 struct semaphore *BoardLock; 922 923 PFC_LINK_QUE fcLQ; // the WorkerThread operates on this 924 925 spinlock_t hba_spinlock; // held/released by WorkerThread 926 927 } CPQFCHBA; 928 929 #define CPQ_SPINLOCK_HBA( x ) spin_lock(&x->hba_spinlock); 930 #define CPQ_SPINUNLOCK_HBA(x) spin_unlock(&x->hba_spinlock); 931 932 933 934 void cpqfcTSImplicitLogout(CPQFCHBA * cpqfcHBAdata, PFC_LOGGEDIN_PORT pFcPort); 935 936 937 void cpqfcTSTerminateExchange(CPQFCHBA *, SCSI_NEXUS * target, int); 938 939 PFC_LOGGEDIN_PORT fcPortLoggedIn(CPQFCHBA * cpqfcHBAdata, TachFCHDR_GCMND * fchs, __u8, __u8); 940 void fcProcessLoggedIn(CPQFCHBA * cpqfcHBAdata, TachFCHDR_GCMND * fchs); 941 942 943 __u32 cpqfcTSBuildExchange(CPQFCHBA * cpqfcHBAdata, __u32 type, // e.g. PLOGI 944 TachFCHDR_GCMND * InFCHS, // incoming FCHS 945 void *Data, // the CDB, scatter/gather, etc. 946 __s32 * ExchangeID); // allocated exchange ID 947 948 __u32 cpqfcTSStartExchange(CPQFCHBA * cpqfcHBAdata, __s32 ExchangeID); 949 950 void cpqfcTSCompleteExchange(struct pci_dev *pcidev, PTACHYON fcChip, __u32 exchange_ID); 951 952 953 PFC_LOGGEDIN_PORT fcFindLoggedInPort(PTACHYON fcChip, Scsi_Cmnd * Cmnd, // (We want the channel/target/lun Nexus from Cmnd) 954 __u32 port_id, // search linked list for al_pa, or 955 __u8 wwn[8], // search linked list for WWN, or... 956 PFC_LOGGEDIN_PORT * pLastLoggedInPort); 957 958 void cpqfcTSPutLinkQue(CPQFCHBA * cpqfcHBAdata, int Type, void *QueContent); 959 960 void fcPutScsiQue(CPQFCHBA * cpqfcHBAdata, int Type, void *QueContent); 961 962 void fcLinkQReset(CPQFCHBA *); 963 void fcScsiQReset(CPQFCHBA *); 964 void fcSestReset(CPQFCHBA *); 965 966 void cpqfc_pci_unmap(struct pci_dev *pcidev, Scsi_Cmnd * cmd, PTACHYON fcChip, __u32 x_ID); 967 968 extern const int number_of_al_pa; 969 970 #define FCP_RESID_UNDER 0x80000 971 #define FCP_RESID_OVER 0x40000 972 #define FCP_SNS_LEN_VALID 0x20000 973 #define FCP_RSP_LEN_VALID 0x10000 974 975 // RSP_CODE definitions (dpANS Fibre Channel Protocol for SCSI, pg 34) 976 #define FCP_DATA_LEN_NOT_BURST_LEN 0x1000000 977 #define FCP_CMND_FIELD_INVALID 0x2000000 978 #define FCP_DATA_RO_NOT_XRDY_RO 0x3000000 979 #define FCP_TASKFUNCTION_NS 0x4000000 980 #define FCP_TASKFUNCTION_FAIL 0x5000000 981 982 // FCP-SCSI response status struct 983 typedef struct // see "TachFCHDR_RSP" definition - 64 bytes 984 { 985 __u32 reserved; 986 __u32 reserved1; 987 __u32 fcp_status; // field validity and SCSI status 988 __u32 fcp_resid; 989 __u32 fcp_sns_len; // length of FCP_SNS_INFO field 990 __u32 fcp_rsp_len; // length of FCP_RSP_INFO field (expect 8) 991 __u32 fcp_rsp_info; // 4 bytes of FCP protocol response information 992 __u32 fcp_rsp_info2; // (4 more bytes, since most implementations use 8) 993 __u8 fcp_sns_info[36]; // bytes for SCSI sense (ASC, ASCQ) 994 995 } FCP_STATUS_RESPONSE, *PFCP_STATUS_RESPONSE; 996 997 998 // Fabric State Change Registration 999 typedef struct scrpl { 1000 __u32 command; 1001 __u32 function; 1002 } SCR_PL; 1003 1004 // Fabric Name Service Request 1005 typedef struct nsrpl { 1006 __u32 CT_Rev; // (& IN_ID) WORD 0 1007 __u32 FCS_Type; // WORD 1 1008 __u32 Command_code; // WORD 2 1009 __u32 reason_code; // WORD 3 1010 __u32 FCP; // WORD 4 (lower byte) 1011 1012 } NSR_PL; 1013 1014 1015 1016 // "FC.H" 1017 #define MAX_RX_SIZE 0x800 // Max Receive Buffer Size is 2048 1018 #define MIN_RX_SIZE 0x100 // Min Size is 256, per FC-PLDA Spec 1019 #define MAX_TARGET_RXIDS SEST_DEPTH 1020 #define TARGET_RX_SIZE SEST_BUFFER_LENGTH 1021 1022 #define CLASS_1 0x01 1023 #define CLASS_2 0x02 1024 #define CLASS_3 0x03 1025 1026 #define FC_PH42 0x08 1027 #define FC_PH43 0x09 1028 #define FC_PH3 0x20 1029 1030 #define RR_TOV 2 // Minimum Time for target to wait for 1031 // PDISC after a LIP. 1032 #define E_D_TOV 2 // Minimum Time to wait for Sequence 1033 // Completion. 1034 #define R_A_TOV 0 // Minimum Time for Target to wait 1035 // before reclaiming resources. 1036 // 1037 // R_CTL Field 1038 // 1039 // Routing Bits (31-28) 1040 // 1041 #define FC4_DEVICE_DATA 0x00000000 1042 #define EXT_LINK_DATA 0x20000000 1043 #define FC4_LINK_DATA 0x30000000 1044 #define VIDEO_DATA 0x40000000 1045 #define BASIC_LINK_DATA 0x80000000 1046 #define LINK_CONTROL 0xC0000000 1047 #define ROUTING_MASK 0xF0000000 1048 1049 // 1050 // Information Bits (27-24) 1051 // 1052 #define UNCAT_INFORMATION 0x00000000 1053 #define SOLICITED_DATA 0x01000000 1054 #define UNSOLICITED_CONTROL 0x02000000 1055 #define SOLICITED_CONTROL 0x03000000 1056 #define UNSOLICITED_DATA 0x04000000 1057 #define DATA_DESCRIPTOR 0x05000000 1058 #define UNSOLICITED_COMMAND 0x06000000 1059 #define COMMAND_STATUS 0x07000000 1060 #define INFO_MASK 0x0F000000 1061 // 1062 // (Link Control Codes) 1063 // 1064 #define ACK_1 0x00000000 1065 #define ACK_0_OR_N 0x01000000 1066 #define P_RJT 0x02000000 1067 #define F_RJT 0x03000000 1068 #define P_BSY 0x04000000 1069 #define FABRIC_BUSY_TO_DF 0x05000000 // Fabric Busy to Data Frame 1070 #define FABRIC_BUSY_TO_LC 0x06000000 // Fabric Busy to Link Ctl Frame 1071 #define LINK_CREDIT_RESET 0x07000000 1072 // 1073 // (Link Service Command Codes) 1074 // 1075 //#define LS_RJT 0x01000000 // LS Reject 1076 1077 #define LS_ACC 0x02000000 // LS Accept 1078 #define LS_PLOGI 0x03000000 // N_PORT Login 1079 #define LS_FLOGI 0x04000000 // F_PORT Login 1080 #define LS_LOGO 0x05000000 // Logout 1081 #define LS_ABTX 0x06000000 // Abort Exchange 1082 #define LS_RCS 0x07000000 // Read Connection Status 1083 #define LS_RES 0x08000000 // Read Exchange Status 1084 #define LS_RSS 0x09000000 // Read Sequence Status 1085 #define LS_RSI 0x0A000000 // Request Seq Initiative 1086 #define LS_ESTS 0x0B000000 // Establish Steaming 1087 #define LS_ESTC 0x0C000000 // Estimate Credit 1088 #define LS_ADVC 0x0D000000 // Advice Credit 1089 #define LS_RTV 0x0E000000 // Read Timeout Value 1090 #define LS_RLS 0x0F000000 // Read Link Status 1091 #define LS_ECHO 0x10000000 // Echo 1092 #define LS_TEST 0x11000000 // Test 1093 #define LS_RRQ 0x12000000 // Reinstate Rec. Qual. 1094 #define LS_PRLI 0x20000000 // Process Login 1095 #define LS_PRLO 0x21000000 // Process Logout 1096 #define LS_TPRLO 0x24000000 // 3rd Party Process Logout 1097 #define LS_PDISC 0x50000000 // Process Discovery 1098 #define LS_FDISC 0x51000000 // Fabric Discovery 1099 #define LS_ADISC 0x52000000 // Discover Address 1100 #define LS_RNC 0x53000000 // Report Node Capability 1101 #define LS_SCR 0x62000000 // State Change Registration 1102 #define LS_MASK 0xFF000000 1103 1104 // 1105 // TYPE Bit Masks 1106 // 1107 #define BASIC_LINK_SERVICE 0x00000000 1108 #define EXT_LINK_SERVICE 0x01000000 1109 1110 #define LLC 0x04000000 1111 #define LLC_SNAP 0x05000000 1112 #define SCSI_FCP 0x08000000 1113 #define SCSI_GPP 0x09000000 1114 #define IPI3_MASTER 0x11000000 1115 #define IPI3_SLAVE 0x12000000 1116 #define IPI3_PEER 0x13000000 1117 #define CP_IPI3_MASTER 0x15000000 1118 #define CP_IPI3_SLAVE 0x16000000 1119 #define CP_IPI3_PEER 0x17000000 1120 #define SBCCS_CHANNEL 0x19000000 1121 #define SBCCS_CONTROL 0x1A000000 1122 #define FIBRE_SERVICES 0x20000000 1123 #define FC_FG 0x21000000 1124 #define FC_XS 0x22000000 1125 #define FC_AL 0x23000000 1126 #define SNMP 0x24000000 1127 #define HIPPI_FP 0x40000000 1128 #define TYPE_MASK 0xFF000000 1129 1130 typedef struct { 1131 __u8 seq_id_valid; 1132 __u8 seq_id; 1133 __u16 reserved; // 2 bytes reserved 1134 __u32 ox_rx_id; 1135 __u16 low_seq_cnt; 1136 __u16 high_seq_cnt; 1137 } BA_ACC_PAYLOAD; 1138 1139 typedef struct { 1140 __u8 reserved; 1141 __u8 reason_code; 1142 __u8 reason_explain; 1143 __u8 vendor_unique; 1144 } BA_RJT_PAYLOAD; 1145 1146 1147 typedef struct { 1148 __u32 command_code; 1149 __u32 sid; 1150 __u16 ox_id; 1151 __u16 rx_id; 1152 } RRQ_MESSAGE; 1153 1154 typedef struct { 1155 __u32 command_code; 1156 __u8 vendor; 1157 __u8 explain; 1158 __u8 reason; 1159 __u8 reserved; 1160 } REJECT_MESSAGE; 1161 1162 1163 #define N_OR_F_PORT 0x1000 1164 #define RANDOM_RELATIVE_OFFSET 0x4000 1165 #define CONTINUOSLY_INCREASING 0x8000 1166 1167 #define CLASS_VALID 0x8000 1168 #define INTERMIX_MODE 0x4000 1169 #define TRANSPARENT_STACKED 0x2000 1170 #define LOCKDOWN_STACKED 0x1000 1171 #define SEQ_DELIVERY 0x800 1172 1173 #define XID_NOT_SUPPORTED 0x00 1174 #define XID_SUPPORTED 0x4000 1175 #define XID_REQUIRED 0xC000 1176 1177 #define ASSOCIATOR_NOT_SUPPORTED 0x00 1178 #define ASSOCIATOR_SUPPORTED 0x1000 1179 #define ASSOCIATOR_REQUIRED 0x3000 1180 1181 #define INIT_ACK0_SUPPORT 0x800 1182 #define INIT_ACKN_SUPPORT 0x400 1183 1184 #define RECIP_ACK0_SUPPORT 0x8000 1185 #define RECIP_ACKN_SUPPORT 0x4000 1186 1187 #define X_ID_INTERLOCK 0x2000 1188 1189 #define ERROR_POLICY 0x1800 // Error Policy Supported 1190 #define ERROR_DISCARD 0x00 // Only Discard Supported 1191 #define ERROR_DISC_PROCESS 0x02 // Discard and process supported 1192 1193 #define NODE_ID 0x01 1194 #define IEEE_EXT 0x20 1195 1196 // 1197 // Categories Supported Per Sequence 1198 // 1199 #define CATEGORIES_PER_SEQUENCE 0x300 1200 #define ONE_CATEGORY_SEQUENCE 0x00 // 1 Category per Sequence 1201 #define TWO_CATEGORY_SEQUENCE 0x01 // 2 Categories per Sequence 1202 #define MANY_CATEGORY_SEQUENCE 0x03 // > 2 Categories/Sequence 1203 1204 typedef struct { 1205 1206 __u16 initiator_control; 1207 __u16 service_options; 1208 1209 __u16 rx_data_size; 1210 __u16 recipient_control; 1211 1212 __u16 ee_credit; 1213 __u16 concurrent_sequences; 1214 1215 __u16 reserved; 1216 __u16 open_sequences; 1217 1218 } CLASS_PARAMETERS; 1219 1220 typedef struct { 1221 __u32 login_cmd; 1222 // 1223 // Common Service Parameters 1224 // 1225 struct { 1226 1227 __u16 bb_credit; 1228 __u8 lowest_ver; 1229 __u8 highest_ver; 1230 1231 __u16 bb_rx_size; 1232 __u16 common_features; 1233 1234 __u16 rel_offset; 1235 __u16 concurrent_seq; 1236 1237 1238 __u32 e_d_tov; 1239 } cmn_services; 1240 1241 // 1242 // Port Name 1243 // 1244 __u8 port_name[8]; 1245 1246 // 1247 // Node/Fabric Name 1248 // 1249 __u8 node_name[8]; 1250 1251 // 1252 // Class 1, 2 and 3 Service Parameters 1253 // 1254 CLASS_PARAMETERS class1; 1255 CLASS_PARAMETERS class2; 1256 CLASS_PARAMETERS class3; 1257 1258 __u32 reserved[4]; 1259 1260 // 1261 // Vendor Version Level 1262 // 1263 __u8 vendor_id[2]; 1264 __u8 vendor_version[6]; 1265 __u32 buffer_size; 1266 __u16 rxid_start; 1267 __u16 total_rxids; 1268 } LOGIN_PAYLOAD; 1269 1270 1271 typedef struct { 1272 __u32 cmd; // 4 bytes 1273 __u8 n_port_identifier[3]; 1274 __u8 reserved; 1275 __u8 port_name[8]; 1276 } LOGOUT_PAYLOAD; 1277 1278 1279 // 1280 // PRLI Request Service Parameter Defines 1281 // 1282 #define PRLI_ACC 0x01 1283 #define PRLI_REQ 0x02 1284 #define ORIG_PROCESS_ASSOC_VALID 0x8000 1285 #define RESP_PROCESS_ASSOC_VALID 0x4000 1286 #define ESTABLISH_PAIR 0x2000 1287 #define DATA_OVERLAY_ALLOWED 0x40 1288 #define INITIATOR_FUNCTION 0x20 1289 #define TARGET_FUNCTION 0x10 1290 #define CMD_DATA_MIXED 0x08 1291 #define DATA_RESP_MIXED 0x04 1292 #define READ_XFER_RDY 0x02 1293 #define WRITE_XFER_RDY 0x01 1294 1295 #define RESPONSE_CODE_MASK 0xF00 1296 #define REQUEST_EXECUTED 0x100 1297 #define NO_RESOURCES 0x200 1298 #define INIT_NOT_COMPLETE 0x300 1299 #define IMAGE_DOES_NOT_EXIST 0x400 1300 #define BAD_PREDEFINED_COND 0x500 1301 #define REQ_EXEC_COND 0x600 1302 #define NO_MULTI_PAGE 0x700 1303 1304 typedef struct { 1305 __u16 payload_length; 1306 __u8 page_length; 1307 __u8 cmd; 1308 1309 1310 __u32 valid; 1311 1312 __u32 orig_process_associator; 1313 1314 __u32 resp_process_associator; 1315 1316 __u32 fcp_info; 1317 } PRLI_REQUEST; 1318 1319 typedef struct { 1320 1321 __u16 payload_length; 1322 __u8 page_length; 1323 __u8 cmd; 1324 1325 __u32 valid; 1326 __u32 orig_process_associator; 1327 1328 __u32 resp_process_associator; 1329 __u32 reserved; 1330 } PRLO_REQUEST; 1331 1332 typedef struct { 1333 __u32 cmd; 1334 1335 __u32 hard_address; 1336 1337 __u8 port_name[8]; 1338 1339 __u8 node_name[8]; 1340 1341 __u32 s_id; 1342 } ADISC_PAYLOAD; 1343 1344 struct ext_sg_entry_t { 1345 __u32 len:18; /* buffer length, bits 0-17 */ 1346 __u32 uba:13; /* upper bus address bits 18-31 */ 1347 __u32 lba; /* lower bus address bits 0-31 */ 1348 }; 1349 1350 // J. McCarty's LINK.H 1351 // 1352 // LS_RJT Reason Codes 1353 // 1354 1355 #define INVALID_COMMAND_CODE 0x01 1356 #define LOGICAL_ERROR 0x03 1357 #define LOGICAL_BUSY 0x05 1358 #define PROTOCOL_ERROR 0x07 1359 #define UNABLE_TO_PERFORM 0x09 1360 #define COMMAND_NOT_SUPPORTED 0x0B 1361 #define LS_VENDOR_UNIQUE 0xFF 1362 1363 // 1364 // LS_RJT Reason Codes Explanations 1365 // 1366 #define NO_REASON 0x00 1367 #define OPTIONS_ERROR 0x01 1368 #define INITIATOR_CTL_ERROR 0x03 1369 #define RECIPIENT_CTL_ERROR 0x05 1370 #define DATA_FIELD_SIZE_ERROR 0x07 1371 #define CONCURRENT_SEQ_ERROR 0x09 1372 #define CREDIT_ERROR 0x0B 1373 #define INVALID_PORT_NAME 0x0D 1374 #define INVALID_NODE_NAME 0x0E 1375 #define INVALID_CSP 0x0F // Invalid Service Parameters 1376 #define INVALID_ASSOC_HDR 0x11 // Invalid Association Header 1377 #define ASSOC_HDR_REQUIRED 0x13 // Association Header Required 1378 #define LS_INVALID_S_ID 0x15 1379 #define INVALID_OX_RX_ID 0x17 // Invalid OX_ID RX_ID Combination 1380 #define CMD_IN_PROCESS 0x19 1381 #define INVALID_IDENTIFIER 0x1F // Invalid N_PORT Identifier 1382 #define INVALID_SEQ_ID 0x21 1383 #define ABT_INVALID_XCHNG 0x23 // Attempt to Abort an invalid Exchange 1384 #define ABT_INACTIVE_XCHNG 0x25 // Attempt to Abort an inactive Exchange 1385 #define NEED_REC_QUAL 0x27 // Recovery Qualifier required 1386 #define NO_LOGIN_RESOURCES 0x29 // No resources to support login 1387 #define NO_DATA 0x2A // Unable to supply requested data 1388 #define REQUEST_NOT_SUPPORTED 0x2C // Request Not Supported 1389 1390 // 1391 // Link Control Codes 1392 // 1393 1394 // 1395 // P_BSY Action Codes 1396 // 1397 #define SEQUENCE_TERMINATED 0x01000000 1398 #define SEQUENCE_ACTIVE 0x02000000 1399 1400 // 1401 // P_BSY Reason Codes 1402 // 1403 #define PHYS_NPORT_BUSY 0x010000 1404 #define NPORT_RESOURCE_BUSY 0x020000 1405 1406 // 1407 // P_RJT, F_RJT Action Codes 1408 // 1409 1410 #define RETRYABLE_ERROR 0x01000000 1411 #define NON_RETRYABLE_ERROR 0x02000000 1412 1413 // 1414 // P_RJT, F_RJT Reason Codes 1415 // 1416 #define INVALID_D_ID 0x010000 1417 #define INVALID_S_ID 0x020000 1418 #define NPORT_NOT_AVAIL_TMP 0x030000 1419 #define NPORT_NOT_AVAIL_PERM 0x040000 1420 #define CLASS_NOT_SUPPORTED 0x050000 1421 #define USAGE_ERROR 0x060000 1422 #define TYPE_NOT_SUPPORTED 0x070000 1423 #define INVAL_LINK_CONTROL 0x080000 1424 #define INVAL_R_CTL 0x090000 1425 #define INVAL_F_CTL 0x0A0000 1426 #define INVAL_OX_ID 0x0B0000 1427 #define INVAL_RX_ID 0x0C0000 1428 #define INVAL_SEQ_ID 0x0D0000 1429 #define INVAL_DF_CTL 0x0E0000 1430 #define INVAL_SEQ_CNT 0x0F0000 1431 #define INVAL_PARAMS 0x100000 1432 #define EXCHANGE_ERROR 0x110000 1433 #define LS_PROTOCOL_ERROR 0x120000 1434 #define INCORRECT_LENGTH 0x130000 1435 #define UNEXPECTED_ACK 0x140000 1436 #define LOGIN_REQ 0x160000 1437 #define EXCESSIVE_SEQ 0x170000 1438 #define NO_EXCHANGE 0x180000 1439 #define SEC_HDR_NOT_SUPPORTED 0x190000 1440 #define NO_FABRIC 0x1A0000 1441 #define P_VENDOR_UNIQUE 0xFF0000 1442 1443 // 1444 // BA_RJT Reason Codes 1445 // 1446 #define BA_INVALID_COMMAND 0x00010000 1447 #define BA_LOGICAL_ERROR 0x00030000 1448 #define BA_LOGICAL_BUSY 0x00050000 1449 #define BA_PROTOCOL_ERROR 0x00070000 1450 #define BA_UNABLE_TO_PERFORM 0x00090000 1451 1452 // 1453 // BA_RJT Reason Explanation Codes 1454 // 1455 #define BA_NO_REASON 0x00000000 1456 #define BA_INVALID_OX_RX 0x00000300 1457 #define BA_SEQUENCE_ABORTED 0x00000500 1458 1459 1460 1461 #endif /* CPQFCTSSTRUCTS_H */ 1462