1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994 Waldorf GMBH
7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8  * Copyright (C) 1996 Paul M. Antoine
9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10  */
11 #ifndef _ASM_PROCESSOR_H
12 #define _ASM_PROCESSOR_H
13 
14 #include <linux/atomic.h>
15 #include <linux/cpumask.h>
16 #include <linux/sizes.h>
17 #include <linux/threads.h>
18 
19 #include <asm/cachectl.h>
20 #include <asm/cpu.h>
21 #include <asm/cpu-info.h>
22 #include <asm/dsemul.h>
23 #include <asm/mipsregs.h>
24 #include <asm/prefetch.h>
25 #include <asm/vdso/processor.h>
26 
27 /*
28  * System setup and hardware flags..
29  */
30 
31 extern unsigned int vced_count, vcei_count;
32 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
33 
34 #ifdef CONFIG_32BIT
35 /*
36  * User space process size: 2GB. This is hardcoded into a few places,
37  * so don't change it unless you know what you are doing.
38  */
39 #define TASK_SIZE	0x80000000UL
40 
41 #define STACK_TOP_MAX	TASK_SIZE
42 
43 #define TASK_IS_32BIT_ADDR 1
44 
45 #endif
46 
47 #ifdef CONFIG_64BIT
48 /*
49  * User space process size: 1TB. This is hardcoded into a few places,
50  * so don't change it unless you know what you are doing.  TASK_SIZE
51  * is limited to 1TB by the R4000 architecture; R10000 and better can
52  * support 16TB; the architectural reserve for future expansion is
53  * 8192EB ...
54  */
55 #define TASK_SIZE32	0x7fff8000UL
56 #ifdef CONFIG_MIPS_VA_BITS_48
57 #define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
58 #else
59 #define TASK_SIZE64     0x10000000000UL
60 #endif
61 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
62 #define STACK_TOP_MAX	TASK_SIZE64
63 
64 #define TASK_SIZE_OF(tsk)						\
65 	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
66 
67 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
68 
69 #endif
70 
71 #define VDSO_RANDOMIZE_SIZE	(TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M)
72 
73 extern unsigned long mips_stack_top(void);
74 #define STACK_TOP		mips_stack_top()
75 
76 /*
77  * This decides where the kernel will search for a free chunk of vm
78  * space during mmap's.
79  */
80 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
81 
82 
83 #define NUM_FPU_REGS	32
84 
85 #ifdef CONFIG_CPU_HAS_MSA
86 # define FPU_REG_WIDTH	128
87 #else
88 # define FPU_REG_WIDTH	64
89 #endif
90 
91 union fpureg {
92 	__u32	val32[FPU_REG_WIDTH / 32];
93 	__u64	val64[FPU_REG_WIDTH / 64];
94 };
95 
96 #ifdef CONFIG_CPU_LITTLE_ENDIAN
97 # define FPR_IDX(width, idx)	(idx)
98 #else
99 # define FPR_IDX(width, idx)	((idx) ^ ((64 / (width)) - 1))
100 #endif
101 
102 #define BUILD_FPR_ACCESS(width) \
103 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)	\
104 {									\
105 	return fpr->val##width[FPR_IDX(width, idx)];			\
106 }									\
107 									\
108 static inline void set_fpr##width(union fpureg *fpr, unsigned idx,	\
109 				  u##width val)				\
110 {									\
111 	fpr->val##width[FPR_IDX(width, idx)] = val;			\
112 }
113 
114 BUILD_FPR_ACCESS(32)
115 BUILD_FPR_ACCESS(64)
116 
117 /*
118  * It would be nice to add some more fields for emulator statistics,
119  * the additional information is private to the FPU emulator for now.
120  * See arch/mips/include/asm/fpu_emulator.h.
121  */
122 
123 struct mips_fpu_struct {
124 	union fpureg	fpr[NUM_FPU_REGS];
125 	unsigned int	fcr31;
126 	unsigned int	msacsr;
127 };
128 
129 #define NUM_DSP_REGS   6
130 
131 typedef unsigned long dspreg_t;
132 
133 struct mips_dsp_state {
134 	dspreg_t	dspr[NUM_DSP_REGS];
135 	unsigned int	dspcontrol;
136 };
137 
138 #define INIT_CPUMASK { \
139 	{0,} \
140 }
141 
142 struct mips3264_watch_reg_state {
143 	/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
144 	   64 bit kernel.  We use unsigned long as it has the same
145 	   property. */
146 	unsigned long watchlo[NUM_WATCH_REGS];
147 	/* Only the mask and IRW bits from watchhi. */
148 	u16 watchhi[NUM_WATCH_REGS];
149 };
150 
151 union mips_watch_reg_state {
152 	struct mips3264_watch_reg_state mips3264;
153 };
154 
155 #if defined(CONFIG_CPU_CAVIUM_OCTEON)
156 
157 struct octeon_cop2_state {
158 	/* DMFC2 rt, 0x0201 */
159 	unsigned long	cop2_crc_iv;
160 	/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
161 	unsigned long	cop2_crc_length;
162 	/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
163 	unsigned long	cop2_crc_poly;
164 	/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
165 	unsigned long	cop2_llm_dat[2];
166        /* DMFC2 rt, 0x0084 */
167 	unsigned long	cop2_3des_iv;
168 	/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
169 	unsigned long	cop2_3des_key[3];
170 	/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
171 	unsigned long	cop2_3des_result;
172 	/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
173 	unsigned long	cop2_aes_inp0;
174 	/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
175 	unsigned long	cop2_aes_iv[2];
176 	/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
177 	 * rt, 0x0107 */
178 	unsigned long	cop2_aes_key[4];
179 	/* DMFC2 rt, 0x0110 */
180 	unsigned long	cop2_aes_keylen;
181 	/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
182 	unsigned long	cop2_aes_result[2];
183 	/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
184 	 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
185 	 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
186 	 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
187 	 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
188 	unsigned long	cop2_hsh_datw[15];
189 	/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
190 	 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
191 	 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
192 	unsigned long	cop2_hsh_ivw[8];
193 	/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
194 	unsigned long	cop2_gfm_mult[2];
195 	/* DMFC2 rt, 0x025E - Pass2 */
196 	unsigned long	cop2_gfm_poly;
197 	/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
198 	unsigned long	cop2_gfm_result[2];
199 	/* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
200 	unsigned long	cop2_sha3[2];
201 };
202 #define COP2_INIT						\
203 	.cp2			= {0,},
204 
205 struct octeon_cvmseg_state {
206 	unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
207 			    [cpu_dcache_line_size() / sizeof(unsigned long)];
208 };
209 
210 #else
211 #define COP2_INIT
212 #endif
213 
214 #ifdef CONFIG_CPU_HAS_MSA
215 # define ARCH_MIN_TASKALIGN	16
216 # define FPU_ALIGN		__aligned(16)
217 #else
218 # define ARCH_MIN_TASKALIGN	8
219 # define FPU_ALIGN
220 #endif
221 
222 struct mips_abi;
223 
224 /*
225  * If you change thread_struct remember to change the #defines below too!
226  */
227 struct thread_struct {
228 	/* Saved main processor registers. */
229 	unsigned long reg16;
230 	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
231 	unsigned long reg29, reg30, reg31;
232 
233 	/* Saved cp0 stuff. */
234 	unsigned long cp0_status;
235 
236 #ifdef CONFIG_MIPS_FP_SUPPORT
237 	/* Saved fpu/fpu emulator stuff. */
238 	struct mips_fpu_struct fpu FPU_ALIGN;
239 	/* Assigned branch delay slot 'emulation' frame */
240 	atomic_t bd_emu_frame;
241 	/* PC of the branch from a branch delay slot 'emulation' */
242 	unsigned long bd_emu_branch_pc;
243 	/* PC to continue from following a branch delay slot 'emulation' */
244 	unsigned long bd_emu_cont_pc;
245 #endif
246 #ifdef CONFIG_MIPS_MT_FPAFF
247 	/* Emulated instruction count */
248 	unsigned long emulated_fp;
249 	/* Saved per-thread scheduler affinity mask */
250 	cpumask_t user_cpus_allowed;
251 #endif /* CONFIG_MIPS_MT_FPAFF */
252 
253 	/* Saved state of the DSP ASE, if available. */
254 	struct mips_dsp_state dsp;
255 
256 	/* Saved watch register state, if available. */
257 	union mips_watch_reg_state watch;
258 
259 	/* Other stuff associated with the thread. */
260 	unsigned long cp0_badvaddr;	/* Last user fault */
261 	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
262 	unsigned long error_code;
263 	unsigned long trap_nr;
264 #ifdef CONFIG_CPU_CAVIUM_OCTEON
265 	struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
266 	struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
267 #endif
268 	struct mips_abi *abi;
269 };
270 
271 #ifdef CONFIG_MIPS_MT_FPAFF
272 #define FPAFF_INIT						\
273 	.emulated_fp			= 0,			\
274 	.user_cpus_allowed		= INIT_CPUMASK,
275 #else
276 #define FPAFF_INIT
277 #endif /* CONFIG_MIPS_MT_FPAFF */
278 
279 #ifdef CONFIG_MIPS_FP_SUPPORT
280 # define FPU_INIT						\
281 	.fpu			= {				\
282 		.fpr		= {{{0,},},},			\
283 		.fcr31		= 0,				\
284 		.msacsr		= 0,				\
285 	},							\
286 	/* Delay slot emulation */				\
287 	.bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE),		\
288 	.bd_emu_branch_pc = 0,					\
289 	.bd_emu_cont_pc = 0,
290 #else
291 # define FPU_INIT
292 #endif
293 
294 #define INIT_THREAD  {						\
295 	/*							\
296 	 * Saved main processor registers			\
297 	 */							\
298 	.reg16			= 0,				\
299 	.reg17			= 0,				\
300 	.reg18			= 0,				\
301 	.reg19			= 0,				\
302 	.reg20			= 0,				\
303 	.reg21			= 0,				\
304 	.reg22			= 0,				\
305 	.reg23			= 0,				\
306 	.reg29			= 0,				\
307 	.reg30			= 0,				\
308 	.reg31			= 0,				\
309 	/*							\
310 	 * Saved cp0 stuff					\
311 	 */							\
312 	.cp0_status		= 0,				\
313 	/*							\
314 	 * Saved FPU/FPU emulator stuff				\
315 	 */							\
316 	FPU_INIT						\
317 	/*							\
318 	 * FPU affinity state (null if not FPAFF)		\
319 	 */							\
320 	FPAFF_INIT						\
321 	/*							\
322 	 * Saved DSP stuff					\
323 	 */							\
324 	.dsp			= {				\
325 		.dspr		= {0, },			\
326 		.dspcontrol	= 0,				\
327 	},							\
328 	/*							\
329 	 * saved watch register stuff				\
330 	 */							\
331 	.watch = {{{0,},},},					\
332 	/*							\
333 	 * Other stuff associated with the process		\
334 	 */							\
335 	.cp0_badvaddr		= 0,				\
336 	.cp0_baduaddr		= 0,				\
337 	.error_code		= 0,				\
338 	.trap_nr		= 0,				\
339 	/*							\
340 	 * Platform specific cop2 registers(null if no COP2)	\
341 	 */							\
342 	COP2_INIT						\
343 }
344 
345 struct task_struct;
346 
347 /* Free all resources held by a thread. */
348 #define release_thread(thread) do { } while(0)
349 
350 /*
351  * Do necessary setup to start up a newly executed thread.
352  */
353 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
354 
flush_thread(void)355 static inline void flush_thread(void)
356 {
357 }
358 
359 unsigned long __get_wchan(struct task_struct *p);
360 
361 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
362 			 THREAD_SIZE - 32 - sizeof(struct pt_regs))
363 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
364 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
365 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
366 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
367 
368 /*
369  * Return_address is a replacement for __builtin_return_address(count)
370  * which on certain architectures cannot reasonably be implemented in GCC
371  * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
372  * Note that __builtin_return_address(x>=1) is forbidden because GCC
373  * aborts compilation on some CPUs.  It's simply not possible to unwind
374  * some CPU's stackframes.
375  *
376  * __builtin_return_address works only for non-leaf functions.	We avoid the
377  * overhead of a function call by forcing the compiler to save the return
378  * address register on the stack.
379  */
380 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
381 
382 #ifdef CONFIG_CPU_HAS_PREFETCH
383 
384 #define ARCH_HAS_PREFETCH
385 #define prefetch(x) __builtin_prefetch((x), 0, 1)
386 
387 #define ARCH_HAS_PREFETCHW
388 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
389 
390 #endif
391 
392 /*
393  * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
394  * to the prctl syscall.
395  */
396 extern int mips_get_process_fp_mode(struct task_struct *task);
397 extern int mips_set_process_fp_mode(struct task_struct *task,
398 				    unsigned int value);
399 
400 #define GET_FP_MODE(task)		mips_get_process_fp_mode(task)
401 #define SET_FP_MODE(task,value)		mips_set_process_fp_mode(task, value)
402 
403 #endif /* _ASM_PROCESSOR_H */
404