1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef KFD_IOCTL_H_INCLUDED 24 #define KFD_IOCTL_H_INCLUDED 25 26 #include <drm/drm.h> 27 #include <linux/ioctl.h> 28 29 /* 30 * - 1.1 - initial version 31 * - 1.3 - Add SMI events support 32 * - 1.4 - Indicate new SRAM EDC bit in device properties 33 * - 1.5 - Add SVM API 34 * - 1.6 - Query clear flags in SVM get_attr API 35 * - 1.7 - Checkpoint Restore (CRIU) API 36 * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs 37 * - 1.9 - Add available memory ioctl 38 * - 1.10 - Add SMI profiler event log 39 * - 1.11 - Add unified memory for ctx save/restore area 40 */ 41 #define KFD_IOCTL_MAJOR_VERSION 1 42 #define KFD_IOCTL_MINOR_VERSION 11 43 44 struct kfd_ioctl_get_version_args { 45 __u32 major_version; /* from KFD */ 46 __u32 minor_version; /* from KFD */ 47 }; 48 49 /* For kfd_ioctl_create_queue_args.queue_type. */ 50 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 51 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 52 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 53 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 54 55 #define KFD_MAX_QUEUE_PERCENTAGE 100 56 #define KFD_MAX_QUEUE_PRIORITY 15 57 58 struct kfd_ioctl_create_queue_args { 59 __u64 ring_base_address; /* to KFD */ 60 __u64 write_pointer_address; /* from KFD */ 61 __u64 read_pointer_address; /* from KFD */ 62 __u64 doorbell_offset; /* from KFD */ 63 64 __u32 ring_size; /* to KFD */ 65 __u32 gpu_id; /* to KFD */ 66 __u32 queue_type; /* to KFD */ 67 __u32 queue_percentage; /* to KFD */ 68 __u32 queue_priority; /* to KFD */ 69 __u32 queue_id; /* from KFD */ 70 71 __u64 eop_buffer_address; /* to KFD */ 72 __u64 eop_buffer_size; /* to KFD */ 73 __u64 ctx_save_restore_address; /* to KFD */ 74 __u32 ctx_save_restore_size; /* to KFD */ 75 __u32 ctl_stack_size; /* to KFD */ 76 }; 77 78 struct kfd_ioctl_destroy_queue_args { 79 __u32 queue_id; /* to KFD */ 80 __u32 pad; 81 }; 82 83 struct kfd_ioctl_update_queue_args { 84 __u64 ring_base_address; /* to KFD */ 85 86 __u32 queue_id; /* to KFD */ 87 __u32 ring_size; /* to KFD */ 88 __u32 queue_percentage; /* to KFD */ 89 __u32 queue_priority; /* to KFD */ 90 }; 91 92 struct kfd_ioctl_set_cu_mask_args { 93 __u32 queue_id; /* to KFD */ 94 __u32 num_cu_mask; /* to KFD */ 95 __u64 cu_mask_ptr; /* to KFD */ 96 }; 97 98 struct kfd_ioctl_get_queue_wave_state_args { 99 __u64 ctl_stack_address; /* to KFD */ 100 __u32 ctl_stack_used_size; /* from KFD */ 101 __u32 save_area_used_size; /* from KFD */ 102 __u32 queue_id; /* to KFD */ 103 __u32 pad; 104 }; 105 106 struct kfd_ioctl_get_available_memory_args { 107 __u64 available; /* from KFD */ 108 __u32 gpu_id; /* to KFD */ 109 __u32 pad; 110 }; 111 112 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ 113 #define KFD_IOC_CACHE_POLICY_COHERENT 0 114 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 115 116 struct kfd_ioctl_set_memory_policy_args { 117 __u64 alternate_aperture_base; /* to KFD */ 118 __u64 alternate_aperture_size; /* to KFD */ 119 120 __u32 gpu_id; /* to KFD */ 121 __u32 default_policy; /* to KFD */ 122 __u32 alternate_policy; /* to KFD */ 123 __u32 pad; 124 }; 125 126 /* 127 * All counters are monotonic. They are used for profiling of compute jobs. 128 * The profiling is done by userspace. 129 * 130 * In case of GPU reset, the counter should not be affected. 131 */ 132 133 struct kfd_ioctl_get_clock_counters_args { 134 __u64 gpu_clock_counter; /* from KFD */ 135 __u64 cpu_clock_counter; /* from KFD */ 136 __u64 system_clock_counter; /* from KFD */ 137 __u64 system_clock_freq; /* from KFD */ 138 139 __u32 gpu_id; /* to KFD */ 140 __u32 pad; 141 }; 142 143 struct kfd_process_device_apertures { 144 __u64 lds_base; /* from KFD */ 145 __u64 lds_limit; /* from KFD */ 146 __u64 scratch_base; /* from KFD */ 147 __u64 scratch_limit; /* from KFD */ 148 __u64 gpuvm_base; /* from KFD */ 149 __u64 gpuvm_limit; /* from KFD */ 150 __u32 gpu_id; /* from KFD */ 151 __u32 pad; 152 }; 153 154 /* 155 * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use 156 * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an 157 * unlimited number of GPUs. 158 */ 159 #define NUM_OF_SUPPORTED_GPUS 7 160 struct kfd_ioctl_get_process_apertures_args { 161 struct kfd_process_device_apertures 162 process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */ 163 164 /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */ 165 __u32 num_of_nodes; 166 __u32 pad; 167 }; 168 169 struct kfd_ioctl_get_process_apertures_new_args { 170 /* User allocated. Pointer to struct kfd_process_device_apertures 171 * filled in by Kernel 172 */ 173 __u64 kfd_process_device_apertures_ptr; 174 /* to KFD - indicates amount of memory present in 175 * kfd_process_device_apertures_ptr 176 * from KFD - Number of entries filled by KFD. 177 */ 178 __u32 num_of_nodes; 179 __u32 pad; 180 }; 181 182 #define MAX_ALLOWED_NUM_POINTS 100 183 #define MAX_ALLOWED_AW_BUFF_SIZE 4096 184 #define MAX_ALLOWED_WAC_BUFF_SIZE 128 185 186 struct kfd_ioctl_dbg_register_args { 187 __u32 gpu_id; /* to KFD */ 188 __u32 pad; 189 }; 190 191 struct kfd_ioctl_dbg_unregister_args { 192 __u32 gpu_id; /* to KFD */ 193 __u32 pad; 194 }; 195 196 struct kfd_ioctl_dbg_address_watch_args { 197 __u64 content_ptr; /* a pointer to the actual content */ 198 __u32 gpu_id; /* to KFD */ 199 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 200 }; 201 202 struct kfd_ioctl_dbg_wave_control_args { 203 __u64 content_ptr; /* a pointer to the actual content */ 204 __u32 gpu_id; /* to KFD */ 205 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 206 }; 207 208 #define KFD_INVALID_FD 0xffffffff 209 210 /* Matching HSA_EVENTTYPE */ 211 #define KFD_IOC_EVENT_SIGNAL 0 212 #define KFD_IOC_EVENT_NODECHANGE 1 213 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 214 #define KFD_IOC_EVENT_HW_EXCEPTION 3 215 #define KFD_IOC_EVENT_SYSTEM_EVENT 4 216 #define KFD_IOC_EVENT_DEBUG_EVENT 5 217 #define KFD_IOC_EVENT_PROFILE_EVENT 6 218 #define KFD_IOC_EVENT_QUEUE_EVENT 7 219 #define KFD_IOC_EVENT_MEMORY 8 220 221 #define KFD_IOC_WAIT_RESULT_COMPLETE 0 222 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 223 #define KFD_IOC_WAIT_RESULT_FAIL 2 224 225 #define KFD_SIGNAL_EVENT_LIMIT 4096 226 227 /* For kfd_event_data.hw_exception_data.reset_type. */ 228 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 229 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 230 231 /* For kfd_event_data.hw_exception_data.reset_cause. */ 232 #define KFD_HW_EXCEPTION_GPU_HANG 0 233 #define KFD_HW_EXCEPTION_ECC 1 234 235 /* For kfd_hsa_memory_exception_data.ErrorType */ 236 #define KFD_MEM_ERR_NO_RAS 0 237 #define KFD_MEM_ERR_SRAM_ECC 1 238 #define KFD_MEM_ERR_POISON_CONSUMED 2 239 #define KFD_MEM_ERR_GPU_HANG 3 240 241 struct kfd_ioctl_create_event_args { 242 __u64 event_page_offset; /* from KFD */ 243 __u32 event_trigger_data; /* from KFD - signal events only */ 244 __u32 event_type; /* to KFD */ 245 __u32 auto_reset; /* to KFD */ 246 __u32 node_id; /* to KFD - only valid for certain 247 event types */ 248 __u32 event_id; /* from KFD */ 249 __u32 event_slot_index; /* from KFD */ 250 }; 251 252 struct kfd_ioctl_destroy_event_args { 253 __u32 event_id; /* to KFD */ 254 __u32 pad; 255 }; 256 257 struct kfd_ioctl_set_event_args { 258 __u32 event_id; /* to KFD */ 259 __u32 pad; 260 }; 261 262 struct kfd_ioctl_reset_event_args { 263 __u32 event_id; /* to KFD */ 264 __u32 pad; 265 }; 266 267 struct kfd_memory_exception_failure { 268 __u32 NotPresent; /* Page not present or supervisor privilege */ 269 __u32 ReadOnly; /* Write access to a read-only page */ 270 __u32 NoExecute; /* Execute access to a page marked NX */ 271 __u32 imprecise; /* Can't determine the exact fault address */ 272 }; 273 274 /* memory exception data */ 275 struct kfd_hsa_memory_exception_data { 276 struct kfd_memory_exception_failure failure; 277 __u64 va; 278 __u32 gpu_id; 279 __u32 ErrorType; /* 0 = no RAS error, 280 * 1 = ECC_SRAM, 281 * 2 = Link_SYNFLOOD (poison), 282 * 3 = GPU hang (not attributable to a specific cause), 283 * other values reserved 284 */ 285 }; 286 287 /* hw exception data */ 288 struct kfd_hsa_hw_exception_data { 289 __u32 reset_type; 290 __u32 reset_cause; 291 __u32 memory_lost; 292 __u32 gpu_id; 293 }; 294 295 /* Event data */ 296 struct kfd_event_data { 297 union { 298 struct kfd_hsa_memory_exception_data memory_exception_data; 299 struct kfd_hsa_hw_exception_data hw_exception_data; 300 }; /* From KFD */ 301 __u64 kfd_event_data_ext; /* pointer to an extension structure 302 for future exception types */ 303 __u32 event_id; /* to KFD */ 304 __u32 pad; 305 }; 306 307 struct kfd_ioctl_wait_events_args { 308 __u64 events_ptr; /* pointed to struct 309 kfd_event_data array, to KFD */ 310 __u32 num_events; /* to KFD */ 311 __u32 wait_for_all; /* to KFD */ 312 __u32 timeout; /* to KFD */ 313 __u32 wait_result; /* from KFD */ 314 }; 315 316 struct kfd_ioctl_set_scratch_backing_va_args { 317 __u64 va_addr; /* to KFD */ 318 __u32 gpu_id; /* to KFD */ 319 __u32 pad; 320 }; 321 322 struct kfd_ioctl_get_tile_config_args { 323 /* to KFD: pointer to tile array */ 324 __u64 tile_config_ptr; 325 /* to KFD: pointer to macro tile array */ 326 __u64 macro_tile_config_ptr; 327 /* to KFD: array size allocated by user mode 328 * from KFD: array size filled by kernel 329 */ 330 __u32 num_tile_configs; 331 /* to KFD: array size allocated by user mode 332 * from KFD: array size filled by kernel 333 */ 334 __u32 num_macro_tile_configs; 335 336 __u32 gpu_id; /* to KFD */ 337 __u32 gb_addr_config; /* from KFD */ 338 __u32 num_banks; /* from KFD */ 339 __u32 num_ranks; /* from KFD */ 340 /* struct size can be extended later if needed 341 * without breaking ABI compatibility 342 */ 343 }; 344 345 struct kfd_ioctl_set_trap_handler_args { 346 __u64 tba_addr; /* to KFD */ 347 __u64 tma_addr; /* to KFD */ 348 __u32 gpu_id; /* to KFD */ 349 __u32 pad; 350 }; 351 352 struct kfd_ioctl_acquire_vm_args { 353 __u32 drm_fd; /* to KFD */ 354 __u32 gpu_id; /* to KFD */ 355 }; 356 357 /* Allocation flags: memory types */ 358 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) 359 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) 360 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) 361 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) 362 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) 363 /* Allocation flags: attributes/access options */ 364 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) 365 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) 366 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) 367 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) 368 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) 369 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) 370 #define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25) 371 372 /* Allocate memory for later SVM (shared virtual memory) mapping. 373 * 374 * @va_addr: virtual address of the memory to be allocated 375 * all later mappings on all GPUs will use this address 376 * @size: size in bytes 377 * @handle: buffer handle returned to user mode, used to refer to 378 * this allocation for mapping, unmapping and freeing 379 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node 380 * for userptrs this is overloaded to specify the CPU address 381 * @gpu_id: device identifier 382 * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above 383 */ 384 struct kfd_ioctl_alloc_memory_of_gpu_args { 385 __u64 va_addr; /* to KFD */ 386 __u64 size; /* to KFD */ 387 __u64 handle; /* from KFD */ 388 __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */ 389 __u32 gpu_id; /* to KFD */ 390 __u32 flags; 391 }; 392 393 /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu 394 * 395 * @handle: memory handle returned by alloc 396 */ 397 struct kfd_ioctl_free_memory_of_gpu_args { 398 __u64 handle; /* to KFD */ 399 }; 400 401 /* Map memory to one or more GPUs 402 * 403 * @handle: memory handle returned by alloc 404 * @device_ids_array_ptr: array of gpu_ids (__u32 per device) 405 * @n_devices: number of devices in the array 406 * @n_success: number of devices mapped successfully 407 * 408 * @n_success returns information to the caller how many devices from 409 * the start of the array have mapped the buffer successfully. It can 410 * be passed into a subsequent retry call to skip those devices. For 411 * the first call the caller should initialize it to 0. 412 * 413 * If the ioctl completes with return code 0 (success), n_success == 414 * n_devices. 415 */ 416 struct kfd_ioctl_map_memory_to_gpu_args { 417 __u64 handle; /* to KFD */ 418 __u64 device_ids_array_ptr; /* to KFD */ 419 __u32 n_devices; /* to KFD */ 420 __u32 n_success; /* to/from KFD */ 421 }; 422 423 /* Unmap memory from one or more GPUs 424 * 425 * same arguments as for mapping 426 */ 427 struct kfd_ioctl_unmap_memory_from_gpu_args { 428 __u64 handle; /* to KFD */ 429 __u64 device_ids_array_ptr; /* to KFD */ 430 __u32 n_devices; /* to KFD */ 431 __u32 n_success; /* to/from KFD */ 432 }; 433 434 /* Allocate GWS for specific queue 435 * 436 * @queue_id: queue's id that GWS is allocated for 437 * @num_gws: how many GWS to allocate 438 * @first_gws: index of the first GWS allocated. 439 * only support contiguous GWS allocation 440 */ 441 struct kfd_ioctl_alloc_queue_gws_args { 442 __u32 queue_id; /* to KFD */ 443 __u32 num_gws; /* to KFD */ 444 __u32 first_gws; /* from KFD */ 445 __u32 pad; 446 }; 447 448 struct kfd_ioctl_get_dmabuf_info_args { 449 __u64 size; /* from KFD */ 450 __u64 metadata_ptr; /* to KFD */ 451 __u32 metadata_size; /* to KFD (space allocated by user) 452 * from KFD (actual metadata size) 453 */ 454 __u32 gpu_id; /* from KFD */ 455 __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */ 456 __u32 dmabuf_fd; /* to KFD */ 457 }; 458 459 struct kfd_ioctl_import_dmabuf_args { 460 __u64 va_addr; /* to KFD */ 461 __u64 handle; /* from KFD */ 462 __u32 gpu_id; /* to KFD */ 463 __u32 dmabuf_fd; /* to KFD */ 464 }; 465 466 /* 467 * KFD SMI(System Management Interface) events 468 */ 469 enum kfd_smi_event { 470 KFD_SMI_EVENT_NONE = 0, /* not used */ 471 KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */ 472 KFD_SMI_EVENT_THERMAL_THROTTLE = 2, 473 KFD_SMI_EVENT_GPU_PRE_RESET = 3, 474 KFD_SMI_EVENT_GPU_POST_RESET = 4, 475 KFD_SMI_EVENT_MIGRATE_START = 5, 476 KFD_SMI_EVENT_MIGRATE_END = 6, 477 KFD_SMI_EVENT_PAGE_FAULT_START = 7, 478 KFD_SMI_EVENT_PAGE_FAULT_END = 8, 479 KFD_SMI_EVENT_QUEUE_EVICTION = 9, 480 KFD_SMI_EVENT_QUEUE_RESTORE = 10, 481 KFD_SMI_EVENT_UNMAP_FROM_GPU = 11, 482 483 /* 484 * max event number, as a flag bit to get events from all processes, 485 * this requires super user permission, otherwise will not be able to 486 * receive event from any process. Without this flag to receive events 487 * from same process. 488 */ 489 KFD_SMI_EVENT_ALL_PROCESS = 64 490 }; 491 492 enum KFD_MIGRATE_TRIGGERS { 493 KFD_MIGRATE_TRIGGER_PREFETCH, 494 KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, 495 KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU, 496 KFD_MIGRATE_TRIGGER_TTM_EVICTION 497 }; 498 499 enum KFD_QUEUE_EVICTION_TRIGGERS { 500 KFD_QUEUE_EVICTION_TRIGGER_SVM, 501 KFD_QUEUE_EVICTION_TRIGGER_USERPTR, 502 KFD_QUEUE_EVICTION_TRIGGER_TTM, 503 KFD_QUEUE_EVICTION_TRIGGER_SUSPEND, 504 KFD_QUEUE_EVICTION_CRIU_CHECKPOINT, 505 KFD_QUEUE_EVICTION_CRIU_RESTORE 506 }; 507 508 enum KFD_SVM_UNMAP_TRIGGERS { 509 KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY, 510 KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE, 511 KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU 512 }; 513 514 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) 515 #define KFD_SMI_EVENT_MSG_SIZE 96 516 517 struct kfd_ioctl_smi_events_args { 518 __u32 gpuid; /* to KFD */ 519 __u32 anon_fd; /* from KFD */ 520 }; 521 522 /************************************************************************************************** 523 * CRIU IOCTLs (Checkpoint Restore In Userspace) 524 * 525 * When checkpointing a process, the userspace application will perform: 526 * 1. PROCESS_INFO op to determine current process information. This pauses execution and evicts 527 * all the queues. 528 * 2. CHECKPOINT op to checkpoint process contents (BOs, queues, events, svm-ranges) 529 * 3. UNPAUSE op to un-evict all the queues 530 * 531 * When restoring a process, the CRIU userspace application will perform: 532 * 533 * 1. RESTORE op to restore process contents 534 * 2. RESUME op to start the process 535 * 536 * Note: Queues are forced into an evicted state after a successful PROCESS_INFO. User 537 * application needs to perform an UNPAUSE operation after calling PROCESS_INFO. 538 */ 539 540 enum kfd_criu_op { 541 KFD_CRIU_OP_PROCESS_INFO, 542 KFD_CRIU_OP_CHECKPOINT, 543 KFD_CRIU_OP_UNPAUSE, 544 KFD_CRIU_OP_RESTORE, 545 KFD_CRIU_OP_RESUME, 546 }; 547 548 /** 549 * kfd_ioctl_criu_args - Arguments perform CRIU operation 550 * @devices: [in/out] User pointer to memory location for devices information. 551 * This is an array of type kfd_criu_device_bucket. 552 * @bos: [in/out] User pointer to memory location for BOs information 553 * This is an array of type kfd_criu_bo_bucket. 554 * @priv_data: [in/out] User pointer to memory location for private data 555 * @priv_data_size: [in/out] Size of priv_data in bytes 556 * @num_devices: [in/out] Number of GPUs used by process. Size of @devices array. 557 * @num_bos [in/out] Number of BOs used by process. Size of @bos array. 558 * @num_objects: [in/out] Number of objects used by process. Objects are opaque to 559 * user application. 560 * @pid: [in/out] PID of the process being checkpointed 561 * @op [in] Type of operation (kfd_criu_op) 562 * 563 * Return: 0 on success, -errno on failure 564 */ 565 struct kfd_ioctl_criu_args { 566 __u64 devices; /* Used during ops: CHECKPOINT, RESTORE */ 567 __u64 bos; /* Used during ops: CHECKPOINT, RESTORE */ 568 __u64 priv_data; /* Used during ops: CHECKPOINT, RESTORE */ 569 __u64 priv_data_size; /* Used during ops: PROCESS_INFO, RESTORE */ 570 __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */ 571 __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */ 572 __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */ 573 __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */ 574 __u32 op; 575 }; 576 577 struct kfd_criu_device_bucket { 578 __u32 user_gpu_id; 579 __u32 actual_gpu_id; 580 __u32 drm_fd; 581 __u32 pad; 582 }; 583 584 struct kfd_criu_bo_bucket { 585 __u64 addr; 586 __u64 size; 587 __u64 offset; 588 __u64 restored_offset; /* During restore, updated offset for BO */ 589 __u32 gpu_id; /* This is the user_gpu_id */ 590 __u32 alloc_flags; 591 __u32 dmabuf_fd; 592 __u32 pad; 593 }; 594 595 /* CRIU IOCTLs - END */ 596 /**************************************************************************************************/ 597 598 /* Register offset inside the remapped mmio page 599 */ 600 enum kfd_mmio_remap { 601 KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, 602 KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, 603 }; 604 605 /* Guarantee host access to memory */ 606 #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 607 /* Fine grained coherency between all devices with access */ 608 #define KFD_IOCTL_SVM_FLAG_COHERENT 0x00000002 609 /* Use any GPU in same hive as preferred device */ 610 #define KFD_IOCTL_SVM_FLAG_HIVE_LOCAL 0x00000004 611 /* GPUs only read, allows replication */ 612 #define KFD_IOCTL_SVM_FLAG_GPU_RO 0x00000008 613 /* Allow execution on GPU */ 614 #define KFD_IOCTL_SVM_FLAG_GPU_EXEC 0x00000010 615 /* GPUs mostly read, may allow similar optimizations as RO, but writes fault */ 616 #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x00000020 617 /* Keep GPU memory mapping always valid as if XNACK is disable */ 618 #define KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED 0x00000040 619 620 /** 621 * kfd_ioctl_svm_op - SVM ioctl operations 622 * 623 * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes 624 * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes 625 */ 626 enum kfd_ioctl_svm_op { 627 KFD_IOCTL_SVM_OP_SET_ATTR, 628 KFD_IOCTL_SVM_OP_GET_ATTR 629 }; 630 631 /** kfd_ioctl_svm_location - Enum for preferred and prefetch locations 632 * 633 * GPU IDs are used to specify GPUs as preferred and prefetch locations. 634 * Below definitions are used for system memory or for leaving the preferred 635 * location unspecified. 636 */ 637 enum kfd_ioctl_svm_location { 638 KFD_IOCTL_SVM_LOCATION_SYSMEM = 0, 639 KFD_IOCTL_SVM_LOCATION_UNDEFINED = 0xffffffff 640 }; 641 642 /** 643 * kfd_ioctl_svm_attr_type - SVM attribute types 644 * 645 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for 646 * system memory 647 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: gpuid of the prefetch location, 0 for 648 * system memory. Setting this triggers an 649 * immediate prefetch (migration). 650 * @KFD_IOCTL_SVM_ATTR_ACCESS: 651 * @KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: 652 * @KFD_IOCTL_SVM_ATTR_NO_ACCESS: specify memory access for the gpuid given 653 * by the attribute value 654 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS: bitmask of flags to set (see 655 * KFD_IOCTL_SVM_FLAG_...) 656 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS: bitmask of flags to clear 657 * @KFD_IOCTL_SVM_ATTR_GRANULARITY: migration granularity 658 * (log2 num pages) 659 */ 660 enum kfd_ioctl_svm_attr_type { 661 KFD_IOCTL_SVM_ATTR_PREFERRED_LOC, 662 KFD_IOCTL_SVM_ATTR_PREFETCH_LOC, 663 KFD_IOCTL_SVM_ATTR_ACCESS, 664 KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE, 665 KFD_IOCTL_SVM_ATTR_NO_ACCESS, 666 KFD_IOCTL_SVM_ATTR_SET_FLAGS, 667 KFD_IOCTL_SVM_ATTR_CLR_FLAGS, 668 KFD_IOCTL_SVM_ATTR_GRANULARITY 669 }; 670 671 /** 672 * kfd_ioctl_svm_attribute - Attributes as pairs of type and value 673 * 674 * The meaning of the @value depends on the attribute type. 675 * 676 * @type: attribute type (see enum @kfd_ioctl_svm_attr_type) 677 * @value: attribute value 678 */ 679 struct kfd_ioctl_svm_attribute { 680 __u32 type; 681 __u32 value; 682 }; 683 684 /** 685 * kfd_ioctl_svm_args - Arguments for SVM ioctl 686 * 687 * @op specifies the operation to perform (see enum 688 * @kfd_ioctl_svm_op). @start_addr and @size are common for all 689 * operations. 690 * 691 * A variable number of attributes can be given in @attrs. 692 * @nattr specifies the number of attributes. New attributes can be 693 * added in the future without breaking the ABI. If unknown attributes 694 * are given, the function returns -EINVAL. 695 * 696 * @KFD_IOCTL_SVM_OP_SET_ATTR sets attributes for a virtual address 697 * range. It may overlap existing virtual address ranges. If it does, 698 * the existing ranges will be split such that the attribute changes 699 * only apply to the specified address range. 700 * 701 * @KFD_IOCTL_SVM_OP_GET_ATTR returns the intersection of attributes 702 * over all memory in the given range and returns the result as the 703 * attribute value. If different pages have different preferred or 704 * prefetch locations, 0xffffffff will be returned for 705 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or 706 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For 707 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be 708 * aggregated by bitwise AND. That means, a flag will be set in the 709 * output, if that flag is set for all pages in the range. For 710 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be 711 * aggregated by bitwise NOR. That means, a flag will be set in the 712 * output, if that flag is clear for all pages in the range. 713 * The minimum migration granularity throughout the range will be 714 * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY. 715 * 716 * Querying of accessibility attributes works by initializing the 717 * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the 718 * GPUID being queried. Multiple attributes can be given to allow 719 * querying multiple GPUIDs. The ioctl function overwrites the 720 * attribute type to indicate the access for the specified GPU. 721 */ 722 struct kfd_ioctl_svm_args { 723 __u64 start_addr; 724 __u64 size; 725 __u32 op; 726 __u32 nattr; 727 /* Variable length array of attributes */ 728 struct kfd_ioctl_svm_attribute attrs[]; 729 }; 730 731 /** 732 * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode 733 * 734 * @xnack_enabled: [in/out] Whether to enable XNACK mode for this process 735 * 736 * @xnack_enabled indicates whether recoverable page faults should be 737 * enabled for the current process. 0 means disabled, positive means 738 * enabled, negative means leave unchanged. If enabled, virtual address 739 * translations on GFXv9 and later AMD GPUs can return XNACK and retry 740 * the access until a valid PTE is available. This is used to implement 741 * device page faults. 742 * 743 * On output, @xnack_enabled returns the (new) current mode (0 or 744 * positive). Therefore, a negative input value can be used to query 745 * the current mode without changing it. 746 * 747 * The XNACK mode fundamentally changes the way SVM managed memory works 748 * in the driver, with subtle effects on application performance and 749 * functionality. 750 * 751 * Enabling XNACK mode requires shader programs to be compiled 752 * differently. Furthermore, not all GPUs support changing the mode 753 * per-process. Therefore changing the mode is only allowed while no 754 * user mode queues exist in the process. This ensure that no shader 755 * code is running that may be compiled for the wrong mode. And GPUs 756 * that cannot change to the requested mode will prevent the XNACK 757 * mode from occurring. All GPUs used by the process must be in the 758 * same XNACK mode. 759 * 760 * GFXv8 or older GPUs do not support 48 bit virtual addresses or SVM. 761 * Therefore those GPUs are not considered for the XNACK mode switch. 762 * 763 * Return: 0 on success, -errno on failure 764 */ 765 struct kfd_ioctl_set_xnack_mode_args { 766 __s32 xnack_enabled; 767 }; 768 769 #define AMDKFD_IOCTL_BASE 'K' 770 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 771 #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 772 #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 773 #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 774 775 #define AMDKFD_IOC_GET_VERSION \ 776 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 777 778 #define AMDKFD_IOC_CREATE_QUEUE \ 779 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 780 781 #define AMDKFD_IOC_DESTROY_QUEUE \ 782 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 783 784 #define AMDKFD_IOC_SET_MEMORY_POLICY \ 785 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 786 787 #define AMDKFD_IOC_GET_CLOCK_COUNTERS \ 788 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 789 790 #define AMDKFD_IOC_GET_PROCESS_APERTURES \ 791 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 792 793 #define AMDKFD_IOC_UPDATE_QUEUE \ 794 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 795 796 #define AMDKFD_IOC_CREATE_EVENT \ 797 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 798 799 #define AMDKFD_IOC_DESTROY_EVENT \ 800 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 801 802 #define AMDKFD_IOC_SET_EVENT \ 803 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 804 805 #define AMDKFD_IOC_RESET_EVENT \ 806 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 807 808 #define AMDKFD_IOC_WAIT_EVENTS \ 809 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 810 811 #define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \ 812 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 813 814 #define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \ 815 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 816 817 #define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \ 818 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 819 820 #define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \ 821 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 822 823 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ 824 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) 825 826 #define AMDKFD_IOC_GET_TILE_CONFIG \ 827 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) 828 829 #define AMDKFD_IOC_SET_TRAP_HANDLER \ 830 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) 831 832 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \ 833 AMDKFD_IOWR(0x14, \ 834 struct kfd_ioctl_get_process_apertures_new_args) 835 836 #define AMDKFD_IOC_ACQUIRE_VM \ 837 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) 838 839 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \ 840 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) 841 842 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \ 843 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) 844 845 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \ 846 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) 847 848 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \ 849 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) 850 851 #define AMDKFD_IOC_SET_CU_MASK \ 852 AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) 853 854 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ 855 AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) 856 857 #define AMDKFD_IOC_GET_DMABUF_INFO \ 858 AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) 859 860 #define AMDKFD_IOC_IMPORT_DMABUF \ 861 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) 862 863 #define AMDKFD_IOC_ALLOC_QUEUE_GWS \ 864 AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args) 865 866 #define AMDKFD_IOC_SMI_EVENTS \ 867 AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args) 868 869 #define AMDKFD_IOC_SVM AMDKFD_IOWR(0x20, struct kfd_ioctl_svm_args) 870 871 #define AMDKFD_IOC_SET_XNACK_MODE \ 872 AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args) 873 874 #define AMDKFD_IOC_CRIU_OP \ 875 AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args) 876 877 #define AMDKFD_IOC_AVAILABLE_MEMORY \ 878 AMDKFD_IOWR(0x23, struct kfd_ioctl_get_available_memory_args) 879 880 #define AMDKFD_COMMAND_START 0x01 881 #define AMDKFD_COMMAND_END 0x24 882 883 #endif 884