1 /*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #ifndef __MIPS_JZ4740_TIMER_H__
17 #define __MIPS_JZ4740_TIMER_H__
18
19 #include <linux/module.h>
20 #include <linux/io.h>
21
22 #define JZ_REG_TIMER_STOP 0x0C
23 #define JZ_REG_TIMER_STOP_SET 0x1C
24 #define JZ_REG_TIMER_STOP_CLEAR 0x2C
25 #define JZ_REG_TIMER_ENABLE 0x00
26 #define JZ_REG_TIMER_ENABLE_SET 0x04
27 #define JZ_REG_TIMER_ENABLE_CLEAR 0x08
28 #define JZ_REG_TIMER_FLAG 0x10
29 #define JZ_REG_TIMER_FLAG_SET 0x14
30 #define JZ_REG_TIMER_FLAG_CLEAR 0x18
31 #define JZ_REG_TIMER_MASK 0x20
32 #define JZ_REG_TIMER_MASK_SET 0x24
33 #define JZ_REG_TIMER_MASK_CLEAR 0x28
34
35 #define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
36 #define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
37 #define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
38 #define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
39
40 #define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
41 #define JZ_TIMER_IRQ_FULL(x) BIT(x)
42
43 #define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
44 #define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
45 #define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
46 #define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
47 #define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
48 #define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
49 #define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
50 #define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
51 #define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
52 #define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
53 #define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
54
55 #define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
56
57 #define JZ_TIMER_CTRL_SRC_EXT BIT(2)
58 #define JZ_TIMER_CTRL_SRC_RTC BIT(1)
59 #define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
60
61 extern void __iomem *jz4740_timer_base;
62 void __init jz4740_timer_init(void);
63
jz4740_timer_stop(unsigned int timer)64 static inline void jz4740_timer_stop(unsigned int timer)
65 {
66 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
67 }
68
jz4740_timer_start(unsigned int timer)69 static inline void jz4740_timer_start(unsigned int timer)
70 {
71 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
72 }
73
jz4740_timer_is_enabled(unsigned int timer)74 static inline bool jz4740_timer_is_enabled(unsigned int timer)
75 {
76 return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
77 }
78
jz4740_timer_enable(unsigned int timer)79 static inline void jz4740_timer_enable(unsigned int timer)
80 {
81 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
82 }
83
jz4740_timer_disable(unsigned int timer)84 static inline void jz4740_timer_disable(unsigned int timer)
85 {
86 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
87 }
88
89
jz4740_timer_set_period(unsigned int timer,uint16_t period)90 static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
91 {
92 writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
93 }
94
jz4740_timer_set_duty(unsigned int timer,uint16_t duty)95 static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
96 {
97 writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
98 }
99
jz4740_timer_set_count(unsigned int timer,uint16_t count)100 static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
101 {
102 writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
103 }
104
jz4740_timer_get_count(unsigned int timer)105 static inline uint16_t jz4740_timer_get_count(unsigned int timer)
106 {
107 return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
108 }
109
jz4740_timer_ack_full(unsigned int timer)110 static inline void jz4740_timer_ack_full(unsigned int timer)
111 {
112 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
113 }
114
jz4740_timer_irq_full_enable(unsigned int timer)115 static inline void jz4740_timer_irq_full_enable(unsigned int timer)
116 {
117 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
118 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
119 }
120
jz4740_timer_irq_full_disable(unsigned int timer)121 static inline void jz4740_timer_irq_full_disable(unsigned int timer)
122 {
123 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
124 }
125
jz4740_timer_set_ctrl(unsigned int timer,uint16_t ctrl)126 static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
127 {
128 writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
129 }
130
jz4740_timer_get_ctrl(unsigned int timer)131 static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
132 {
133 return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
134 }
135
136 #endif
137