1 /*
2  * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
3  *
4  * Chipset register definitions for IXP2400/2800 based systems.
5  *
6  * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7  *
8  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
9  *
10  * Copyright (C) 2002 Intel Corp.
11  * Copyright (C) 2003-2004 MontaVista Software, Inc.
12  *
13  *  This program is free software; you can redistribute  it and/or modify it
14  *  under  the terms of  the GNU General  Public License as published by the
15  *  Free Software Foundation;  either version 2 of the  License, or (at your
16  *  option) any later version.
17  */
18 #ifndef _IXP2000_REGS_H_
19 #define _IXP2000_REGS_H_
20 
21 /*
22  * IXP2000 linux memory map:
23  *
24  * virt		phys		size
25  * fb000000	db000000	16M		PCI CFG1
26  * fc000000	da000000	16M		PCI CFG0
27  * fd000000	d8000000	16M		PCI I/O
28  * fe[0-7]00000			8M		per-platform mappings
29  * fe900000	80000000	1M		SRAM #0 (first MB)
30  * fea00000	cb400000	1M		SCRATCH ring get/put
31  * feb00000	c8000000	1M		MSF
32  * fec00000	df000000	1M		PCI CSRs
33  * fed00000	de000000	1M		PCI CREG
34  * fee00000	d6000000	1M		INTCTL
35  * fef00000	c0000000	1M		CAP
36  */
37 
38 /*
39  * Static I/O regions.
40  *
41  * Most of the registers are clumped in 4K regions spread throughout
42  * the 0xc0000000 -> 0xc0100000 address range, but we just map in
43  * the whole range using a single 1 MB section instead of small
44  * 4K pages.
45  *
46  * CAP stands for CSR Access Proxy.
47  *
48  * If you change the virtual address of this mapping, please propagate
49  * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
50  * address of the UART located in this region.
51  */
52 
53 #define	IXP2000_CAP_PHYS_BASE		0xc0000000
54 #define	IXP2000_CAP_VIRT_BASE		0xfef00000
55 #define	IXP2000_CAP_SIZE		0x00100000
56 
57 /*
58  * Addresses for specific on-chip peripherals.
59  */
60 #define	IXP2000_SLOWPORT_CSR_VIRT_BASE	0xfef80000
61 #define	IXP2000_GLOBAL_REG_VIRT_BASE	0xfef04000
62 #define	IXP2000_UART_PHYS_BASE		0xc0030000
63 #define	IXP2000_UART_VIRT_BASE		0xfef30000
64 #define	IXP2000_TIMER_VIRT_BASE		0xfef20000
65 #define	IXP2000_UENGINE_CSR_VIRT_BASE	0xfef18000
66 #define	IXP2000_GPIO_VIRT_BASE		0xfef10000
67 
68 /*
69  * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
70  * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
71  * entry-macro.S, so if you ever change these please propagate
72  * the change.
73  */
74 #define IXP2000_INTCTL_PHYS_BASE	0xd6000000
75 #define	IXP2000_INTCTL_VIRT_BASE	0xfee00000
76 #define	IXP2000_INTCTL_SIZE		0x00100000
77 
78 #define IXP2000_PCI_CREG_PHYS_BASE	0xde000000
79 #define	IXP2000_PCI_CREG_VIRT_BASE	0xfed00000
80 #define	IXP2000_PCI_CREG_SIZE		0x00100000
81 
82 #define IXP2000_PCI_CSR_PHYS_BASE	0xdf000000
83 #define	IXP2000_PCI_CSR_VIRT_BASE	0xfec00000
84 #define	IXP2000_PCI_CSR_SIZE		0x00100000
85 
86 #define IXP2000_MSF_PHYS_BASE		0xc8000000
87 #define IXP2000_MSF_VIRT_BASE		0xfeb00000
88 #define IXP2000_MSF_SIZE		0x00100000
89 
90 #define IXP2000_SCRATCH_RING_PHYS_BASE	0xcb400000
91 #define IXP2000_SCRATCH_RING_VIRT_BASE	0xfea00000
92 #define IXP2000_SCRATCH_RING_SIZE	0x00100000
93 
94 #define IXP2000_SRAM0_PHYS_BASE		0x80000000
95 #define IXP2000_SRAM0_VIRT_BASE		0xfe900000
96 #define IXP2000_SRAM0_SIZE		0x00100000
97 
98 #define IXP2000_PCI_IO_PHYS_BASE	0xd8000000
99 #define	IXP2000_PCI_IO_VIRT_BASE	0xfd000000
100 #define IXP2000_PCI_IO_SIZE     	0x01000000
101 
102 #define IXP2000_PCI_CFG0_PHYS_BASE	0xda000000
103 #define IXP2000_PCI_CFG0_VIRT_BASE	0xfc000000
104 #define IXP2000_PCI_CFG0_SIZE   	0x01000000
105 
106 #define IXP2000_PCI_CFG1_PHYS_BASE	0xdb000000
107 #define IXP2000_PCI_CFG1_VIRT_BASE	0xfb000000
108 #define IXP2000_PCI_CFG1_SIZE		0x01000000
109 
110 /*
111  * Timers
112  */
113 #define	IXP2000_TIMER_REG(x)		((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
114 /* Timer control */
115 #define	IXP2000_T1_CTL			IXP2000_TIMER_REG(0x00)
116 #define	IXP2000_T2_CTL			IXP2000_TIMER_REG(0x04)
117 #define	IXP2000_T3_CTL			IXP2000_TIMER_REG(0x08)
118 #define	IXP2000_T4_CTL			IXP2000_TIMER_REG(0x0c)
119 /* Store initial value */
120 #define	IXP2000_T1_CLD			IXP2000_TIMER_REG(0x10)
121 #define	IXP2000_T2_CLD			IXP2000_TIMER_REG(0x14)
122 #define	IXP2000_T3_CLD			IXP2000_TIMER_REG(0x18)
123 #define	IXP2000_T4_CLD			IXP2000_TIMER_REG(0x1c)
124 /* Read current value */
125 #define	IXP2000_T1_CSR			IXP2000_TIMER_REG(0x20)
126 #define	IXP2000_T2_CSR			IXP2000_TIMER_REG(0x24)
127 #define	IXP2000_T3_CSR			IXP2000_TIMER_REG(0x28)
128 #define	IXP2000_T4_CSR			IXP2000_TIMER_REG(0x2c)
129 /* Clear associated timer interrupt */
130 #define	IXP2000_T1_CLR			IXP2000_TIMER_REG(0x30)
131 #define	IXP2000_T2_CLR			IXP2000_TIMER_REG(0x34)
132 #define	IXP2000_T3_CLR			IXP2000_TIMER_REG(0x38)
133 #define	IXP2000_T4_CLR			IXP2000_TIMER_REG(0x3c)
134 /* Timer watchdog enable for T4 */
135 #define	IXP2000_TWDE			IXP2000_TIMER_REG(0x40)
136 
137 #define	WDT_ENABLE			0x00000001
138 #define	TIMER_DIVIDER_256		0x00000008
139 #define	TIMER_ENABLE			0x00000080
140 #define	IRQ_MASK_TIMER1         	(1 << 4)
141 
142 /*
143  * Interrupt controller registers
144  */
145 #define IXP2000_INTCTL_REG(x)		(volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
146 #define IXP2000_IRQ_STATUS		IXP2000_INTCTL_REG(0x08)
147 #define IXP2000_IRQ_ENABLE		IXP2000_INTCTL_REG(0x10)
148 #define IXP2000_IRQ_ENABLE_SET		IXP2000_INTCTL_REG(0x10)
149 #define IXP2000_IRQ_ENABLE_CLR		IXP2000_INTCTL_REG(0x18)
150 #define IXP2000_FIQ_ENABLE_CLR		IXP2000_INTCTL_REG(0x14)
151 #define IXP2000_IRQ_ERR_STATUS		IXP2000_INTCTL_REG(0x24)
152 #define IXP2000_IRQ_ERR_ENABLE_SET	IXP2000_INTCTL_REG(0x2c)
153 #define IXP2000_FIQ_ERR_ENABLE_CLR	IXP2000_INTCTL_REG(0x30)
154 #define IXP2000_IRQ_ERR_ENABLE_CLR	IXP2000_INTCTL_REG(0x34)
155 #define IXP2000_IRQ_THD_RAW_STATUS_A_0	IXP2000_INTCTL_REG(0x60)
156 #define IXP2000_IRQ_THD_RAW_STATUS_A_1	IXP2000_INTCTL_REG(0x64)
157 #define IXP2000_IRQ_THD_RAW_STATUS_A_2	IXP2000_INTCTL_REG(0x68)
158 #define IXP2000_IRQ_THD_RAW_STATUS_A_3	IXP2000_INTCTL_REG(0x6c)
159 #define IXP2000_IRQ_THD_RAW_STATUS_B_0	IXP2000_INTCTL_REG(0x80)
160 #define IXP2000_IRQ_THD_RAW_STATUS_B_1	IXP2000_INTCTL_REG(0x84)
161 #define IXP2000_IRQ_THD_RAW_STATUS_B_2	IXP2000_INTCTL_REG(0x88)
162 #define IXP2000_IRQ_THD_RAW_STATUS_B_3	IXP2000_INTCTL_REG(0x8c)
163 #define IXP2000_IRQ_THD_STATUS_A_0	IXP2000_INTCTL_REG(0xe0)
164 #define IXP2000_IRQ_THD_STATUS_A_1	IXP2000_INTCTL_REG(0xe4)
165 #define IXP2000_IRQ_THD_STATUS_A_2	IXP2000_INTCTL_REG(0xe8)
166 #define IXP2000_IRQ_THD_STATUS_A_3	IXP2000_INTCTL_REG(0xec)
167 #define IXP2000_IRQ_THD_STATUS_B_0	IXP2000_INTCTL_REG(0x100)
168 #define IXP2000_IRQ_THD_STATUS_B_1	IXP2000_INTCTL_REG(0x104)
169 #define IXP2000_IRQ_THD_STATUS_B_2	IXP2000_INTCTL_REG(0x108)
170 #define IXP2000_IRQ_THD_STATUS_B_3	IXP2000_INTCTL_REG(0x10c)
171 #define IXP2000_IRQ_THD_ENABLE_SET_A_0	IXP2000_INTCTL_REG(0x160)
172 #define IXP2000_IRQ_THD_ENABLE_SET_A_1	IXP2000_INTCTL_REG(0x164)
173 #define IXP2000_IRQ_THD_ENABLE_SET_A_2	IXP2000_INTCTL_REG(0x168)
174 #define IXP2000_IRQ_THD_ENABLE_SET_A_3	IXP2000_INTCTL_REG(0x16c)
175 #define IXP2000_IRQ_THD_ENABLE_SET_B_0	IXP2000_INTCTL_REG(0x180)
176 #define IXP2000_IRQ_THD_ENABLE_SET_B_1	IXP2000_INTCTL_REG(0x184)
177 #define IXP2000_IRQ_THD_ENABLE_SET_B_2	IXP2000_INTCTL_REG(0x188)
178 #define IXP2000_IRQ_THD_ENABLE_SET_B_3	IXP2000_INTCTL_REG(0x18c)
179 #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0	IXP2000_INTCTL_REG(0x1e0)
180 #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1	IXP2000_INTCTL_REG(0x1e4)
181 #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2	IXP2000_INTCTL_REG(0x1e8)
182 #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3	IXP2000_INTCTL_REG(0x1ec)
183 #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0	IXP2000_INTCTL_REG(0x200)
184 #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1	IXP2000_INTCTL_REG(0x204)
185 #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2	IXP2000_INTCTL_REG(0x208)
186 #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3	IXP2000_INTCTL_REG(0x20c)
187 
188 /*
189  * Mask of valid IRQs in the 32-bit IRQ register. We use
190  * this to mark certain IRQs as being invalid.
191  */
192 #define	IXP2000_VALID_IRQ_MASK	0x0f0fffff
193 
194 /*
195  * PCI config register access from core
196  */
197 #define IXP2000_PCI_CREG(x)		(volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
198 #define IXP2000_PCI_CMDSTAT 		IXP2000_PCI_CREG(0x04)
199 #define IXP2000_PCI_CSR_BAR		IXP2000_PCI_CREG(0x10)
200 #define IXP2000_PCI_SRAM_BAR		IXP2000_PCI_CREG(0x14)
201 #define IXP2000_PCI_SDRAM_BAR		IXP2000_PCI_CREG(0x18)
202 
203 /*
204  * PCI CSRs
205  */
206 #define IXP2000_PCI_CSR(x)		(volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
207 
208 /*
209  * PCI outbound interrupts
210  */
211 #define IXP2000_PCI_OUT_INT_STATUS	IXP2000_PCI_CSR(0x30)
212 #define IXP2000_PCI_OUT_INT_MASK	IXP2000_PCI_CSR(0x34)
213 /*
214  * PCI communications
215  */
216 #define IXP2000_PCI_MAILBOX0		IXP2000_PCI_CSR(0x50)
217 #define IXP2000_PCI_MAILBOX1		IXP2000_PCI_CSR(0x54)
218 #define IXP2000_PCI_MAILBOX2		IXP2000_PCI_CSR(0x58)
219 #define IXP2000_PCI_MAILBOX3		IXP2000_PCI_CSR(0x5C)
220 #define IXP2000_XSCALE_DOORBELL		IXP2000_PCI_CSR(0x60)
221 #define IXP2000_XSCALE_DOORBELL_SETUP	IXP2000_PCI_CSR(0x64)
222 #define IXP2000_PCI_DOORBELL		IXP2000_PCI_CSR(0x70)
223 #define IXP2000_PCI_DOORBELL_SETUP	IXP2000_PCI_CSR(0x74)
224 
225 /*
226  * DMA engines
227  */
228 #define IXP2000_PCI_CH1_BYTE_CNT	IXP2000_PCI_CSR(0x80)
229 #define IXP2000_PCI_CH1_ADDR		IXP2000_PCI_CSR(0x84)
230 #define IXP2000_PCI_CH1_DRAM_ADDR	IXP2000_PCI_CSR(0x88)
231 #define IXP2000_PCI_CH1_DESC_PTR	IXP2000_PCI_CSR(0x8C)
232 #define IXP2000_PCI_CH1_CNTRL		IXP2000_PCI_CSR(0x90)
233 #define IXP2000_PCI_CH1_ME_PARAM	IXP2000_PCI_CSR(0x94)
234 #define IXP2000_PCI_CH2_BYTE_CNT	IXP2000_PCI_CSR(0xA0)
235 #define IXP2000_PCI_CH2_ADDR		IXP2000_PCI_CSR(0xA4)
236 #define IXP2000_PCI_CH2_DRAM_ADDR	IXP2000_PCI_CSR(0xA8)
237 #define IXP2000_PCI_CH2_DESC_PTR	IXP2000_PCI_CSR(0xAC)
238 #define IXP2000_PCI_CH2_CNTRL		IXP2000_PCI_CSR(0xB0)
239 #define IXP2000_PCI_CH2_ME_PARAM	IXP2000_PCI_CSR(0xB4)
240 #define IXP2000_PCI_CH3_BYTE_CNT	IXP2000_PCI_CSR(0xC0)
241 #define IXP2000_PCI_CH3_ADDR		IXP2000_PCI_CSR(0xC4)
242 #define IXP2000_PCI_CH3_DRAM_ADDR	IXP2000_PCI_CSR(0xC8)
243 #define IXP2000_PCI_CH3_DESC_PTR	IXP2000_PCI_CSR(0xCC)
244 #define IXP2000_PCI_CH3_CNTRL		IXP2000_PCI_CSR(0xD0)
245 #define IXP2000_PCI_CH3_ME_PARAM	IXP2000_PCI_CSR(0xD4)
246 #define IXP2000_DMA_INF_MODE		IXP2000_PCI_CSR(0xE0)
247 /*
248  * Size masks for BARs
249  */
250 #define IXP2000_PCI_SRAM_BASE_ADDR_MASK	IXP2000_PCI_CSR(0xFC)
251 #define IXP2000_PCI_DRAM_BASE_ADDR_MASK	IXP2000_PCI_CSR(0x100)
252 /*
253  * Control and uEngine related
254  */
255 #define IXP2000_PCI_CONTROL		IXP2000_PCI_CSR(0x13C)
256 #define IXP2000_PCI_ADDR_EXT		IXP2000_PCI_CSR(0x140)
257 #define IXP2000_PCI_ME_PUSH_STATUS	IXP2000_PCI_CSR(0x148)
258 #define IXP2000_PCI_ME_PUSH_EN		IXP2000_PCI_CSR(0x14C)
259 #define IXP2000_PCI_ERR_STATUS		IXP2000_PCI_CSR(0x150)
260 #define IXP2000_PCI_ERR_ENABLE		IXP2000_PCI_CSR(0x154)
261 /*
262  * Inbound PCI interrupt control
263  */
264 #define IXP2000_PCI_XSCALE_INT_STATUS	IXP2000_PCI_CSR(0x158)
265 #define IXP2000_PCI_XSCALE_INT_ENABLE	IXP2000_PCI_CSR(0x15C)
266 
267 #define IXP2000_PCICNTL_PNR		(1<<17)	/* PCI not Reset bit of PCI_CONTROL */
268 #define IXP2000_PCICNTL_PCF		(1<<28)	/* PCI Central function bit */
269 #define IXP2000_XSCALE_INT		(1<<1)	/* Interrupt from XScale to PCI */
270 
271 /* These are from the IRQ register in the PCI ISR register */
272 #define PCI_CONTROL_BE_DEO		(1 << 22)	/* Big Endian Data Enable Out */
273 #define PCI_CONTROL_BE_DEI		(1 << 21)	/* Big Endian Data Enable In  */
274 #define PCI_CONTROL_BE_BEO		(1 << 20)	/* Big Endian Byte Enable Out */
275 #define PCI_CONTROL_BE_BEI		(1 << 19)	/* Big Endian Byte Enable In  */
276 #define PCI_CONTROL_IEE			(1 << 17)	/* I/O cycle Endian swap Enable */
277 
278 #define IXP2000_PCI_RST_REL		(1 << 2)
279 #define CFG_RST_DIR			(*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
280 #define CFG_PCI_BOOT_HOST		(1 << 2)
281 #define CFG_BOOT_PROM			(1 << 1)
282 
283 /*
284  * SlowPort CSRs
285  *
286  * The slowport is used to access things like flash, SONET framer control
287  * ports, slave microprocessors, CPLDs, and others of chip memory mapped
288  * peripherals.
289  */
290 #define	SLOWPORT_CSR(x)		(volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
291 
292 #define	IXP2000_SLOWPORT_CCR		SLOWPORT_CSR(0x00)
293 #define	IXP2000_SLOWPORT_WTC1		SLOWPORT_CSR(0x04)
294 #define	IXP2000_SLOWPORT_WTC2		SLOWPORT_CSR(0x08)
295 #define	IXP2000_SLOWPORT_RTC1		SLOWPORT_CSR(0x0c)
296 #define	IXP2000_SLOWPORT_RTC2		SLOWPORT_CSR(0x10)
297 #define	IXP2000_SLOWPORT_FSR		SLOWPORT_CSR(0x14)
298 #define	IXP2000_SLOWPORT_PCR		SLOWPORT_CSR(0x18)
299 #define	IXP2000_SLOWPORT_ADC		SLOWPORT_CSR(0x1C)
300 #define	IXP2000_SLOWPORT_FAC		SLOWPORT_CSR(0x20)
301 #define	IXP2000_SLOWPORT_FRM		SLOWPORT_CSR(0x24)
302 #define	IXP2000_SLOWPORT_FIN		SLOWPORT_CSR(0x28)
303 
304 /*
305  * CCR values.
306  * The CCR configures the clock division for the slowport interface.
307  */
308 #define	SLOWPORT_CCR_DIV_1		0x00
309 #define	SLOWPORT_CCR_DIV_2		0x01
310 #define	SLOWPORT_CCR_DIV_4		0x02
311 #define	SLOWPORT_CCR_DIV_6		0x03
312 #define	SLOWPORT_CCR_DIV_8		0x04
313 #define	SLOWPORT_CCR_DIV_10		0x05
314 #define	SLOWPORT_CCR_DIV_12		0x06
315 #define	SLOWPORT_CCR_DIV_14		0x07
316 #define	SLOWPORT_CCR_DIV_16		0x08
317 #define	SLOWPORT_CCR_DIV_18		0x09
318 #define	SLOWPORT_CCR_DIV_20		0x0a
319 #define	SLOWPORT_CCR_DIV_22		0x0b
320 #define	SLOWPORT_CCR_DIV_24		0x0c
321 #define	SLOWPORT_CCR_DIV_26		0x0d
322 #define	SLOWPORT_CCR_DIV_28		0x0e
323 #define	SLOWPORT_CCR_DIV_30		0x0f
324 
325 /*
326  * PCR values.  PCR configure the mode of the interface.
327  */
328 #define	SLOWPORT_MODE_FLASH		0x00
329 #define	SLOWPORT_MODE_LUCENT		0x01
330 #define	SLOWPORT_MODE_PMC_SIERRA	0x02
331 #define	SLOWPORT_MODE_INTEL_UP		0x03
332 #define	SLOWPORT_MODE_MOTOROLA_UP	0x04
333 
334 /*
335  * ADC values.  Defines data and address bus widths.
336  */
337 #define	SLOWPORT_ADDR_WIDTH_8		0x00
338 #define	SLOWPORT_ADDR_WIDTH_16		0x01
339 #define	SLOWPORT_ADDR_WIDTH_24		0x02
340 #define	SLOWPORT_ADDR_WIDTH_32		0x03
341 #define	SLOWPORT_DATA_WIDTH_8		0x00
342 #define	SLOWPORT_DATA_WIDTH_16		0x10
343 #define	SLOWPORT_DATA_WIDTH_24		0x20
344 #define	SLOWPORT_DATA_WIDTH_32		0x30
345 
346 /*
347  * Masks and shifts for various fields in the WTC and RTC registers.
348  */
349 #define	SLOWPORT_WRTC_MASK_HD		0x0003
350 #define	SLOWPORT_WRTC_MASK_PW		0x003c
351 #define	SLOWPORT_WRTC_MASK_SU		0x03c0
352 
353 #define	SLOWPORT_WRTC_SHIFT_HD		0x00
354 #define	SLOWPORT_WRTC_SHIFT_SU		0x02
355 #define	SLOWPORT_WRTC_SHFIT_PW		0x06
356 
357 
358 /*
359  * GPIO registers & GPIO interface.
360  */
361 #define IXP2000_GPIO_REG(x)		((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
362 #define IXP2000_GPIO_PLR		IXP2000_GPIO_REG(0x00)
363 #define IXP2000_GPIO_PDPR		IXP2000_GPIO_REG(0x04)
364 #define IXP2000_GPIO_PDSR		IXP2000_GPIO_REG(0x08)
365 #define IXP2000_GPIO_PDCR		IXP2000_GPIO_REG(0x0c)
366 #define IXP2000_GPIO_POPR		IXP2000_GPIO_REG(0x10)
367 #define IXP2000_GPIO_POSR		IXP2000_GPIO_REG(0x14)
368 #define IXP2000_GPIO_POCR		IXP2000_GPIO_REG(0x18)
369 #define IXP2000_GPIO_REDR		IXP2000_GPIO_REG(0x1c)
370 #define IXP2000_GPIO_FEDR		IXP2000_GPIO_REG(0x20)
371 #define IXP2000_GPIO_EDSR		IXP2000_GPIO_REG(0x24)
372 #define IXP2000_GPIO_LSHR		IXP2000_GPIO_REG(0x28)
373 #define IXP2000_GPIO_LSLR		IXP2000_GPIO_REG(0x2c)
374 #define IXP2000_GPIO_LDSR		IXP2000_GPIO_REG(0x30)
375 #define IXP2000_GPIO_INER		IXP2000_GPIO_REG(0x34)
376 #define IXP2000_GPIO_INSR		IXP2000_GPIO_REG(0x38)
377 #define IXP2000_GPIO_INCR		IXP2000_GPIO_REG(0x3c)
378 #define IXP2000_GPIO_INST		IXP2000_GPIO_REG(0x40)
379 
380 /*
381  * "Global" registers...whatever that's supposed to mean.
382  */
383 #define GLOBAL_REG_BASE			(IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
384 #define GLOBAL_REG(x)			(volatile unsigned long*)(GLOBAL_REG_BASE | (x))
385 
386 #define IXP2000_MAJ_PROD_TYPE_MASK	0x001F0000
387 #define IXP2000_MAJ_PROD_TYPE_IXP2000	0x00000000
388 #define IXP2000_MIN_PROD_TYPE_MASK 	0x0000FF00
389 #define IXP2000_MIN_PROD_TYPE_IXP2400	0x00000200
390 #define IXP2000_MIN_PROD_TYPE_IXP2850	0x00000100
391 #define IXP2000_MIN_PROD_TYPE_IXP2800	0x00000000
392 #define IXP2000_MAJ_REV_MASK	      	0x000000F0
393 #define IXP2000_MIN_REV_MASK	      	0x0000000F
394 #define IXP2000_PROD_ID_MASK		0xFFFFFFFF
395 
396 #define IXP2000_PRODUCT_ID		GLOBAL_REG(0x00)
397 #define IXP2000_MISC_CONTROL		GLOBAL_REG(0x04)
398 #define IXP2000_MSF_CLK_CNTRL  		GLOBAL_REG(0x08)
399 #define IXP2000_RESET0      		GLOBAL_REG(0x0c)
400 #define IXP2000_RESET1      		GLOBAL_REG(0x10)
401 #define IXP2000_CCR            		GLOBAL_REG(0x14)
402 #define	IXP2000_STRAP_OPTIONS  		GLOBAL_REG(0x18)
403 
404 #define	RSTALL				(1 << 16)
405 #define	WDT_RESET_ENABLE		0x01000000
406 
407 
408 /*
409  * MSF registers.  The IXP2400 and IXP2800 have somewhat different MSF
410  * units, but the registers that differ between the two don't overlap,
411  * so we can have one register list for both.
412  */
413 #define IXP2000_MSF_REG(x)			((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
414 #define IXP2000_MSF_RX_CONTROL			IXP2000_MSF_REG(0x0000)
415 #define IXP2000_MSF_TX_CONTROL			IXP2000_MSF_REG(0x0004)
416 #define IXP2000_MSF_INTERRUPT_STATUS		IXP2000_MSF_REG(0x0008)
417 #define IXP2000_MSF_INTERRUPT_ENABLE		IXP2000_MSF_REG(0x000c)
418 #define IXP2000_MSF_CSIX_TYPE_MAP		IXP2000_MSF_REG(0x0010)
419 #define IXP2000_MSF_FC_EGRESS_STATUS		IXP2000_MSF_REG(0x0014)
420 #define IXP2000_MSF_FC_INGRESS_STATUS		IXP2000_MSF_REG(0x0018)
421 #define IXP2000_MSF_HWM_CONTROL			IXP2000_MSF_REG(0x0024)
422 #define IXP2000_MSF_FC_STATUS_OVERRIDE		IXP2000_MSF_REG(0x0028)
423 #define IXP2000_MSF_CLOCK_CONTROL		IXP2000_MSF_REG(0x002c)
424 #define IXP2000_MSF_RX_PORT_MAP			IXP2000_MSF_REG(0x0040)
425 #define IXP2000_MSF_RBUF_ELEMENT_DONE		IXP2000_MSF_REG(0x0044)
426 #define IXP2000_MSF_RX_MPHY_POLL_LIMIT		IXP2000_MSF_REG(0x0048)
427 #define IXP2000_MSF_RX_CALENDAR_LENGTH		IXP2000_MSF_REG(0x0048)
428 #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0	IXP2000_MSF_REG(0x0050)
429 #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1	IXP2000_MSF_REG(0x0054)
430 #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2	IXP2000_MSF_REG(0x0058)
431 #define IXP2000_MSF_TX_SEQUENCE_0		IXP2000_MSF_REG(0x0060)
432 #define IXP2000_MSF_TX_SEQUENCE_1		IXP2000_MSF_REG(0x0064)
433 #define IXP2000_MSF_TX_SEQUENCE_2		IXP2000_MSF_REG(0x0068)
434 #define IXP2000_MSF_TX_MPHY_POLL_LIMIT		IXP2000_MSF_REG(0x0070)
435 #define IXP2000_MSF_TX_CALENDAR_LENGTH		IXP2000_MSF_REG(0x0070)
436 #define IXP2000_MSF_RX_UP_CONTROL_0		IXP2000_MSF_REG(0x0080)
437 #define IXP2000_MSF_RX_UP_CONTROL_1		IXP2000_MSF_REG(0x0084)
438 #define IXP2000_MSF_RX_UP_CONTROL_2		IXP2000_MSF_REG(0x0088)
439 #define IXP2000_MSF_RX_UP_CONTROL_3		IXP2000_MSF_REG(0x008c)
440 #define IXP2000_MSF_TX_UP_CONTROL_0		IXP2000_MSF_REG(0x0090)
441 #define IXP2000_MSF_TX_UP_CONTROL_1		IXP2000_MSF_REG(0x0094)
442 #define IXP2000_MSF_TX_UP_CONTROL_2		IXP2000_MSF_REG(0x0098)
443 #define IXP2000_MSF_TX_UP_CONTROL_3		IXP2000_MSF_REG(0x009c)
444 #define IXP2000_MSF_TRAIN_DATA			IXP2000_MSF_REG(0x00a0)
445 #define IXP2000_MSF_TRAIN_CALENDAR		IXP2000_MSF_REG(0x00a4)
446 #define IXP2000_MSF_TRAIN_FLOW_CONTROL		IXP2000_MSF_REG(0x00a8)
447 #define IXP2000_MSF_TX_CALENDAR_0		IXP2000_MSF_REG(0x1000)
448 #define IXP2000_MSF_RX_PORT_CALENDAR_STATUS	IXP2000_MSF_REG(0x1400)
449 
450 
451 #endif				/* _IXP2000_H_ */
452