1 /*******************************************************************************
2 
3   Intel PRO/10GbE Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5 
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9 
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14 
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21 
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 /* glue for the OS independent part of ixgb
30  * includes register access macros
31  */
32 
33 #ifndef _IXGB_OSDEP_H_
34 #define _IXGB_OSDEP_H_
35 
36 #include <linux/types.h>
37 #include <linux/delay.h>
38 #include <asm/io.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 
42 #undef ASSERT
43 #define ASSERT(x)	BUG_ON(!(x))
44 
45 #define ENTER() pr_debug("%s\n", __func__);
46 
47 #define IXGB_WRITE_REG(a, reg, value) ( \
48 	writel((value), ((a)->hw_addr + IXGB_##reg)))
49 
50 #define IXGB_READ_REG(a, reg) ( \
51 	readl((a)->hw_addr + IXGB_##reg))
52 
53 #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \
54 	writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2))))
55 
56 #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \
57 	readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
58 
59 #define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS)
60 
61 #define IXGB_MEMCPY memcpy
62 
63 #endif /* _IXGB_OSDEP_H_ */
64