1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #ifndef _IXGBE_TYPE_H_ 29 #define _IXGBE_TYPE_H_ 30 31 #include <linux/types.h> 32 #include <linux/mdio.h> 33 #include <linux/netdevice.h> 34 35 /* Vendor ID */ 36 #define IXGBE_INTEL_VENDOR_ID 0x8086 37 38 /* Device IDs */ 39 #define IXGBE_DEV_ID_82598 0x10B6 40 #define IXGBE_DEV_ID_82598_BX 0x1508 41 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 42 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 43 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 44 #define IXGBE_DEV_ID_82598AT 0x10C8 45 #define IXGBE_DEV_ID_82598AT2 0x150B 46 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD 47 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 48 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 49 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 50 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 51 #define IXGBE_DEV_ID_82599_KX4 0x10F7 52 #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 53 #define IXGBE_DEV_ID_82599_KR 0x1517 54 #define IXGBE_DEV_ID_82599_T3_LOM 0x151C 55 #define IXGBE_DEV_ID_82599_CX4 0x10F9 56 #define IXGBE_DEV_ID_82599_SFP 0x10FB 57 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a 58 #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 59 #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 60 #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 61 #define IXGBE_DEV_ID_82599_SFP_EM 0x1507 62 #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D 63 #define IXGBE_DEV_ID_82599EN_SFP 0x1557 64 #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC 65 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 66 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C 67 #define IXGBE_DEV_ID_82599_LS 0x154F 68 #define IXGBE_DEV_ID_X540T 0x1528 69 #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A 70 #define IXGBE_DEV_ID_X540T1 0x1560 71 72 /* VF Device IDs */ 73 #define IXGBE_DEV_ID_82599_VF 0x10ED 74 #define IXGBE_DEV_ID_X540_VF 0x1515 75 76 /* General Registers */ 77 #define IXGBE_CTRL 0x00000 78 #define IXGBE_STATUS 0x00008 79 #define IXGBE_CTRL_EXT 0x00018 80 #define IXGBE_ESDP 0x00020 81 #define IXGBE_EODSDP 0x00028 82 #define IXGBE_I2CCTL 0x00028 83 #define IXGBE_LEDCTL 0x00200 84 #define IXGBE_FRTIMER 0x00048 85 #define IXGBE_TCPTIMER 0x0004C 86 #define IXGBE_CORESPARE 0x00600 87 #define IXGBE_EXVET 0x05078 88 89 /* NVM Registers */ 90 #define IXGBE_EEC 0x10010 91 #define IXGBE_EERD 0x10014 92 #define IXGBE_EEWR 0x10018 93 #define IXGBE_FLA 0x1001C 94 #define IXGBE_EEMNGCTL 0x10110 95 #define IXGBE_EEMNGDATA 0x10114 96 #define IXGBE_FLMNGCTL 0x10118 97 #define IXGBE_FLMNGDATA 0x1011C 98 #define IXGBE_FLMNGCNT 0x10120 99 #define IXGBE_FLOP 0x1013C 100 #define IXGBE_GRC 0x10200 101 102 /* General Receive Control */ 103 #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 104 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ 105 106 #define IXGBE_VPDDIAG0 0x10204 107 #define IXGBE_VPDDIAG1 0x10208 108 109 /* I2CCTL Bit Masks */ 110 #define IXGBE_I2C_CLK_IN 0x00000001 111 #define IXGBE_I2C_CLK_OUT 0x00000002 112 #define IXGBE_I2C_DATA_IN 0x00000004 113 #define IXGBE_I2C_DATA_OUT 0x00000008 114 115 /* Interrupt Registers */ 116 #define IXGBE_EICR 0x00800 117 #define IXGBE_EICS 0x00808 118 #define IXGBE_EIMS 0x00880 119 #define IXGBE_EIMC 0x00888 120 #define IXGBE_EIAC 0x00810 121 #define IXGBE_EIAM 0x00890 122 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 123 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 124 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 125 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 126 /* 127 * 82598 EITR is 16 bits but set the limits based on the max 128 * supported by all ixgbe hardware. 82599 EITR is only 12 bits, 129 * with the lower 3 always zero. 130 */ 131 #define IXGBE_MAX_INT_RATE 488281 132 #define IXGBE_MIN_INT_RATE 956 133 #define IXGBE_MAX_EITR 0x00000FF8 134 #define IXGBE_MIN_EITR 8 135 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 136 (0x012300 + (((_i) - 24) * 4))) 137 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 138 #define IXGBE_EITR_LLI_MOD 0x00008000 139 #define IXGBE_EITR_CNT_WDIS 0x80000000 140 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 141 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 142 #define IXGBE_EITRSEL 0x00894 143 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 144 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 145 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 146 #define IXGBE_GPIE 0x00898 147 148 /* Flow Control Registers */ 149 #define IXGBE_FCADBUL 0x03210 150 #define IXGBE_FCADBUH 0x03214 151 #define IXGBE_FCAMACL 0x04328 152 #define IXGBE_FCAMACH 0x0432C 153 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 154 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 155 #define IXGBE_PFCTOP 0x03008 156 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 157 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 158 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 159 #define IXGBE_FCRTV 0x032A0 160 #define IXGBE_FCCFG 0x03D00 161 #define IXGBE_TFCS 0x0CE00 162 163 /* Receive DMA Registers */ 164 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 165 (0x0D000 + (((_i) - 64) * 0x40))) 166 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 167 (0x0D004 + (((_i) - 64) * 0x40))) 168 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 169 (0x0D008 + (((_i) - 64) * 0x40))) 170 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 171 (0x0D010 + (((_i) - 64) * 0x40))) 172 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 173 (0x0D018 + (((_i) - 64) * 0x40))) 174 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 175 (0x0D028 + (((_i) - 64) * 0x40))) 176 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 177 (0x0D02C + (((_i) - 64) * 0x40))) 178 #define IXGBE_RSCDBU 0x03028 179 #define IXGBE_RDDCC 0x02F20 180 #define IXGBE_RXMEMWRAP 0x03190 181 #define IXGBE_STARCTRL 0x03024 182 /* 183 * Split and Replication Receive Control Registers 184 * 00-15 : 0x02100 + n*4 185 * 16-64 : 0x01014 + n*0x40 186 * 64-127: 0x0D014 + (n-64)*0x40 187 */ 188 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 189 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 190 (0x0D014 + (((_i) - 64) * 0x40)))) 191 /* 192 * Rx DCA Control Register: 193 * 00-15 : 0x02200 + n*4 194 * 16-64 : 0x0100C + n*0x40 195 * 64-127: 0x0D00C + (n-64)*0x40 196 */ 197 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 198 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 199 (0x0D00C + (((_i) - 64) * 0x40)))) 200 #define IXGBE_RDRXCTL 0x02F00 201 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 202 /* 8 of these 0x03C00 - 0x03C1C */ 203 #define IXGBE_RXCTRL 0x03000 204 #define IXGBE_DROPEN 0x03D04 205 #define IXGBE_RXPBSIZE_SHIFT 10 206 207 /* Receive Registers */ 208 #define IXGBE_RXCSUM 0x05000 209 #define IXGBE_RFCTL 0x05008 210 #define IXGBE_DRECCCTL 0x02F08 211 #define IXGBE_DRECCCTL_DISABLE 0 212 /* Multicast Table Array - 128 entries */ 213 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 214 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 215 (0x0A200 + ((_i) * 8))) 216 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 217 (0x0A204 + ((_i) * 8))) 218 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 219 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 220 /* Packet split receive type */ 221 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 222 (0x0EA00 + ((_i) * 4))) 223 /* array of 4096 1-bit vlan filters */ 224 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 225 /*array of 4096 4-bit vlan vmdq indices */ 226 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 227 #define IXGBE_FCTRL 0x05080 228 #define IXGBE_VLNCTRL 0x05088 229 #define IXGBE_MCSTCTRL 0x05090 230 #define IXGBE_MRQC 0x05818 231 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 232 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 233 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 234 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 235 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 236 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 237 #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 238 #define IXGBE_RQTC 0x0EC70 239 #define IXGBE_MTQC 0x08120 240 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 241 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 242 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ 243 #define IXGBE_VT_CTL 0x051B0 244 #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ 245 #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */ 246 #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ 247 #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ 248 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 249 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 250 #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) 251 #define IXGBE_QDE 0x2F04 252 #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ 253 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 254 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 255 #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) 256 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 257 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 258 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 259 #define IXGBE_RXFECCERR0 0x051B8 260 #define IXGBE_LLITHRESH 0x0EC90 261 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 262 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 263 #define IXGBE_IMIRVP 0x05AC0 264 #define IXGBE_VMD_CTL 0x0581C 265 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 266 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 267 268 /* Flow Director registers */ 269 #define IXGBE_FDIRCTRL 0x0EE00 270 #define IXGBE_FDIRHKEY 0x0EE68 271 #define IXGBE_FDIRSKEY 0x0EE6C 272 #define IXGBE_FDIRDIP4M 0x0EE3C 273 #define IXGBE_FDIRSIP4M 0x0EE40 274 #define IXGBE_FDIRTCPM 0x0EE44 275 #define IXGBE_FDIRUDPM 0x0EE48 276 #define IXGBE_FDIRIP6M 0x0EE74 277 #define IXGBE_FDIRM 0x0EE70 278 279 /* Flow Director Stats registers */ 280 #define IXGBE_FDIRFREE 0x0EE38 281 #define IXGBE_FDIRLEN 0x0EE4C 282 #define IXGBE_FDIRUSTAT 0x0EE50 283 #define IXGBE_FDIRFSTAT 0x0EE54 284 #define IXGBE_FDIRMATCH 0x0EE58 285 #define IXGBE_FDIRMISS 0x0EE5C 286 287 /* Flow Director Programming registers */ 288 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 289 #define IXGBE_FDIRIPSA 0x0EE18 290 #define IXGBE_FDIRIPDA 0x0EE1C 291 #define IXGBE_FDIRPORT 0x0EE20 292 #define IXGBE_FDIRVLAN 0x0EE24 293 #define IXGBE_FDIRHASH 0x0EE28 294 #define IXGBE_FDIRCMD 0x0EE2C 295 296 /* Transmit DMA registers */ 297 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ 298 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 299 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 300 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 301 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 302 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 303 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 304 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 305 #define IXGBE_DTXCTL 0x07E00 306 307 #define IXGBE_DMATXCTL 0x04A80 308 #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ 309 #define IXGBE_PFDTXGSWC 0x08220 310 #define IXGBE_DTXMXSZRQ 0x08100 311 #define IXGBE_DTXTCPFLGL 0x04A88 312 #define IXGBE_DTXTCPFLGH 0x04A8C 313 #define IXGBE_LBDRPEN 0x0CA00 314 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 315 316 #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 317 #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 318 #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 319 #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 320 321 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 322 323 /* Anti-spoofing defines */ 324 #define IXGBE_SPOOF_MACAS_MASK 0xFF 325 #define IXGBE_SPOOF_VLANAS_MASK 0xFF00 326 #define IXGBE_SPOOF_VLANAS_SHIFT 8 327 #define IXGBE_PFVFSPOOF_REG_COUNT 8 328 329 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ 330 /* Tx DCA Control register : 128 of these (0-127) */ 331 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 332 #define IXGBE_TIPG 0x0CB00 333 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 334 #define IXGBE_MNGTXMAP 0x0CD10 335 #define IXGBE_TIPG_FIBER_DEFAULT 3 336 #define IXGBE_TXPBSIZE_SHIFT 10 337 338 /* Wake up registers */ 339 #define IXGBE_WUC 0x05800 340 #define IXGBE_WUFC 0x05808 341 #define IXGBE_WUS 0x05810 342 #define IXGBE_IPAV 0x05838 343 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 344 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 345 346 #define IXGBE_WUPL 0x05900 347 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 348 #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ 349 #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) /* Ext Flexible Host 350 * Filter Table */ 351 352 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 353 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 354 355 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 356 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 357 #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 358 #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 359 360 /* Definitions for power management and wakeup registers */ 361 /* Wake Up Control */ 362 #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 363 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 364 #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ 365 366 /* Wake Up Filter Control */ 367 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 368 #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 369 #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 370 #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 371 #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 372 #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 373 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 374 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 375 #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 376 377 #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 378 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 379 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 380 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 381 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 382 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 383 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 384 #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 385 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */ 386 #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */ 387 #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 388 389 /* Wake Up Status */ 390 #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 391 #define IXGBE_WUS_MAG IXGBE_WUFC_MAG 392 #define IXGBE_WUS_EX IXGBE_WUFC_EX 393 #define IXGBE_WUS_MC IXGBE_WUFC_MC 394 #define IXGBE_WUS_BC IXGBE_WUFC_BC 395 #define IXGBE_WUS_ARP IXGBE_WUFC_ARP 396 #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 397 #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 398 #define IXGBE_WUS_MNG IXGBE_WUFC_MNG 399 #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 400 #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 401 #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 402 #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 403 #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 404 #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 405 #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 406 407 /* Wake Up Packet Length */ 408 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF 409 410 /* DCB registers */ 411 #define MAX_TRAFFIC_CLASS 8 412 #define X540_TRAFFIC_CLASS 4 413 #define IXGBE_RMCS 0x03D00 414 #define IXGBE_DPMCS 0x07F40 415 #define IXGBE_PDPMCS 0x0CD00 416 #define IXGBE_RUPPBMR 0x050A0 417 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 418 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 419 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 420 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 421 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 422 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 423 424 425 /* Security Control Registers */ 426 #define IXGBE_SECTXCTRL 0x08800 427 #define IXGBE_SECTXSTAT 0x08804 428 #define IXGBE_SECTXBUFFAF 0x08808 429 #define IXGBE_SECTXMINIFG 0x08810 430 #define IXGBE_SECRXCTRL 0x08D00 431 #define IXGBE_SECRXSTAT 0x08D04 432 433 /* Security Bit Fields and Masks */ 434 #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 435 #define IXGBE_SECTXCTRL_TX_DIS 0x00000002 436 #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 437 438 #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 439 #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 440 441 #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 442 #define IXGBE_SECRXCTRL_RX_DIS 0x00000002 443 444 #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 445 #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 446 447 /* LinkSec (MacSec) Registers */ 448 #define IXGBE_LSECTXCAP 0x08A00 449 #define IXGBE_LSECRXCAP 0x08F00 450 #define IXGBE_LSECTXCTRL 0x08A04 451 #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 452 #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 453 #define IXGBE_LSECTXSA 0x08A10 454 #define IXGBE_LSECTXPN0 0x08A14 455 #define IXGBE_LSECTXPN1 0x08A18 456 #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 457 #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 458 #define IXGBE_LSECRXCTRL 0x08F04 459 #define IXGBE_LSECRXSCL 0x08F08 460 #define IXGBE_LSECRXSCH 0x08F0C 461 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 462 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 463 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 464 #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 465 #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 466 #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 467 #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 468 #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 469 #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 470 #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 471 #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 472 #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 473 #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 474 #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 475 #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 476 #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 477 #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 478 #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 479 #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 480 #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 481 #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 482 #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 483 484 /* LinkSec (MacSec) Bit Fields and Masks */ 485 #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 486 #define IXGBE_LSECTXCAP_SUM_SHIFT 16 487 #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 488 #define IXGBE_LSECRXCAP_SUM_SHIFT 16 489 490 #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 491 #define IXGBE_LSECTXCTRL_DISABLE 0x0 492 #define IXGBE_LSECTXCTRL_AUTH 0x1 493 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 494 #define IXGBE_LSECTXCTRL_AISCI 0x00000020 495 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 496 #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 497 498 #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 499 #define IXGBE_LSECRXCTRL_EN_SHIFT 2 500 #define IXGBE_LSECRXCTRL_DISABLE 0x0 501 #define IXGBE_LSECRXCTRL_CHECK 0x1 502 #define IXGBE_LSECRXCTRL_STRICT 0x2 503 #define IXGBE_LSECRXCTRL_DROP 0x3 504 #define IXGBE_LSECRXCTRL_PLSH 0x00000040 505 #define IXGBE_LSECRXCTRL_RP 0x00000080 506 #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 507 508 /* IpSec Registers */ 509 #define IXGBE_IPSTXIDX 0x08900 510 #define IXGBE_IPSTXSALT 0x08904 511 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 512 #define IXGBE_IPSRXIDX 0x08E00 513 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 514 #define IXGBE_IPSRXSPI 0x08E14 515 #define IXGBE_IPSRXIPIDX 0x08E18 516 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 517 #define IXGBE_IPSRXSALT 0x08E2C 518 #define IXGBE_IPSRXMOD 0x08E30 519 520 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 521 522 /* DCB registers */ 523 #define IXGBE_RTRPCS 0x02430 524 #define IXGBE_RTTDCS 0x04900 525 #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 526 #define IXGBE_RTTPCS 0x0CD00 527 #define IXGBE_RTRUP2TC 0x03020 528 #define IXGBE_RTTUP2TC 0x0C800 529 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 530 #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ 531 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 532 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 533 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 534 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 535 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 536 #define IXGBE_RTTDQSEL 0x04904 537 #define IXGBE_RTTDT1C 0x04908 538 #define IXGBE_RTTDT1S 0x0490C 539 #define IXGBE_RTTDTECC 0x04990 540 #define IXGBE_RTTDTECC_NO_BCN 0x00000100 541 #define IXGBE_RTTBCNRC 0x04984 542 #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 543 #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF 544 #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 545 #define IXGBE_RTTBCNRC_RF_INT_MASK \ 546 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) 547 #define IXGBE_RTTBCNRM 0x04980 548 549 /* FCoE DMA Context Registers */ 550 #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 551 #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 552 #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 553 #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 554 #define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */ 555 #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) 556 #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 557 #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 558 #define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 559 #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 560 #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 561 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 562 #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 563 #define IXGBE_FCBUFF_OFFSET_SHIFT 16 564 #define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 565 #define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 566 #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 567 #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 568 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 569 570 /* FCoE SOF/EOF */ 571 #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 572 #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 573 #define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 574 #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 575 /* FCoE Filter Context Registers */ 576 #define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 577 #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 578 #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 579 #define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 580 #define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 581 #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 582 #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 583 #define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 584 #define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 585 #define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 586 /* FCoE Receive Control */ 587 #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 588 #define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 589 #define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 590 #define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 591 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 592 #define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 593 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 594 #define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 595 #define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 596 #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 597 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 598 /* FCoE Redirection */ 599 #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 600 #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 601 #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 602 #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 603 #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 604 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 605 606 /* Stats registers */ 607 #define IXGBE_CRCERRS 0x04000 608 #define IXGBE_ILLERRC 0x04004 609 #define IXGBE_ERRBC 0x04008 610 #define IXGBE_MSPDC 0x04010 611 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 612 #define IXGBE_MLFC 0x04034 613 #define IXGBE_MRFC 0x04038 614 #define IXGBE_RLEC 0x04040 615 #define IXGBE_LXONTXC 0x03F60 616 #define IXGBE_LXONRXC 0x0CF60 617 #define IXGBE_LXOFFTXC 0x03F68 618 #define IXGBE_LXOFFRXC 0x0CF68 619 #define IXGBE_LXONRXCNT 0x041A4 620 #define IXGBE_LXOFFRXCNT 0x041A8 621 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 622 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 623 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 624 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 625 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 626 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 627 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 628 #define IXGBE_PRC64 0x0405C 629 #define IXGBE_PRC127 0x04060 630 #define IXGBE_PRC255 0x04064 631 #define IXGBE_PRC511 0x04068 632 #define IXGBE_PRC1023 0x0406C 633 #define IXGBE_PRC1522 0x04070 634 #define IXGBE_GPRC 0x04074 635 #define IXGBE_BPRC 0x04078 636 #define IXGBE_MPRC 0x0407C 637 #define IXGBE_GPTC 0x04080 638 #define IXGBE_GORCL 0x04088 639 #define IXGBE_GORCH 0x0408C 640 #define IXGBE_GOTCL 0x04090 641 #define IXGBE_GOTCH 0x04094 642 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 643 #define IXGBE_RUC 0x040A4 644 #define IXGBE_RFC 0x040A8 645 #define IXGBE_ROC 0x040AC 646 #define IXGBE_RJC 0x040B0 647 #define IXGBE_MNGPRC 0x040B4 648 #define IXGBE_MNGPDC 0x040B8 649 #define IXGBE_MNGPTC 0x0CF90 650 #define IXGBE_TORL 0x040C0 651 #define IXGBE_TORH 0x040C4 652 #define IXGBE_TPR 0x040D0 653 #define IXGBE_TPT 0x040D4 654 #define IXGBE_PTC64 0x040D8 655 #define IXGBE_PTC127 0x040DC 656 #define IXGBE_PTC255 0x040E0 657 #define IXGBE_PTC511 0x040E4 658 #define IXGBE_PTC1023 0x040E8 659 #define IXGBE_PTC1522 0x040EC 660 #define IXGBE_MPTC 0x040F0 661 #define IXGBE_BPTC 0x040F4 662 #define IXGBE_XEC 0x04120 663 #define IXGBE_SSVPC 0x08780 664 665 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 666 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 667 (0x08600 + ((_i) * 4))) 668 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 669 670 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 671 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 672 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 673 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 674 #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 675 #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ 676 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 677 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 678 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 679 #define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */ 680 #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 681 #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 682 #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 683 #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 684 #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 685 #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 686 #define IXGBE_O2BGPTC 0x041C4 687 #define IXGBE_O2BSPC 0x087B0 688 #define IXGBE_B2OSPC 0x041C0 689 #define IXGBE_B2OGPRC 0x02F90 690 #define IXGBE_PCRC8ECL 0x0E810 691 #define IXGBE_PCRC8ECH 0x0E811 692 #define IXGBE_PCRC8ECH_MASK 0x1F 693 #define IXGBE_LDPCECL 0x0E820 694 #define IXGBE_LDPCECH 0x0E821 695 696 /* Management */ 697 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 698 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 699 #define IXGBE_MANC 0x05820 700 #define IXGBE_MFVAL 0x05824 701 #define IXGBE_MANC2H 0x05860 702 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 703 #define IXGBE_MIPAF 0x058B0 704 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 705 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 706 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 707 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 708 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 709 #define IXGBE_LSWFW 0x15014 710 711 /* ARC Subsystem registers */ 712 #define IXGBE_HICR 0x15F00 713 #define IXGBE_FWSTS 0x15F0C 714 #define IXGBE_HSMC0R 0x15F04 715 #define IXGBE_HSMC1R 0x15F08 716 #define IXGBE_SWSR 0x15F10 717 #define IXGBE_HFDR 0x15FE8 718 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 719 720 #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ 721 /* Driver sets this bit when done to put command in RAM */ 722 #define IXGBE_HICR_C 0x02 723 #define IXGBE_HICR_SV 0x04 /* Status Validity */ 724 #define IXGBE_HICR_FW_RESET_ENABLE 0x40 725 #define IXGBE_HICR_FW_RESET 0x80 726 727 /* PCI-E registers */ 728 #define IXGBE_GCR 0x11000 729 #define IXGBE_GTV 0x11004 730 #define IXGBE_FUNCTAG 0x11008 731 #define IXGBE_GLT 0x1100C 732 #define IXGBE_GSCL_1 0x11010 733 #define IXGBE_GSCL_2 0x11014 734 #define IXGBE_GSCL_3 0x11018 735 #define IXGBE_GSCL_4 0x1101C 736 #define IXGBE_GSCN_0 0x11020 737 #define IXGBE_GSCN_1 0x11024 738 #define IXGBE_GSCN_2 0x11028 739 #define IXGBE_GSCN_3 0x1102C 740 #define IXGBE_FACTPS 0x10150 741 #define IXGBE_PCIEANACTL 0x11040 742 #define IXGBE_SWSM 0x10140 743 #define IXGBE_FWSM 0x10148 744 #define IXGBE_GSSR 0x10160 745 #define IXGBE_MREVID 0x11064 746 #define IXGBE_DCA_ID 0x11070 747 #define IXGBE_DCA_CTRL 0x11074 748 #define IXGBE_SWFW_SYNC IXGBE_GSSR 749 750 /* PCIe registers 82599-specific */ 751 #define IXGBE_GCR_EXT 0x11050 752 #define IXGBE_GSCL_5_82599 0x11030 753 #define IXGBE_GSCL_6_82599 0x11034 754 #define IXGBE_GSCL_7_82599 0x11038 755 #define IXGBE_GSCL_8_82599 0x1103C 756 #define IXGBE_PHYADR_82599 0x11040 757 #define IXGBE_PHYDAT_82599 0x11044 758 #define IXGBE_PHYCTL_82599 0x11048 759 #define IXGBE_PBACLR_82599 0x11068 760 #define IXGBE_CIAA_82599 0x11088 761 #define IXGBE_CIAD_82599 0x1108C 762 #define IXGBE_PICAUSE 0x110B0 763 #define IXGBE_PIENA 0x110B8 764 #define IXGBE_CDQ_MBR_82599 0x110B4 765 #define IXGBE_PCIESPARE 0x110BC 766 #define IXGBE_MISC_REG_82599 0x110F0 767 #define IXGBE_ECC_CTRL_0_82599 0x11100 768 #define IXGBE_ECC_CTRL_1_82599 0x11104 769 #define IXGBE_ECC_STATUS_82599 0x110E0 770 #define IXGBE_BAR_CTRL_82599 0x110F4 771 772 /* PCI Express Control */ 773 #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 774 #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 775 #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 776 #define IXGBE_GCR_CAP_VER2 0x00040000 777 778 #define IXGBE_GCR_EXT_MSIX_EN 0x80000000 779 #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 780 #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 781 #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 782 #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 783 #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ 784 IXGBE_GCR_EXT_VT_MODE_64) 785 786 /* Time Sync Registers */ 787 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 788 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 789 #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 790 #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 791 #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 792 #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 793 #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 794 #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 795 #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 796 #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 797 #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 798 #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 799 #define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ 800 #define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ 801 #define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ 802 #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ 803 #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ 804 #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ 805 #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ 806 #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ 807 #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ 808 #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ 809 #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ 810 #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ 811 #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ 812 813 /* Diagnostic Registers */ 814 #define IXGBE_RDSTATCTL 0x02C20 815 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 816 #define IXGBE_RDHMPN 0x02F08 817 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 818 #define IXGBE_RDPROBE 0x02F20 819 #define IXGBE_RDMAM 0x02F30 820 #define IXGBE_RDMAD 0x02F34 821 #define IXGBE_TDSTATCTL 0x07C20 822 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 823 #define IXGBE_TDHMPN 0x07F08 824 #define IXGBE_TDHMPN2 0x082FC 825 #define IXGBE_TXDESCIC 0x082CC 826 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 827 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 828 #define IXGBE_TDPROBE 0x07F20 829 #define IXGBE_TXBUFCTRL 0x0C600 830 #define IXGBE_TXBUFDATA0 0x0C610 831 #define IXGBE_TXBUFDATA1 0x0C614 832 #define IXGBE_TXBUFDATA2 0x0C618 833 #define IXGBE_TXBUFDATA3 0x0C61C 834 #define IXGBE_RXBUFCTRL 0x03600 835 #define IXGBE_RXBUFDATA0 0x03610 836 #define IXGBE_RXBUFDATA1 0x03614 837 #define IXGBE_RXBUFDATA2 0x03618 838 #define IXGBE_RXBUFDATA3 0x0361C 839 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 840 #define IXGBE_RFVAL 0x050A4 841 #define IXGBE_MDFTC1 0x042B8 842 #define IXGBE_MDFTC2 0x042C0 843 #define IXGBE_MDFTFIFO1 0x042C4 844 #define IXGBE_MDFTFIFO2 0x042C8 845 #define IXGBE_MDFTS 0x042CC 846 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 847 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 848 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 849 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 850 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 851 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 852 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 853 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 854 #define IXGBE_PCIEECCCTL 0x1106C 855 #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 856 #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 857 #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 858 #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 859 #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 860 #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 861 #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 862 #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 863 #define IXGBE_PCIEECCCTL0 0x11100 864 #define IXGBE_PCIEECCCTL1 0x11104 865 #define IXGBE_RXDBUECC 0x03F70 866 #define IXGBE_TXDBUECC 0x0CF70 867 #define IXGBE_RXDBUEST 0x03F74 868 #define IXGBE_TXDBUEST 0x0CF74 869 #define IXGBE_PBTXECC 0x0C300 870 #define IXGBE_PBRXECC 0x03300 871 #define IXGBE_GHECCR 0x110B0 872 873 /* MAC Registers */ 874 #define IXGBE_PCS1GCFIG 0x04200 875 #define IXGBE_PCS1GLCTL 0x04208 876 #define IXGBE_PCS1GLSTA 0x0420C 877 #define IXGBE_PCS1GDBG0 0x04210 878 #define IXGBE_PCS1GDBG1 0x04214 879 #define IXGBE_PCS1GANA 0x04218 880 #define IXGBE_PCS1GANLP 0x0421C 881 #define IXGBE_PCS1GANNP 0x04220 882 #define IXGBE_PCS1GANLPNP 0x04224 883 #define IXGBE_HLREG0 0x04240 884 #define IXGBE_HLREG1 0x04244 885 #define IXGBE_PAP 0x04248 886 #define IXGBE_MACA 0x0424C 887 #define IXGBE_APAE 0x04250 888 #define IXGBE_ARD 0x04254 889 #define IXGBE_AIS 0x04258 890 #define IXGBE_MSCA 0x0425C 891 #define IXGBE_MSRWD 0x04260 892 #define IXGBE_MLADD 0x04264 893 #define IXGBE_MHADD 0x04268 894 #define IXGBE_MAXFRS 0x04268 895 #define IXGBE_TREG 0x0426C 896 #define IXGBE_PCSS1 0x04288 897 #define IXGBE_PCSS2 0x0428C 898 #define IXGBE_XPCSS 0x04290 899 #define IXGBE_MFLCN 0x04294 900 #define IXGBE_SERDESC 0x04298 901 #define IXGBE_MACS 0x0429C 902 #define IXGBE_AUTOC 0x042A0 903 #define IXGBE_LINKS 0x042A4 904 #define IXGBE_LINKS2 0x04324 905 #define IXGBE_AUTOC2 0x042A8 906 #define IXGBE_AUTOC3 0x042AC 907 #define IXGBE_ANLP1 0x042B0 908 #define IXGBE_ANLP2 0x042B4 909 #define IXGBE_MACC 0x04330 910 #define IXGBE_ATLASCTL 0x04800 911 #define IXGBE_MMNGC 0x042D0 912 #define IXGBE_ANLPNP1 0x042D4 913 #define IXGBE_ANLPNP2 0x042D8 914 #define IXGBE_KRPCSFC 0x042E0 915 #define IXGBE_KRPCSS 0x042E4 916 #define IXGBE_FECS1 0x042E8 917 #define IXGBE_FECS2 0x042EC 918 #define IXGBE_SMADARCTL 0x14F10 919 #define IXGBE_MPVC 0x04318 920 #define IXGBE_SGMIIC 0x04314 921 922 /* Statistics Registers */ 923 #define IXGBE_RXNFGPC 0x041B0 924 #define IXGBE_RXNFGBCL 0x041B4 925 #define IXGBE_RXNFGBCH 0x041B8 926 #define IXGBE_RXDGPC 0x02F50 927 #define IXGBE_RXDGBCL 0x02F54 928 #define IXGBE_RXDGBCH 0x02F58 929 #define IXGBE_RXDDGPC 0x02F5C 930 #define IXGBE_RXDDGBCL 0x02F60 931 #define IXGBE_RXDDGBCH 0x02F64 932 #define IXGBE_RXLPBKGPC 0x02F68 933 #define IXGBE_RXLPBKGBCL 0x02F6C 934 #define IXGBE_RXLPBKGBCH 0x02F70 935 #define IXGBE_RXDLPBKGPC 0x02F74 936 #define IXGBE_RXDLPBKGBCL 0x02F78 937 #define IXGBE_RXDLPBKGBCH 0x02F7C 938 #define IXGBE_TXDGPC 0x087A0 939 #define IXGBE_TXDGBCL 0x087A4 940 #define IXGBE_TXDGBCH 0x087A8 941 942 #define IXGBE_RXDSTATCTRL 0x02F40 943 944 /* Copper Pond 2 link timeout */ 945 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 946 947 /* Omer CORECTL */ 948 #define IXGBE_CORECTL 0x014F00 949 /* BARCTRL */ 950 #define IXGBE_BARCTRL 0x110F4 951 #define IXGBE_BARCTRL_FLSIZE 0x0700 952 #define IXGBE_BARCTRL_FLSIZE_SHIFT 8 953 #define IXGBE_BARCTRL_CSRSIZE 0x2000 954 955 /* RSCCTL Bit Masks */ 956 #define IXGBE_RSCCTL_RSCEN 0x01 957 #define IXGBE_RSCCTL_MAXDESC_1 0x00 958 #define IXGBE_RSCCTL_MAXDESC_4 0x04 959 #define IXGBE_RSCCTL_MAXDESC_8 0x08 960 #define IXGBE_RSCCTL_MAXDESC_16 0x0C 961 962 /* RSCDBU Bit Masks */ 963 #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 964 #define IXGBE_RSCDBU_RSCACKDIS 0x00000080 965 966 /* RDRXCTL Bit Masks */ 967 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ 968 #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 969 #define IXGBE_RDRXCTL_MVMEN 0x00000020 970 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 971 #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 972 #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 973 #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */ 974 #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */ 975 #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */ 976 977 /* RQTC Bit Masks and Shifts */ 978 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 979 #define IXGBE_RQTC_TC0_MASK (0x7 << 0) 980 #define IXGBE_RQTC_TC1_MASK (0x7 << 4) 981 #define IXGBE_RQTC_TC2_MASK (0x7 << 8) 982 #define IXGBE_RQTC_TC3_MASK (0x7 << 12) 983 #define IXGBE_RQTC_TC4_MASK (0x7 << 16) 984 #define IXGBE_RQTC_TC5_MASK (0x7 << 20) 985 #define IXGBE_RQTC_TC6_MASK (0x7 << 24) 986 #define IXGBE_RQTC_TC7_MASK (0x7 << 28) 987 988 /* PSRTYPE.RQPL Bit masks and shift */ 989 #define IXGBE_PSRTYPE_RQPL_MASK 0x7 990 #define IXGBE_PSRTYPE_RQPL_SHIFT 29 991 992 /* CTRL Bit Masks */ 993 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 994 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 995 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 996 #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) 997 998 /* FACTPS */ 999 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 1000 1001 /* MHADD Bit Masks */ 1002 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000 1003 #define IXGBE_MHADD_MFS_SHIFT 16 1004 1005 /* Extended Device Control */ 1006 #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 1007 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 1008 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1009 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1010 1011 /* Direct Cache Access (DCA) definitions */ 1012 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 1013 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 1014 1015 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 1016 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 1017 1018 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 1019 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 1020 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 1021 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 1022 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 1023 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 1024 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */ 1025 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 1026 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 1027 1028 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 1029 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 1030 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 1031 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 1032 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 1033 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 1034 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 1035 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 1036 1037 /* MSCA Bit Masks */ 1038 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ 1039 #define IXGBE_MSCA_NP_ADDR_SHIFT 0 1040 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ 1041 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ 1042 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 1043 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 1044 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 1045 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 1046 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 1047 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ 1048 #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */ 1049 #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/ 1050 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 1051 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 1052 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ 1053 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ 1054 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 1055 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ 1056 1057 /* MSRWD bit masks */ 1058 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 1059 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 1060 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 1061 #define IXGBE_MSRWD_READ_DATA_SHIFT 16 1062 1063 /* Atlas registers */ 1064 #define IXGBE_ATLAS_PDN_LPBK 0x24 1065 #define IXGBE_ATLAS_PDN_10G 0xB 1066 #define IXGBE_ATLAS_PDN_1G 0xC 1067 #define IXGBE_ATLAS_PDN_AN 0xD 1068 1069 /* Atlas bit masks */ 1070 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 1071 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 1072 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 1073 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 1074 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 1075 1076 /* Omer bit masks */ 1077 #define IXGBE_CORECTL_WRITE_CMD 0x00010000 1078 1079 /* MDIO definitions */ 1080 1081 #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 1082 1083 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ 1084 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 1085 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 1086 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ 1087 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 1088 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 1089 1090 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 1091 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 1092 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 1093 1094 /* MII clause 22/28 definitions */ 1095 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 1096 #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 1097 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 1098 #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1099 #define IXGBE_MII_AUTONEG_REG 0x0 1100 1101 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1102 #define IXGBE_MAX_PHY_ADDR 32 1103 1104 /* PHY IDs*/ 1105 #define TN1010_PHY_ID 0x00A19410 1106 #define TNX_FW_REV 0xB 1107 #define X540_PHY_ID 0x01540200 1108 #define QT2022_PHY_ID 0x0043A400 1109 #define ATH_PHY_ID 0x03429050 1110 #define AQ_FW_REV 0x20 1111 1112 /* PHY Types */ 1113 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 1114 1115 /* Special PHY Init Routine */ 1116 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B 1117 #define IXGBE_PHY_INIT_END_NL 0xFFFF 1118 #define IXGBE_CONTROL_MASK_NL 0xF000 1119 #define IXGBE_DATA_MASK_NL 0x0FFF 1120 #define IXGBE_CONTROL_SHIFT_NL 12 1121 #define IXGBE_DELAY_NL 0 1122 #define IXGBE_DATA_NL 1 1123 #define IXGBE_CONTROL_NL 0x000F 1124 #define IXGBE_CONTROL_EOL_NL 0x0FFF 1125 #define IXGBE_CONTROL_SOL_NL 0x0000 1126 1127 /* General purpose Interrupt Enable */ 1128 #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 1129 #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 1130 #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ 1131 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 1132 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 1133 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 1134 #define IXGBE_GPIE_EIAME 0x40000000 1135 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 1136 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11 1137 #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 1138 #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 1139 #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 1140 #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 1141 1142 /* Packet Buffer Initialization */ 1143 #define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ 1144 #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 1145 #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 1146 #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 1147 #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 1148 #define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 1149 #define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer*/ 1150 #define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/ 1151 1152 #define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 1153 #define IXGBE_MAX_PB 8 1154 1155 /* Packet buffer allocation strategies */ 1156 enum { 1157 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 1158 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 1159 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 1160 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 1161 }; 1162 1163 /* Transmit Flow Control status */ 1164 #define IXGBE_TFCS_TXOFF 0x00000001 1165 #define IXGBE_TFCS_TXOFF0 0x00000100 1166 #define IXGBE_TFCS_TXOFF1 0x00000200 1167 #define IXGBE_TFCS_TXOFF2 0x00000400 1168 #define IXGBE_TFCS_TXOFF3 0x00000800 1169 #define IXGBE_TFCS_TXOFF4 0x00001000 1170 #define IXGBE_TFCS_TXOFF5 0x00002000 1171 #define IXGBE_TFCS_TXOFF6 0x00004000 1172 #define IXGBE_TFCS_TXOFF7 0x00008000 1173 1174 /* TCP Timer */ 1175 #define IXGBE_TCPTIMER_KS 0x00000100 1176 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 1177 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 1178 #define IXGBE_TCPTIMER_LOOP 0x00000800 1179 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 1180 1181 /* HLREG0 Bit Masks */ 1182 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 1183 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 1184 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 1185 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 1186 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 1187 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 1188 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 1189 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 1190 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 1191 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 1192 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 1193 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 1194 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 1195 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 1196 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 1197 1198 /* VMD_CTL bitmasks */ 1199 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 1200 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 1201 1202 /* VT_CTL bitmasks */ 1203 #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 1204 #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 1205 #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 1206 #define IXGBE_VT_CTL_POOL_SHIFT 7 1207 #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 1208 1209 /* VMOLR bitmasks */ 1210 #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 1211 #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 1212 #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 1213 #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 1214 #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 1215 1216 /* VFRE bitmask */ 1217 #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 1218 1219 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1220 1221 /* RDHMPN and TDHMPN bitmasks */ 1222 #define IXGBE_RDHMPN_RDICADDR 0x007FF800 1223 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000 1224 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11 1225 #define IXGBE_TDHMPN_TDICADDR 0x003FF800 1226 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000 1227 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11 1228 1229 #define IXGBE_RDMAM_MEM_SEL_SHIFT 13 1230 #define IXGBE_RDMAM_DWORD_SHIFT 9 1231 #define IXGBE_RDMAM_DESC_COMP_FIFO 1 1232 #define IXGBE_RDMAM_DFC_CMD_FIFO 2 1233 #define IXGBE_RDMAM_TCN_STATUS_RAM 4 1234 #define IXGBE_RDMAM_WB_COLL_FIFO 5 1235 #define IXGBE_RDMAM_QSC_CNT_RAM 6 1236 #define IXGBE_RDMAM_QSC_QUEUE_CNT 8 1237 #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 1238 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 1239 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 1240 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 1241 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 1242 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 1243 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 1244 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 1245 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 1246 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 1247 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 1248 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 1249 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 1250 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 1251 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 1252 1253 #define IXGBE_TXDESCIC_READY 0x80000000 1254 1255 /* Receive Checksum Control */ 1256 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1257 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1258 1259 /* FCRTL Bit Masks */ 1260 #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 1261 #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 1262 1263 /* PAP bit masks*/ 1264 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1265 1266 /* RMCS Bit Masks */ 1267 #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 1268 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1269 #define IXGBE_RMCS_RAC 0x00000004 1270 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ 1271 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 1272 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 1273 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1274 1275 /* FCCFG Bit Masks */ 1276 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 1277 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 1278 1279 /* Interrupt register bitmasks */ 1280 1281 /* Extended Interrupt Cause Read */ 1282 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1283 #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 1284 #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 1285 #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 1286 #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 1287 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1288 #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 1289 #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 1290 #define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ 1291 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 1292 #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 1293 #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ 1294 #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1295 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1296 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1297 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1298 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 1299 1300 /* Extended Interrupt Cause Set */ 1301 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1302 #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1303 #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 1304 #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1305 #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1306 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1307 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1308 #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1309 #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1310 #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1311 #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1312 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1313 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1314 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1315 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1316 1317 /* Extended Interrupt Mask Set */ 1318 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1319 #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1320 #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1321 #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1322 #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1323 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1324 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1325 #define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermel Sensor Event */ 1326 #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1327 #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1328 #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1329 #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 1330 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1331 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 1332 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1333 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1334 1335 /* Extended Interrupt Mask Clear */ 1336 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1337 #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1338 #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1339 #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 1340 #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1341 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 1342 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1343 #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1344 #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1345 #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1346 #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 1347 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1348 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 1349 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1350 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1351 1352 #define IXGBE_EIMS_ENABLE_MASK ( \ 1353 IXGBE_EIMS_RTX_QUEUE | \ 1354 IXGBE_EIMS_LSC | \ 1355 IXGBE_EIMS_TCP_TIMER | \ 1356 IXGBE_EIMS_OTHER) 1357 1358 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 1359 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 1360 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 1361 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 1362 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 1363 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 1364 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 1365 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 1366 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 1367 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 1368 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 1369 #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 1370 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 1371 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 1372 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 1373 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 1374 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 1375 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 1376 #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */ 1377 #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 1378 #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 1379 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 1380 #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 1381 #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 1382 1383 #define IXGBE_MAX_FTQF_FILTERS 128 1384 #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 1385 #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 1386 #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 1387 #define IXGBE_FTQF_PROTOCOL_SCTP 2 1388 #define IXGBE_FTQF_PRIORITY_MASK 0x00000007 1389 #define IXGBE_FTQF_PRIORITY_SHIFT 2 1390 #define IXGBE_FTQF_POOL_MASK 0x0000003F 1391 #define IXGBE_FTQF_POOL_SHIFT 8 1392 #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 1393 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 1394 #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 1395 #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 1396 #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 1397 #define IXGBE_FTQF_DEST_PORT_MASK 0x17 1398 #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 1399 #define IXGBE_FTQF_POOL_MASK_EN 0x40000000 1400 #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 1401 1402 /* Interrupt clear mask */ 1403 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 1404 1405 /* Interrupt Vector Allocation Registers */ 1406 #define IXGBE_IVAR_REG_NUM 25 1407 #define IXGBE_IVAR_REG_NUM_82599 64 1408 #define IXGBE_IVAR_TXRX_ENTRY 96 1409 #define IXGBE_IVAR_RX_ENTRY 64 1410 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 1411 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 1412 #define IXGBE_IVAR_TX_ENTRY 32 1413 1414 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 1415 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 1416 1417 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 1418 1419 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 1420 1421 /* ETYPE Queue Filter/Select Bit Masks */ 1422 #define IXGBE_MAX_ETQF_FILTERS 8 1423 #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 1424 #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 1425 #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 1426 #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 1427 #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 1428 1429 #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 1430 #define IXGBE_ETQS_RX_QUEUE_SHIFT 16 1431 #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 1432 #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 1433 1434 /* 1435 * ETQF filter list: one static filter per filter consumer. This is 1436 * to avoid filter collisions later. Add new filters 1437 * here!! 1438 * 1439 * Current filters: 1440 * EAPOL 802.1x (0x888e): Filter 0 1441 * FCoE (0x8906): Filter 2 1442 * 1588 (0x88f7): Filter 3 1443 * FIP (0x8914): Filter 4 1444 */ 1445 #define IXGBE_ETQF_FILTER_EAPOL 0 1446 #define IXGBE_ETQF_FILTER_FCOE 2 1447 #define IXGBE_ETQF_FILTER_1588 3 1448 #define IXGBE_ETQF_FILTER_FIP 4 1449 /* VLAN Control Bit Masks */ 1450 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 1451 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 1452 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 1453 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 1454 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 1455 1456 /* VLAN pool filtering masks */ 1457 #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 1458 #define IXGBE_VLVF_ENTRIES 64 1459 #define IXGBE_VLVF_VLANID_MASK 0x00000FFF 1460 1461 /* Per VF Port VLAN insertion rules */ 1462 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 1463 #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 1464 1465 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 1466 1467 /* STATUS Bit Masks */ 1468 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 1469 #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 1470 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ 1471 1472 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 1473 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 1474 1475 /* ESDP Bit Masks */ 1476 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 1477 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 1478 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 1479 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 1480 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 1481 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 1482 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 1483 #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ 1484 #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 1485 1486 /* LEDCTL Bit Masks */ 1487 #define IXGBE_LED_IVRT_BASE 0x00000040 1488 #define IXGBE_LED_BLINK_BASE 0x00000080 1489 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F 1490 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 1491 #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i)) 1492 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 1493 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 1494 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 1495 1496 /* LED modes */ 1497 #define IXGBE_LED_LINK_UP 0x0 1498 #define IXGBE_LED_LINK_10G 0x1 1499 #define IXGBE_LED_MAC 0x2 1500 #define IXGBE_LED_FILTER 0x3 1501 #define IXGBE_LED_LINK_ACTIVE 0x4 1502 #define IXGBE_LED_LINK_1G 0x5 1503 #define IXGBE_LED_ON 0xE 1504 #define IXGBE_LED_OFF 0xF 1505 1506 /* AUTOC Bit Masks */ 1507 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 1508 #define IXGBE_AUTOC_KX4_SUPP 0x80000000 1509 #define IXGBE_AUTOC_KX_SUPP 0x40000000 1510 #define IXGBE_AUTOC_PAUSE 0x30000000 1511 #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 1512 #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 1513 #define IXGBE_AUTOC_RF 0x08000000 1514 #define IXGBE_AUTOC_PD_TMR 0x06000000 1515 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 1516 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 1517 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 1518 #define IXGBE_AUTOC_FECA 0x00040000 1519 #define IXGBE_AUTOC_FECR 0x00020000 1520 #define IXGBE_AUTOC_KR_SUPP 0x00010000 1521 #define IXGBE_AUTOC_AN_RESTART 0x00001000 1522 #define IXGBE_AUTOC_FLU 0x00000001 1523 #define IXGBE_AUTOC_LMS_SHIFT 13 1524 #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 1525 #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1526 #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 1527 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1528 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1529 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1530 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 1531 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 1532 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 1533 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1534 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1535 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1536 1537 #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 1538 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 1539 #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 1540 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 1541 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1542 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1543 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1544 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1545 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1546 #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1547 #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1548 1549 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 1550 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 1551 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 1552 #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1553 #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1554 #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1555 1556 #define IXGBE_MACC_FLU 0x00000001 1557 #define IXGBE_MACC_FSV_10G 0x00030000 1558 #define IXGBE_MACC_FS 0x00040000 1559 #define IXGBE_MAC_RX2TX_LPBK 0x00000002 1560 1561 /* LINKS Bit Masks */ 1562 #define IXGBE_LINKS_KX_AN_COMP 0x80000000 1563 #define IXGBE_LINKS_UP 0x40000000 1564 #define IXGBE_LINKS_SPEED 0x20000000 1565 #define IXGBE_LINKS_MODE 0x18000000 1566 #define IXGBE_LINKS_RX_MODE 0x06000000 1567 #define IXGBE_LINKS_TX_MODE 0x01800000 1568 #define IXGBE_LINKS_XGXS_EN 0x00400000 1569 #define IXGBE_LINKS_SGMII_EN 0x02000000 1570 #define IXGBE_LINKS_PCS_1G_EN 0x00200000 1571 #define IXGBE_LINKS_1G_AN_EN 0x00100000 1572 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000 1573 #define IXGBE_LINKS_1G_SYNC 0x00040000 1574 #define IXGBE_LINKS_10G_ALIGN 0x00020000 1575 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 1576 #define IXGBE_LINKS_TL_FAULT 0x00001000 1577 #define IXGBE_LINKS_SIGNAL 0x00000F00 1578 1579 #define IXGBE_LINKS_SPEED_82599 0x30000000 1580 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 1581 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 1582 #define IXGBE_LINKS_SPEED_100_82599 0x10000000 1583 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 1584 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1585 1586 #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 1587 1588 /* PCS1GLSTA Bit Masks */ 1589 #define IXGBE_PCS1GLSTA_LINK_OK 1 1590 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 1591 #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 1592 #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 1593 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 1594 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 1595 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 1596 1597 #define IXGBE_PCS1GANA_SYM_PAUSE 0x80 1598 #define IXGBE_PCS1GANA_ASM_PAUSE 0x100 1599 1600 /* PCS1GLCTL Bit Masks */ 1601 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 1602 #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 1603 #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 1604 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 1605 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 1606 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 1607 1608 /* ANLP1 Bit Masks */ 1609 #define IXGBE_ANLP1_PAUSE 0x0C00 1610 #define IXGBE_ANLP1_SYM_PAUSE 0x0400 1611 #define IXGBE_ANLP1_ASM_PAUSE 0x0800 1612 #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 1613 1614 /* SW Semaphore Register bitmasks */ 1615 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1616 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1617 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1618 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 1619 1620 /* SW_FW_SYNC/GSSR definitions */ 1621 #define IXGBE_GSSR_EEP_SM 0x0001 1622 #define IXGBE_GSSR_PHY0_SM 0x0002 1623 #define IXGBE_GSSR_PHY1_SM 0x0004 1624 #define IXGBE_GSSR_MAC_CSR_SM 0x0008 1625 #define IXGBE_GSSR_FLASH_SM 0x0010 1626 #define IXGBE_GSSR_SW_MNG_SM 0x0400 1627 1628 /* FW Status register bitmask */ 1629 #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 1630 1631 /* EEC Register */ 1632 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 1633 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 1634 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 1635 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 1636 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 1637 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1638 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 1639 #define IXGBE_EEC_FWE_SHIFT 4 1640 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 1641 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 1642 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 1643 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 1644 #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 1645 #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ 1646 #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 1647 /* EEPROM Addressing bits based on type (0-small, 1-large) */ 1648 #define IXGBE_EEC_ADDR_SIZE 0x00000400 1649 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 1650 #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ 1651 1652 #define IXGBE_EEC_SIZE_SHIFT 11 1653 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 1654 #define IXGBE_EEPROM_OPCODE_BITS 8 1655 1656 /* Part Number String Length */ 1657 #define IXGBE_PBANUM_LENGTH 11 1658 1659 /* Checksum and EEPROM pointers */ 1660 #define IXGBE_PBANUM_PTR_GUARD 0xFAFA 1661 #define IXGBE_EEPROM_CHECKSUM 0x3F 1662 #define IXGBE_EEPROM_SUM 0xBABA 1663 #define IXGBE_PCIE_ANALOG_PTR 0x03 1664 #define IXGBE_ATLAS0_CONFIG_PTR 0x04 1665 #define IXGBE_PHY_PTR 0x04 1666 #define IXGBE_ATLAS1_CONFIG_PTR 0x05 1667 #define IXGBE_OPTION_ROM_PTR 0x05 1668 #define IXGBE_PCIE_GENERAL_PTR 0x06 1669 #define IXGBE_PCIE_CONFIG0_PTR 0x07 1670 #define IXGBE_PCIE_CONFIG1_PTR 0x08 1671 #define IXGBE_CORE0_PTR 0x09 1672 #define IXGBE_CORE1_PTR 0x0A 1673 #define IXGBE_MAC0_PTR 0x0B 1674 #define IXGBE_MAC1_PTR 0x0C 1675 #define IXGBE_CSR0_CONFIG_PTR 0x0D 1676 #define IXGBE_CSR1_CONFIG_PTR 0x0E 1677 #define IXGBE_FW_PTR 0x0F 1678 #define IXGBE_PBANUM0_PTR 0x15 1679 #define IXGBE_PBANUM1_PTR 0x16 1680 #define IXGBE_FREE_SPACE_PTR 0X3E 1681 #define IXGBE_SAN_MAC_ADDR_PTR 0x28 1682 #define IXGBE_DEVICE_CAPS 0x2C 1683 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 1684 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72 1685 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62 1686 1687 /* MSI-X capability fields masks */ 1688 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 1689 1690 /* Legacy EEPROM word offsets */ 1691 #define IXGBE_ISCSI_BOOT_CAPS 0x0033 1692 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030 1693 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034 1694 1695 /* EEPROM Commands - SPI */ 1696 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 1697 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 1698 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 1699 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 1700 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 1701 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 1702 /* EEPROM reset Write Enable latch */ 1703 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 1704 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 1705 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 1706 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 1707 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 1708 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 1709 1710 /* EEPROM Read Register */ 1711 #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 1712 #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 1713 #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 1714 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1715 #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1716 #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1717 1718 #define IXGBE_EEPROM_PAGE_SIZE_MAX 128 1719 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */ 1720 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */ 1721 1722 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 1723 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1724 #endif 1725 1726 #ifndef IXGBE_EERD_EEWR_ATTEMPTS 1727 /* Number of 5 microseconds we wait for EERD read and 1728 * EERW write to complete */ 1729 #define IXGBE_EERD_EEWR_ATTEMPTS 100000 1730 #endif 1731 1732 #ifndef IXGBE_FLUDONE_ATTEMPTS 1733 /* # attempts we wait for flush update to complete */ 1734 #define IXGBE_FLUDONE_ATTEMPTS 20000 1735 #endif 1736 1737 #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 1738 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 1739 #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 1740 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 1741 1742 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 1743 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 1744 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 1745 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 1746 #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 1747 #define IXGBE_FW_LESM_STATE_1 0x1 1748 #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 1749 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 1750 #define IXGBE_FW_PATCH_VERSION_4 0x7 1751 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ 1752 #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ 1753 #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ 1754 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ 1755 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ 1756 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 1757 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */ 1758 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */ 1759 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */ 1760 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */ 1761 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */ 1762 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */ 1763 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */ 1764 1765 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ 1766 #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ 1767 #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ 1768 1769 /* PCI Bus Info */ 1770 #define IXGBE_PCI_DEVICE_STATUS 0xAA 1771 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 1772 #define IXGBE_PCI_LINK_STATUS 0xB2 1773 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8 1774 #define IXGBE_PCI_LINK_WIDTH 0x3F0 1775 #define IXGBE_PCI_LINK_WIDTH_1 0x10 1776 #define IXGBE_PCI_LINK_WIDTH_2 0x20 1777 #define IXGBE_PCI_LINK_WIDTH_4 0x40 1778 #define IXGBE_PCI_LINK_WIDTH_8 0x80 1779 #define IXGBE_PCI_LINK_SPEED 0xF 1780 #define IXGBE_PCI_LINK_SPEED_2500 0x1 1781 #define IXGBE_PCI_LINK_SPEED_5000 0x2 1782 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 1783 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 1784 #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 1785 1786 /* Number of 100 microseconds we wait for PCI Express master disable */ 1787 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 1788 1789 /* Check whether address is multicast. This is little-endian specific check.*/ 1790 #define IXGBE_IS_MULTICAST(Address) \ 1791 (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 1792 1793 /* Check whether an address is broadcast. */ 1794 #define IXGBE_IS_BROADCAST(Address) \ 1795 ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 1796 (((u8 *)(Address))[1] == ((u8)0xff))) 1797 1798 /* RAH */ 1799 #define IXGBE_RAH_VIND_MASK 0x003C0000 1800 #define IXGBE_RAH_VIND_SHIFT 18 1801 #define IXGBE_RAH_AV 0x80000000 1802 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 1803 1804 /* Header split receive */ 1805 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001 1806 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 1807 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 1808 #define IXGBE_RFCTL_NFSW_DIS 0x00000040 1809 #define IXGBE_RFCTL_NFSR_DIS 0x00000080 1810 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 1811 #define IXGBE_RFCTL_NFS_VER_SHIFT 8 1812 #define IXGBE_RFCTL_NFS_VER_2 0 1813 #define IXGBE_RFCTL_NFS_VER_3 1 1814 #define IXGBE_RFCTL_NFS_VER_4 2 1815 #define IXGBE_RFCTL_IPV6_DIS 0x00000400 1816 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 1817 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 1818 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 1819 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 1820 1821 /* Transmit Config masks */ 1822 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 1823 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 1824 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 1825 /* Enable short packet padding to 64 bytes */ 1826 #define IXGBE_TX_PAD_ENABLE 0x00000400 1827 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 1828 /* This allows for 16K packets + 4k for vlan */ 1829 #define IXGBE_MAX_FRAME_SZ 0x40040000 1830 1831 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 1832 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 1833 1834 /* Receive Config masks */ 1835 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 1836 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 1837 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 1838 #define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ 1839 #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ 1840 #define IXGBE_RXDCTL_RLPML_EN 0x00008000 1841 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 1842 1843 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 1844 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 1845 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 1846 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 1847 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 1848 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 1849 /* Receive Priority Flow Control Enable */ 1850 #define IXGBE_FCTRL_RPFCE 0x00004000 1851 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 1852 #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 1853 #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 1854 #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 1855 #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 1856 #define IXGBE_MFLCN_RPFCE_MASK 0x00000FF0 /* Receive FC Mask */ 1857 1858 #define IXGBE_MFLCN_RPFCE_SHIFT 4 1859 1860 /* Multiple Receive Queue Control */ 1861 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 1862 #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 1863 #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 1864 #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 1865 #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 1866 #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 1867 #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 1868 #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 1869 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 1870 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 1871 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 1872 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 1873 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 1874 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 1875 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 1876 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 1877 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 1878 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 1879 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 1880 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 1881 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 1882 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000 1883 1884 /* Queue Drop Enable */ 1885 #define IXGBE_QDE_ENABLE 0x00000001 1886 #define IXGBE_QDE_IDX_MASK 0x00007F00 1887 #define IXGBE_QDE_IDX_SHIFT 8 1888 1889 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 1890 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 1891 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 1892 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 1893 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 1894 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 1895 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 1896 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 1897 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 1898 1899 #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 1900 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 1901 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 1902 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 1903 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 1904 /* Multiple Transmit Queue Command Register */ 1905 #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 1906 #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 1907 #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 1908 #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 1909 #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 1910 #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 1911 #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */ 1912 1913 /* Receive Descriptor bit definitions */ 1914 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 1915 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 1916 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 1917 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 1918 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 1919 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 1920 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 1921 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 1922 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 1923 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 1924 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 1925 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 1926 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 1927 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 1928 #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 1929 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 1930 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 1931 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 1932 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 1933 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 1934 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 1935 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 1936 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 1937 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 1938 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 1939 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 1940 #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 1941 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 1942 #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ 1943 #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 1944 #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 1945 #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 1946 #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 1947 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 1948 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 1949 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 1950 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 1951 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 1952 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 1953 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 1954 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 1955 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 1956 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 1957 #define IXGBE_RXD_PRI_SHIFT 13 1958 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 1959 #define IXGBE_RXD_CFI_SHIFT 12 1960 1961 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 1962 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 1963 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 1964 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 1965 #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 1966 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 1967 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 1968 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 1969 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 1970 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 1971 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 1972 1973 /* PSRTYPE bit definitions */ 1974 #define IXGBE_PSRTYPE_TCPHDR 0x00000010 1975 #define IXGBE_PSRTYPE_UDPHDR 0x00000020 1976 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 1977 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 1978 #define IXGBE_PSRTYPE_L2HDR 0x00001000 1979 1980 /* SRRCTL bit definitions */ 1981 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 1982 #define IXGBE_SRRCTL_RDMTS_SHIFT 22 1983 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 1984 #define IXGBE_SRRCTL_DROP_EN 0x10000000 1985 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 1986 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 1987 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 1988 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 1989 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 1990 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 1991 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 1992 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 1993 1994 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 1995 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 1996 1997 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 1998 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 1999 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 2000 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 2001 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 2002 #define IXGBE_RXDADV_RSCCNT_SHIFT 17 2003 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 2004 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 2005 #define IXGBE_RXDADV_SPH 0x8000 2006 2007 /* RSS Hash results */ 2008 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 2009 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 2010 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 2011 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 2012 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 2013 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 2014 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 2015 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 2016 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 2017 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 2018 2019 /* RSS Packet Types as indicated in the receive descriptor. */ 2020 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 2021 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 2022 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 2023 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 2024 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 2025 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 2026 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 2027 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 2028 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 2029 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 2030 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 2031 #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 2032 #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 2033 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 2034 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 2035 2036 /* Security Processing bit Indication */ 2037 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 2038 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 2039 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 2040 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 2041 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 2042 2043 /* Masks to determine if packets should be dropped due to frame errors */ 2044 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 2045 IXGBE_RXD_ERR_CE | \ 2046 IXGBE_RXD_ERR_LE | \ 2047 IXGBE_RXD_ERR_PE | \ 2048 IXGBE_RXD_ERR_OSE | \ 2049 IXGBE_RXD_ERR_USE) 2050 2051 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 2052 IXGBE_RXDADV_ERR_CE | \ 2053 IXGBE_RXDADV_ERR_LE | \ 2054 IXGBE_RXDADV_ERR_PE | \ 2055 IXGBE_RXDADV_ERR_OSE | \ 2056 IXGBE_RXDADV_ERR_USE) 2057 2058 /* Multicast bit mask */ 2059 #define IXGBE_MCSTCTRL_MFE 0x4 2060 2061 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2062 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 2063 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 2064 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 2065 2066 /* Vlan-specific macros */ 2067 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 2068 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 2069 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 2070 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 2071 2072 /* SR-IOV specific macros */ 2073 #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) 2074 #define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) 2075 #define IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600)) 2076 #define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) 2077 2078 enum ixgbe_fdir_pballoc_type { 2079 IXGBE_FDIR_PBALLOC_NONE = 0, 2080 IXGBE_FDIR_PBALLOC_64K = 1, 2081 IXGBE_FDIR_PBALLOC_128K = 2, 2082 IXGBE_FDIR_PBALLOC_256K = 3, 2083 }; 2084 #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16 2085 2086 /* Flow Director register values */ 2087 #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 2088 #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 2089 #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 2090 #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 2091 #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 2092 #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 2093 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 2094 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 2095 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16 2096 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 2097 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 2098 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 2099 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 2100 2101 #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 2102 #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 2103 #define IXGBE_FDIRIP6M_DIPM_SHIFT 16 2104 #define IXGBE_FDIRM_VLANID 0x00000001 2105 #define IXGBE_FDIRM_VLANP 0x00000002 2106 #define IXGBE_FDIRM_POOL 0x00000004 2107 #define IXGBE_FDIRM_L4P 0x00000008 2108 #define IXGBE_FDIRM_FLEX 0x00000010 2109 #define IXGBE_FDIRM_DIPv6 0x00000020 2110 2111 #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 2112 #define IXGBE_FDIRFREE_FREE_SHIFT 0 2113 #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 2114 #define IXGBE_FDIRFREE_COLL_SHIFT 16 2115 #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 2116 #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 2117 #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 2118 #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 2119 #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 2120 #define IXGBE_FDIRUSTAT_ADD_SHIFT 0 2121 #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 2122 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 2123 #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 2124 #define IXGBE_FDIRFSTAT_FADD_SHIFT 0 2125 #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 2126 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 2127 #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 2128 #define IXGBE_FDIRVLAN_FLEX_SHIFT 16 2129 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 2130 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 2131 2132 #define IXGBE_FDIRCMD_CMD_MASK 0x00000003 2133 #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 2134 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 2135 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 2136 #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 2137 #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 2138 #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 2139 #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 2140 #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 2141 #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 2142 #define IXGBE_FDIRCMD_IPV6 0x00000080 2143 #define IXGBE_FDIRCMD_CLEARHT 0x00000100 2144 #define IXGBE_FDIRCMD_DROP 0x00000200 2145 #define IXGBE_FDIRCMD_INT 0x00000400 2146 #define IXGBE_FDIRCMD_LAST 0x00000800 2147 #define IXGBE_FDIRCMD_COLLISION 0x00001000 2148 #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 2149 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 2150 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 2151 #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 2152 #define IXGBE_FDIR_INIT_DONE_POLL 10 2153 #define IXGBE_FDIRCMD_CMD_POLL 10 2154 2155 #define IXGBE_FDIR_DROP_QUEUE 127 2156 2157 /* Manageablility Host Interface defines */ 2158 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 2159 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 2160 #define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ 2161 2162 /* CEM Support */ 2163 #define FW_CEM_HDR_LEN 0x4 2164 #define FW_CEM_CMD_DRIVER_INFO 0xDD 2165 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 2166 #define FW_CEM_CMD_RESERVED 0x0 2167 #define FW_CEM_UNUSED_VER 0x0 2168 #define FW_CEM_MAX_RETRIES 3 2169 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 2170 2171 /* Host Interface Command Structures */ 2172 struct ixgbe_hic_hdr { 2173 u8 cmd; 2174 u8 buf_len; 2175 union { 2176 u8 cmd_resv; 2177 u8 ret_status; 2178 } cmd_or_resp; 2179 u8 checksum; 2180 }; 2181 2182 struct ixgbe_hic_drv_info { 2183 struct ixgbe_hic_hdr hdr; 2184 u8 port_num; 2185 u8 ver_sub; 2186 u8 ver_build; 2187 u8 ver_min; 2188 u8 ver_maj; 2189 u8 pad; /* end spacing to ensure length is mult. of dword */ 2190 u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 2191 }; 2192 2193 /* Transmit Descriptor - Advanced */ 2194 union ixgbe_adv_tx_desc { 2195 struct { 2196 __le64 buffer_addr; /* Address of descriptor's data buf */ 2197 __le32 cmd_type_len; 2198 __le32 olinfo_status; 2199 } read; 2200 struct { 2201 __le64 rsvd; /* Reserved */ 2202 __le32 nxtseq_seed; 2203 __le32 status; 2204 } wb; 2205 }; 2206 2207 /* Receive Descriptor - Advanced */ 2208 union ixgbe_adv_rx_desc { 2209 struct { 2210 __le64 pkt_addr; /* Packet buffer address */ 2211 __le64 hdr_addr; /* Header buffer address */ 2212 } read; 2213 struct { 2214 struct { 2215 union { 2216 __le32 data; 2217 struct { 2218 __le16 pkt_info; /* RSS, Pkt type */ 2219 __le16 hdr_info; /* Splithdr, hdrlen */ 2220 } hs_rss; 2221 } lo_dword; 2222 union { 2223 __le32 rss; /* RSS Hash */ 2224 struct { 2225 __le16 ip_id; /* IP id */ 2226 __le16 csum; /* Packet Checksum */ 2227 } csum_ip; 2228 } hi_dword; 2229 } lower; 2230 struct { 2231 __le32 status_error; /* ext status/error */ 2232 __le16 length; /* Packet length */ 2233 __le16 vlan; /* VLAN tag */ 2234 } upper; 2235 } wb; /* writeback */ 2236 }; 2237 2238 /* Context descriptors */ 2239 struct ixgbe_adv_tx_context_desc { 2240 __le32 vlan_macip_lens; 2241 __le32 seqnum_seed; 2242 __le32 type_tucmd_mlhl; 2243 __le32 mss_l4len_idx; 2244 }; 2245 2246 /* Adv Transmit Descriptor Config Masks */ 2247 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 2248 #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 2249 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 2250 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 2251 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 2252 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 2253 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 2254 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 2255 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 2256 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 2257 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 2258 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 2259 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 2260 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 2261 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 2262 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 2263 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 2264 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 2265 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 2266 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 2267 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 2268 IXGBE_ADVTXD_POPTS_SHIFT) 2269 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 2270 IXGBE_ADVTXD_POPTS_SHIFT) 2271 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 2272 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 2273 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 2274 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ 2275 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 2276 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 2277 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 2278 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 2279 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 2280 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 2281 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 2282 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 2283 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 2284 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ 2285 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 2286 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 2287 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 2288 #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 2289 #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 2290 #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 2291 #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 2292 #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */ 2293 #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */ 2294 #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 2295 #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 2296 #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 2297 #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 2298 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 2299 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 2300 2301 /* Autonegotiation advertised speeds */ 2302 typedef u32 ixgbe_autoneg_advertised; 2303 /* Link speed */ 2304 typedef u32 ixgbe_link_speed; 2305 #define IXGBE_LINK_SPEED_UNKNOWN 0 2306 #define IXGBE_LINK_SPEED_100_FULL 0x0008 2307 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 2308 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 2309 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 2310 IXGBE_LINK_SPEED_10GB_FULL) 2311 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 2312 IXGBE_LINK_SPEED_1GB_FULL | \ 2313 IXGBE_LINK_SPEED_10GB_FULL) 2314 2315 2316 /* Physical layer type */ 2317 typedef u32 ixgbe_physical_layer; 2318 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 2319 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 2320 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 2321 #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004 2322 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 2323 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 2324 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 2325 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040 2326 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080 2327 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 2328 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 2329 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 2330 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800 2331 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000 2332 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000 2333 2334 /* Flow Control Data Sheet defined values 2335 * Calculation and defines taken from 802.1bb Annex O 2336 */ 2337 2338 /* BitTimes (BT) conversion */ 2339 #define IXGBE_BT2KB(BT) ((BT + 1023) / (8 * 1024)) 2340 #define IXGBE_B2BT(BT) (BT * 8) 2341 2342 /* Calculate Delay to respond to PFC */ 2343 #define IXGBE_PFC_D 672 2344 2345 /* Calculate Cable Delay */ 2346 #define IXGBE_CABLE_DC 5556 /* Delay Copper */ 2347 #define IXGBE_CABLE_DO 5000 /* Delay Optical */ 2348 2349 /* Calculate Interface Delay X540 */ 2350 #define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ 2351 #define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ 2352 #define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ 2353 2354 #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) 2355 2356 /* Calculate Interface Delay 82598, 82599 */ 2357 #define IXGBE_PHY_D 12800 2358 #define IXGBE_MAC_D 4096 2359 #define IXGBE_XAUI_D (2 * 1024) 2360 2361 #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) 2362 2363 /* Calculate Delay incurred from higher layer */ 2364 #define IXGBE_HD 6144 2365 2366 /* Calculate PCI Bus delay for low thresholds */ 2367 #define IXGBE_PCI_DELAY 10000 2368 2369 /* Calculate X540 delay value in bit times */ 2370 #define IXGBE_FILL_RATE (36 / 25) 2371 2372 #define IXGBE_DV_X540(LINK, TC) (IXGBE_FILL_RATE * \ 2373 (IXGBE_B2BT(LINK) + IXGBE_PFC_D + \ 2374 (2 * IXGBE_CABLE_DC) + \ 2375 (2 * IXGBE_ID_X540) + \ 2376 IXGBE_HD + IXGBE_B2BT(TC))) 2377 2378 /* Calculate 82599, 82598 delay value in bit times */ 2379 #define IXGBE_DV(LINK, TC) (IXGBE_FILL_RATE * \ 2380 (IXGBE_B2BT(LINK) + IXGBE_PFC_D + \ 2381 (2 * IXGBE_CABLE_DC) + (2 * IXGBE_ID) + \ 2382 IXGBE_HD + IXGBE_B2BT(TC))) 2383 2384 /* Calculate low threshold delay values */ 2385 #define IXGBE_LOW_DV_X540(TC) (2 * IXGBE_B2BT(TC) + \ 2386 (IXGBE_FILL_RATE * IXGBE_PCI_DELAY)) 2387 #define IXGBE_LOW_DV(TC) (2 * IXGBE_LOW_DV_X540(TC)) 2388 2389 /* Software ATR hash keys */ 2390 #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 2391 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 2392 2393 /* Software ATR input stream values and masks */ 2394 #define IXGBE_ATR_HASH_MASK 0x7fff 2395 #define IXGBE_ATR_L4TYPE_MASK 0x3 2396 #define IXGBE_ATR_L4TYPE_UDP 0x1 2397 #define IXGBE_ATR_L4TYPE_TCP 0x2 2398 #define IXGBE_ATR_L4TYPE_SCTP 0x3 2399 #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 2400 enum ixgbe_atr_flow_type { 2401 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 2402 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 2403 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 2404 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 2405 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 2406 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 2407 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 2408 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 2409 }; 2410 2411 /* Flow Director ATR input struct. */ 2412 union ixgbe_atr_input { 2413 /* 2414 * Byte layout in order, all values with MSB first: 2415 * 2416 * vm_pool - 1 byte 2417 * flow_type - 1 byte 2418 * vlan_id - 2 bytes 2419 * src_ip - 16 bytes 2420 * dst_ip - 16 bytes 2421 * src_port - 2 bytes 2422 * dst_port - 2 bytes 2423 * flex_bytes - 2 bytes 2424 * bkt_hash - 2 bytes 2425 */ 2426 struct { 2427 u8 vm_pool; 2428 u8 flow_type; 2429 __be16 vlan_id; 2430 __be32 dst_ip[4]; 2431 __be32 src_ip[4]; 2432 __be16 src_port; 2433 __be16 dst_port; 2434 __be16 flex_bytes; 2435 __be16 bkt_hash; 2436 } formatted; 2437 __be32 dword_stream[11]; 2438 }; 2439 2440 /* Flow Director compressed ATR hash input struct */ 2441 union ixgbe_atr_hash_dword { 2442 struct { 2443 u8 vm_pool; 2444 u8 flow_type; 2445 __be16 vlan_id; 2446 } formatted; 2447 __be32 ip; 2448 struct { 2449 __be16 src; 2450 __be16 dst; 2451 } port; 2452 __be16 flex_bytes; 2453 __be32 dword; 2454 }; 2455 2456 enum ixgbe_eeprom_type { 2457 ixgbe_eeprom_uninitialized = 0, 2458 ixgbe_eeprom_spi, 2459 ixgbe_flash, 2460 ixgbe_eeprom_none /* No NVM support */ 2461 }; 2462 2463 enum ixgbe_mac_type { 2464 ixgbe_mac_unknown = 0, 2465 ixgbe_mac_82598EB, 2466 ixgbe_mac_82599EB, 2467 ixgbe_mac_X540, 2468 ixgbe_num_macs 2469 }; 2470 2471 enum ixgbe_phy_type { 2472 ixgbe_phy_unknown = 0, 2473 ixgbe_phy_none, 2474 ixgbe_phy_tn, 2475 ixgbe_phy_aq, 2476 ixgbe_phy_cu_unknown, 2477 ixgbe_phy_qt, 2478 ixgbe_phy_xaui, 2479 ixgbe_phy_nl, 2480 ixgbe_phy_sfp_passive_tyco, 2481 ixgbe_phy_sfp_passive_unknown, 2482 ixgbe_phy_sfp_active_unknown, 2483 ixgbe_phy_sfp_avago, 2484 ixgbe_phy_sfp_ftl, 2485 ixgbe_phy_sfp_ftl_active, 2486 ixgbe_phy_sfp_unknown, 2487 ixgbe_phy_sfp_intel, 2488 ixgbe_phy_sfp_unsupported, 2489 ixgbe_phy_generic 2490 }; 2491 2492 /* 2493 * SFP+ module type IDs: 2494 * 2495 * ID Module Type 2496 * ============= 2497 * 0 SFP_DA_CU 2498 * 1 SFP_SR 2499 * 2 SFP_LR 2500 * 3 SFP_DA_CU_CORE0 - 82599-specific 2501 * 4 SFP_DA_CU_CORE1 - 82599-specific 2502 * 5 SFP_SR/LR_CORE0 - 82599-specific 2503 * 6 SFP_SR/LR_CORE1 - 82599-specific 2504 */ 2505 enum ixgbe_sfp_type { 2506 ixgbe_sfp_type_da_cu = 0, 2507 ixgbe_sfp_type_sr = 1, 2508 ixgbe_sfp_type_lr = 2, 2509 ixgbe_sfp_type_da_cu_core0 = 3, 2510 ixgbe_sfp_type_da_cu_core1 = 4, 2511 ixgbe_sfp_type_srlr_core0 = 5, 2512 ixgbe_sfp_type_srlr_core1 = 6, 2513 ixgbe_sfp_type_da_act_lmt_core0 = 7, 2514 ixgbe_sfp_type_da_act_lmt_core1 = 8, 2515 ixgbe_sfp_type_1g_cu_core0 = 9, 2516 ixgbe_sfp_type_1g_cu_core1 = 10, 2517 ixgbe_sfp_type_not_present = 0xFFFE, 2518 ixgbe_sfp_type_unknown = 0xFFFF 2519 }; 2520 2521 enum ixgbe_media_type { 2522 ixgbe_media_type_unknown = 0, 2523 ixgbe_media_type_fiber, 2524 ixgbe_media_type_fiber_lco, 2525 ixgbe_media_type_copper, 2526 ixgbe_media_type_backplane, 2527 ixgbe_media_type_cx4, 2528 ixgbe_media_type_virtual 2529 }; 2530 2531 /* Flow Control Settings */ 2532 enum ixgbe_fc_mode { 2533 ixgbe_fc_none = 0, 2534 ixgbe_fc_rx_pause, 2535 ixgbe_fc_tx_pause, 2536 ixgbe_fc_full, 2537 #ifdef CONFIG_DCB 2538 ixgbe_fc_pfc, 2539 #endif 2540 ixgbe_fc_default 2541 }; 2542 2543 /* Smart Speed Settings */ 2544 #define IXGBE_SMARTSPEED_MAX_RETRIES 3 2545 enum ixgbe_smart_speed { 2546 ixgbe_smart_speed_auto = 0, 2547 ixgbe_smart_speed_on, 2548 ixgbe_smart_speed_off 2549 }; 2550 2551 /* PCI bus types */ 2552 enum ixgbe_bus_type { 2553 ixgbe_bus_type_unknown = 0, 2554 ixgbe_bus_type_pci, 2555 ixgbe_bus_type_pcix, 2556 ixgbe_bus_type_pci_express, 2557 ixgbe_bus_type_reserved 2558 }; 2559 2560 /* PCI bus speeds */ 2561 enum ixgbe_bus_speed { 2562 ixgbe_bus_speed_unknown = 0, 2563 ixgbe_bus_speed_33 = 33, 2564 ixgbe_bus_speed_66 = 66, 2565 ixgbe_bus_speed_100 = 100, 2566 ixgbe_bus_speed_120 = 120, 2567 ixgbe_bus_speed_133 = 133, 2568 ixgbe_bus_speed_2500 = 2500, 2569 ixgbe_bus_speed_5000 = 5000, 2570 ixgbe_bus_speed_reserved 2571 }; 2572 2573 /* PCI bus widths */ 2574 enum ixgbe_bus_width { 2575 ixgbe_bus_width_unknown = 0, 2576 ixgbe_bus_width_pcie_x1 = 1, 2577 ixgbe_bus_width_pcie_x2 = 2, 2578 ixgbe_bus_width_pcie_x4 = 4, 2579 ixgbe_bus_width_pcie_x8 = 8, 2580 ixgbe_bus_width_32 = 32, 2581 ixgbe_bus_width_64 = 64, 2582 ixgbe_bus_width_reserved 2583 }; 2584 2585 struct ixgbe_addr_filter_info { 2586 u32 num_mc_addrs; 2587 u32 rar_used_count; 2588 u32 mta_in_use; 2589 u32 overflow_promisc; 2590 bool uc_set_promisc; 2591 bool user_set_promisc; 2592 }; 2593 2594 /* Bus parameters */ 2595 struct ixgbe_bus_info { 2596 enum ixgbe_bus_speed speed; 2597 enum ixgbe_bus_width width; 2598 enum ixgbe_bus_type type; 2599 2600 u16 func; 2601 u16 lan_id; 2602 }; 2603 2604 /* Flow control parameters */ 2605 struct ixgbe_fc_info { 2606 u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */ 2607 u32 low_water; /* Flow Control Low-water */ 2608 u16 pause_time; /* Flow Control Pause timer */ 2609 bool send_xon; /* Flow control send XON */ 2610 bool strict_ieee; /* Strict IEEE mode */ 2611 bool disable_fc_autoneg; /* Do not autonegotiate FC */ 2612 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 2613 enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 2614 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 2615 }; 2616 2617 /* Statistics counters collected by the MAC */ 2618 struct ixgbe_hw_stats { 2619 u64 crcerrs; 2620 u64 illerrc; 2621 u64 errbc; 2622 u64 mspdc; 2623 u64 mpctotal; 2624 u64 mpc[8]; 2625 u64 mlfc; 2626 u64 mrfc; 2627 u64 rlec; 2628 u64 lxontxc; 2629 u64 lxonrxc; 2630 u64 lxofftxc; 2631 u64 lxoffrxc; 2632 u64 pxontxc[8]; 2633 u64 pxonrxc[8]; 2634 u64 pxofftxc[8]; 2635 u64 pxoffrxc[8]; 2636 u64 prc64; 2637 u64 prc127; 2638 u64 prc255; 2639 u64 prc511; 2640 u64 prc1023; 2641 u64 prc1522; 2642 u64 gprc; 2643 u64 bprc; 2644 u64 mprc; 2645 u64 gptc; 2646 u64 gorc; 2647 u64 gotc; 2648 u64 rnbc[8]; 2649 u64 ruc; 2650 u64 rfc; 2651 u64 roc; 2652 u64 rjc; 2653 u64 mngprc; 2654 u64 mngpdc; 2655 u64 mngptc; 2656 u64 tor; 2657 u64 tpr; 2658 u64 tpt; 2659 u64 ptc64; 2660 u64 ptc127; 2661 u64 ptc255; 2662 u64 ptc511; 2663 u64 ptc1023; 2664 u64 ptc1522; 2665 u64 mptc; 2666 u64 bptc; 2667 u64 xec; 2668 u64 rqsmr[16]; 2669 u64 tqsmr[8]; 2670 u64 qprc[16]; 2671 u64 qptc[16]; 2672 u64 qbrc[16]; 2673 u64 qbtc[16]; 2674 u64 qprdc[16]; 2675 u64 pxon2offc[8]; 2676 u64 fdirustat_add; 2677 u64 fdirustat_remove; 2678 u64 fdirfstat_fadd; 2679 u64 fdirfstat_fremove; 2680 u64 fdirmatch; 2681 u64 fdirmiss; 2682 u64 fccrc; 2683 u64 fcoerpdc; 2684 u64 fcoeprc; 2685 u64 fcoeptc; 2686 u64 fcoedwrc; 2687 u64 fcoedwtc; 2688 u64 fcoe_noddp; 2689 u64 fcoe_noddp_ext_buff; 2690 u64 b2ospc; 2691 u64 b2ogprc; 2692 u64 o2bgptc; 2693 u64 o2bspc; 2694 }; 2695 2696 /* forward declaration */ 2697 struct ixgbe_hw; 2698 2699 /* iterator type for walking multicast address lists */ 2700 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 2701 u32 *vmdq); 2702 2703 /* Function pointer table */ 2704 struct ixgbe_eeprom_operations { 2705 s32 (*init_params)(struct ixgbe_hw *); 2706 s32 (*read)(struct ixgbe_hw *, u16, u16 *); 2707 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 2708 s32 (*write)(struct ixgbe_hw *, u16, u16); 2709 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 2710 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 2711 s32 (*update_checksum)(struct ixgbe_hw *); 2712 u16 (*calc_checksum)(struct ixgbe_hw *); 2713 }; 2714 2715 struct ixgbe_mac_operations { 2716 s32 (*init_hw)(struct ixgbe_hw *); 2717 s32 (*reset_hw)(struct ixgbe_hw *); 2718 s32 (*start_hw)(struct ixgbe_hw *); 2719 s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 2720 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 2721 u32 (*get_supported_physical_layer)(struct ixgbe_hw *); 2722 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 2723 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 2724 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 2725 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 2726 s32 (*stop_adapter)(struct ixgbe_hw *); 2727 s32 (*get_bus_info)(struct ixgbe_hw *); 2728 void (*set_lan_id)(struct ixgbe_hw *); 2729 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 2730 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 2731 s32 (*setup_sfp)(struct ixgbe_hw *); 2732 s32 (*disable_rx_buff)(struct ixgbe_hw *); 2733 s32 (*enable_rx_buff)(struct ixgbe_hw *); 2734 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 2735 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16); 2736 void (*release_swfw_sync)(struct ixgbe_hw *, u16); 2737 2738 /* Link */ 2739 void (*disable_tx_laser)(struct ixgbe_hw *); 2740 void (*enable_tx_laser)(struct ixgbe_hw *); 2741 void (*flap_tx_laser)(struct ixgbe_hw *); 2742 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool); 2743 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 2744 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 2745 bool *); 2746 2747 /* Packet Buffer Manipulation */ 2748 void (*set_rxpba)(struct ixgbe_hw *, int, u32, int); 2749 2750 /* LED */ 2751 s32 (*led_on)(struct ixgbe_hw *, u32); 2752 s32 (*led_off)(struct ixgbe_hw *, u32); 2753 s32 (*blink_led_start)(struct ixgbe_hw *, u32); 2754 s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 2755 2756 /* RAR, Multicast, VLAN */ 2757 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 2758 s32 (*clear_rar)(struct ixgbe_hw *, u32); 2759 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 2760 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 2761 s32 (*init_rx_addrs)(struct ixgbe_hw *); 2762 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *); 2763 s32 (*enable_mc)(struct ixgbe_hw *); 2764 s32 (*disable_mc)(struct ixgbe_hw *); 2765 s32 (*clear_vfta)(struct ixgbe_hw *); 2766 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); 2767 s32 (*init_uta_tables)(struct ixgbe_hw *); 2768 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); 2769 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); 2770 2771 /* Flow Control */ 2772 s32 (*fc_enable)(struct ixgbe_hw *, s32); 2773 2774 /* Manageability interface */ 2775 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8); 2776 }; 2777 2778 struct ixgbe_phy_operations { 2779 s32 (*identify)(struct ixgbe_hw *); 2780 s32 (*identify_sfp)(struct ixgbe_hw *); 2781 s32 (*init)(struct ixgbe_hw *); 2782 s32 (*reset)(struct ixgbe_hw *); 2783 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 2784 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 2785 s32 (*setup_link)(struct ixgbe_hw *); 2786 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool, 2787 bool); 2788 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 2789 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 2790 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 2791 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 2792 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 2793 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 2794 s32 (*check_overtemp)(struct ixgbe_hw *); 2795 }; 2796 2797 struct ixgbe_eeprom_info { 2798 struct ixgbe_eeprom_operations ops; 2799 enum ixgbe_eeprom_type type; 2800 u32 semaphore_delay; 2801 u16 word_size; 2802 u16 address_bits; 2803 u16 word_page_size; 2804 }; 2805 2806 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 2807 struct ixgbe_mac_info { 2808 struct ixgbe_mac_operations ops; 2809 enum ixgbe_mac_type type; 2810 u8 addr[ETH_ALEN]; 2811 u8 perm_addr[ETH_ALEN]; 2812 u8 san_addr[ETH_ALEN]; 2813 /* prefix for World Wide Node Name (WWNN) */ 2814 u16 wwnn_prefix; 2815 /* prefix for World Wide Port Name (WWPN) */ 2816 u16 wwpn_prefix; 2817 #define IXGBE_MAX_MTA 128 2818 u32 mta_shadow[IXGBE_MAX_MTA]; 2819 s32 mc_filter_type; 2820 u32 mcft_size; 2821 u32 vft_size; 2822 u32 num_rar_entries; 2823 u32 rar_highwater; 2824 u32 rx_pb_size; 2825 u32 max_tx_queues; 2826 u32 max_rx_queues; 2827 u32 max_msix_vectors; 2828 u32 orig_autoc; 2829 u32 orig_autoc2; 2830 bool orig_link_settings_stored; 2831 bool autotry_restart; 2832 u8 flags; 2833 }; 2834 2835 struct ixgbe_phy_info { 2836 struct ixgbe_phy_operations ops; 2837 struct mdio_if_info mdio; 2838 enum ixgbe_phy_type type; 2839 u32 id; 2840 enum ixgbe_sfp_type sfp_type; 2841 bool sfp_setup_needed; 2842 u32 revision; 2843 enum ixgbe_media_type media_type; 2844 bool reset_disable; 2845 ixgbe_autoneg_advertised autoneg_advertised; 2846 enum ixgbe_smart_speed smart_speed; 2847 bool smart_speed_active; 2848 bool multispeed_fiber; 2849 bool reset_if_overtemp; 2850 }; 2851 2852 #include "ixgbe_mbx.h" 2853 2854 struct ixgbe_mbx_operations { 2855 s32 (*init_params)(struct ixgbe_hw *hw); 2856 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); 2857 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); 2858 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); 2859 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); 2860 s32 (*check_for_msg)(struct ixgbe_hw *, u16); 2861 s32 (*check_for_ack)(struct ixgbe_hw *, u16); 2862 s32 (*check_for_rst)(struct ixgbe_hw *, u16); 2863 }; 2864 2865 struct ixgbe_mbx_stats { 2866 u32 msgs_tx; 2867 u32 msgs_rx; 2868 2869 u32 acks; 2870 u32 reqs; 2871 u32 rsts; 2872 }; 2873 2874 struct ixgbe_mbx_info { 2875 struct ixgbe_mbx_operations ops; 2876 struct ixgbe_mbx_stats stats; 2877 u32 timeout; 2878 u32 usec_delay; 2879 u32 v2p_mailbox; 2880 u16 size; 2881 }; 2882 2883 struct ixgbe_hw { 2884 u8 __iomem *hw_addr; 2885 void *back; 2886 struct ixgbe_mac_info mac; 2887 struct ixgbe_addr_filter_info addr_ctrl; 2888 struct ixgbe_fc_info fc; 2889 struct ixgbe_phy_info phy; 2890 struct ixgbe_eeprom_info eeprom; 2891 struct ixgbe_bus_info bus; 2892 struct ixgbe_mbx_info mbx; 2893 u16 device_id; 2894 u16 vendor_id; 2895 u16 subsystem_device_id; 2896 u16 subsystem_vendor_id; 2897 u8 revision_id; 2898 bool adapter_stopped; 2899 bool force_full_reset; 2900 bool allow_unsupported_sfp; 2901 }; 2902 2903 struct ixgbe_info { 2904 enum ixgbe_mac_type mac; 2905 s32 (*get_invariants)(struct ixgbe_hw *); 2906 struct ixgbe_mac_operations *mac_ops; 2907 struct ixgbe_eeprom_operations *eeprom_ops; 2908 struct ixgbe_phy_operations *phy_ops; 2909 struct ixgbe_mbx_operations *mbx_ops; 2910 }; 2911 2912 2913 /* Error Codes */ 2914 #define IXGBE_ERR_EEPROM -1 2915 #define IXGBE_ERR_EEPROM_CHECKSUM -2 2916 #define IXGBE_ERR_PHY -3 2917 #define IXGBE_ERR_CONFIG -4 2918 #define IXGBE_ERR_PARAM -5 2919 #define IXGBE_ERR_MAC_TYPE -6 2920 #define IXGBE_ERR_UNKNOWN_PHY -7 2921 #define IXGBE_ERR_LINK_SETUP -8 2922 #define IXGBE_ERR_ADAPTER_STOPPED -9 2923 #define IXGBE_ERR_INVALID_MAC_ADDR -10 2924 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 2925 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 2926 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13 2927 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 2928 #define IXGBE_ERR_RESET_FAILED -15 2929 #define IXGBE_ERR_SWFW_SYNC -16 2930 #define IXGBE_ERR_PHY_ADDR_INVALID -17 2931 #define IXGBE_ERR_I2C -18 2932 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19 2933 #define IXGBE_ERR_SFP_NOT_PRESENT -20 2934 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 2935 #define IXGBE_ERR_NO_SAN_ADDR_PTR -22 2936 #define IXGBE_ERR_FDIR_REINIT_FAILED -23 2937 #define IXGBE_ERR_EEPROM_VERSION -24 2938 #define IXGBE_ERR_NO_SPACE -25 2939 #define IXGBE_ERR_OVERTEMP -26 2940 #define IXGBE_ERR_FC_NOT_NEGOTIATED -27 2941 #define IXGBE_ERR_FC_NOT_SUPPORTED -28 2942 #define IXGBE_ERR_FLOW_CONTROL -29 2943 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 2944 #define IXGBE_ERR_PBA_SECTION -31 2945 #define IXGBE_ERR_INVALID_ARGUMENT -32 2946 #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 2947 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 2948 2949 #endif /* _IXGBE_TYPE_H_ */ 2950