1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3  * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
4  * Copyright (C) 2016-2017 Intel Deutschland GmbH
5  * Copyright (C) 2018-2023 Intel Corporation
6  */
7 #ifndef __IWL_CONFIG_H__
8 #define __IWL_CONFIG_H__
9 
10 #include <linux/types.h>
11 #include <linux/netdevice.h>
12 #include <linux/ieee80211.h>
13 #include <linux/nl80211.h>
14 #include "iwl-csr.h"
15 
16 enum iwl_device_family {
17 	IWL_DEVICE_FAMILY_UNDEFINED,
18 	IWL_DEVICE_FAMILY_1000,
19 	IWL_DEVICE_FAMILY_100,
20 	IWL_DEVICE_FAMILY_2000,
21 	IWL_DEVICE_FAMILY_2030,
22 	IWL_DEVICE_FAMILY_105,
23 	IWL_DEVICE_FAMILY_135,
24 	IWL_DEVICE_FAMILY_5000,
25 	IWL_DEVICE_FAMILY_5150,
26 	IWL_DEVICE_FAMILY_6000,
27 	IWL_DEVICE_FAMILY_6000i,
28 	IWL_DEVICE_FAMILY_6005,
29 	IWL_DEVICE_FAMILY_6030,
30 	IWL_DEVICE_FAMILY_6050,
31 	IWL_DEVICE_FAMILY_6150,
32 	IWL_DEVICE_FAMILY_7000,
33 	IWL_DEVICE_FAMILY_8000,
34 	IWL_DEVICE_FAMILY_9000,
35 	IWL_DEVICE_FAMILY_22000,
36 	IWL_DEVICE_FAMILY_AX210,
37 	IWL_DEVICE_FAMILY_BZ,
38 	IWL_DEVICE_FAMILY_SC,
39 };
40 
41 /*
42  * LED mode
43  *    IWL_LED_DEFAULT:  use device default
44  *    IWL_LED_RF_STATE: turn LED on/off based on RF state
45  *			LED ON  = RF ON
46  *			LED OFF = RF OFF
47  *    IWL_LED_BLINK:    adjust led blink rate based on blink table
48  *    IWL_LED_DISABLE:	led disabled
49  */
50 enum iwl_led_mode {
51 	IWL_LED_DEFAULT,
52 	IWL_LED_RF_STATE,
53 	IWL_LED_BLINK,
54 	IWL_LED_DISABLE,
55 };
56 
57 /**
58  * enum iwl_nvm_type - nvm formats
59  * @IWL_NVM: the regular format
60  * @IWL_NVM_EXT: extended NVM format
61  * @IWL_NVM_SDP: NVM format used by 3168 series
62  */
63 enum iwl_nvm_type {
64 	IWL_NVM,
65 	IWL_NVM_EXT,
66 	IWL_NVM_SDP,
67 };
68 
69 /*
70  * This is the threshold value of plcp error rate per 100mSecs.  It is
71  * used to set and check for the validity of plcp_delta.
72  */
73 #define IWL_MAX_PLCP_ERR_THRESHOLD_MIN		1
74 #define IWL_MAX_PLCP_ERR_THRESHOLD_DEF		50
75 #define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF	100
76 #define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF	200
77 #define IWL_MAX_PLCP_ERR_THRESHOLD_MAX		255
78 #define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE	0
79 
80 /* TX queue watchdog timeouts in mSecs */
81 #define IWL_WATCHDOG_DISABLED	0
82 #define IWL_DEF_WD_TIMEOUT	2500
83 #define IWL_LONG_WD_TIMEOUT	10000
84 #define IWL_MAX_WD_TIMEOUT	120000
85 
86 #define IWL_DEFAULT_MAX_TX_POWER 22
87 #define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\
88 				 NETIF_F_TSO | NETIF_F_TSO6)
89 #define IWL_CSUM_NETIF_FLAGS_MASK (IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM)
90 
91 /* Antenna presence definitions */
92 #define	ANT_NONE	0x0
93 #define	ANT_INVALID	0xff
94 #define	ANT_A		BIT(0)
95 #define	ANT_B		BIT(1)
96 #define ANT_C		BIT(2)
97 #define	ANT_AB		(ANT_A | ANT_B)
98 #define	ANT_AC		(ANT_A | ANT_C)
99 #define ANT_BC		(ANT_B | ANT_C)
100 #define ANT_ABC		(ANT_A | ANT_B | ANT_C)
101 
102 
num_of_ant(u8 mask)103 static inline u8 num_of_ant(u8 mask)
104 {
105 	return  !!((mask) & ANT_A) +
106 		!!((mask) & ANT_B) +
107 		!!((mask) & ANT_C);
108 }
109 
110 /**
111  * struct iwl_base_params - params not likely to change within a device family
112  * @max_ll_items: max number of OTP blocks
113  * @shadow_ram_support: shadow support for OTP memory
114  * @led_compensation: compensate on the led on/off time per HW according
115  *	to the deviation to achieve the desired led frequency.
116  *	The detail algorithm is described in iwl-led.c
117  * @wd_timeout: TX queues watchdog timeout
118  * @max_event_log_size: size of event log buffer size for ucode event logging
119  * @shadow_reg_enable: HW shadow register support
120  * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command
121  *	is in flight. This is due to a HW bug in 7260, 3160 and 7265.
122  * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled.
123  * @max_tfd_queue_size: max number of entries in tfd queue.
124  */
125 struct iwl_base_params {
126 	unsigned int wd_timeout;
127 
128 	u16 eeprom_size;
129 	u16 max_event_log_size;
130 
131 	u8 pll_cfg:1, /* for iwl_pcie_apm_init() */
132 	   shadow_ram_support:1,
133 	   shadow_reg_enable:1,
134 	   pcie_l1_allowed:1,
135 	   apmg_wake_up_wa:1,
136 	   scd_chain_ext_wa:1;
137 
138 	u16 num_of_queues;	/* def: HW dependent */
139 	u32 max_tfd_queue_size;	/* def: HW dependent */
140 
141 	u8 max_ll_items;
142 	u8 led_compensation;
143 };
144 
145 /*
146  * @stbc: support Tx STBC and 1*SS Rx STBC
147  * @ldpc: support Tx/Rx with LDPC
148  * @use_rts_for_aggregation: use rts/cts protection for HT traffic
149  * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40
150  */
151 struct iwl_ht_params {
152 	u8 ht_greenfield_support:1,
153 	   stbc:1,
154 	   ldpc:1,
155 	   use_rts_for_aggregation:1;
156 	u8 ht40_bands;
157 };
158 
159 /*
160  * Tx-backoff threshold
161  * @temperature: The threshold in Celsius
162  * @backoff: The tx-backoff in uSec
163  */
164 struct iwl_tt_tx_backoff {
165 	s32 temperature;
166 	u32 backoff;
167 };
168 
169 #define TT_TX_BACKOFF_SIZE 6
170 
171 /**
172  * struct iwl_tt_params - thermal throttling parameters
173  * @ct_kill_entry: CT Kill entry threshold
174  * @ct_kill_exit: CT Kill exit threshold
175  * @ct_kill_duration: The time  intervals (in uSec) in which the driver needs
176  *	to checks whether to exit CT Kill.
177  * @dynamic_smps_entry: Dynamic SMPS entry threshold
178  * @dynamic_smps_exit: Dynamic SMPS exit threshold
179  * @tx_protection_entry: TX protection entry threshold
180  * @tx_protection_exit: TX protection exit threshold
181  * @tx_backoff: Array of thresholds for tx-backoff , in ascending order.
182  * @support_ct_kill: Support CT Kill?
183  * @support_dynamic_smps: Support dynamic SMPS?
184  * @support_tx_protection: Support tx protection?
185  * @support_tx_backoff: Support tx-backoff?
186  */
187 struct iwl_tt_params {
188 	u32 ct_kill_entry;
189 	u32 ct_kill_exit;
190 	u32 ct_kill_duration;
191 	u32 dynamic_smps_entry;
192 	u32 dynamic_smps_exit;
193 	u32 tx_protection_entry;
194 	u32 tx_protection_exit;
195 	struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE];
196 	u8 support_ct_kill:1,
197 	   support_dynamic_smps:1,
198 	   support_tx_protection:1,
199 	   support_tx_backoff:1;
200 };
201 
202 /*
203  * information on how to parse the EEPROM
204  */
205 #define EEPROM_REG_BAND_1_CHANNELS		0x08
206 #define EEPROM_REG_BAND_2_CHANNELS		0x26
207 #define EEPROM_REG_BAND_3_CHANNELS		0x42
208 #define EEPROM_REG_BAND_4_CHANNELS		0x5C
209 #define EEPROM_REG_BAND_5_CHANNELS		0x74
210 #define EEPROM_REG_BAND_24_HT40_CHANNELS	0x82
211 #define EEPROM_REG_BAND_52_HT40_CHANNELS	0x92
212 #define EEPROM_6000_REG_BAND_24_HT40_CHANNELS	0x80
213 #define EEPROM_REGULATORY_BAND_NO_HT40		0
214 
215 /* lower blocks contain EEPROM image and calibration data */
216 #define OTP_LOW_IMAGE_SIZE_2K		(2 * 512 * sizeof(u16))  /*  2 KB */
217 #define OTP_LOW_IMAGE_SIZE_16K		(16 * 512 * sizeof(u16)) /* 16 KB */
218 #define OTP_LOW_IMAGE_SIZE_32K		(32 * 512 * sizeof(u16)) /* 32 KB */
219 
220 struct iwl_eeprom_params {
221 	const u8 regulatory_bands[7];
222 	bool enhanced_txpower;
223 };
224 
225 /* Tx-backoff power threshold
226  * @pwr: The power limit in mw
227  * @backoff: The tx-backoff in uSec
228  */
229 struct iwl_pwr_tx_backoff {
230 	u32 pwr;
231 	u32 backoff;
232 };
233 
234 enum iwl_cfg_trans_ltr_delay {
235 	IWL_CFG_TRANS_LTR_DELAY_NONE	= 0,
236 	IWL_CFG_TRANS_LTR_DELAY_200US	= 1,
237 	IWL_CFG_TRANS_LTR_DELAY_2500US	= 2,
238 	IWL_CFG_TRANS_LTR_DELAY_1820US	= 3,
239 };
240 
241 /**
242  * struct iwl_cfg_trans - information needed to start the trans
243  *
244  * These values are specific to the device ID and do not change when
245  * multiple configs are used for a single device ID.  They values are
246  * used, among other things, to boot the NIC so that the HW REV or
247  * RFID can be read before deciding the remaining parameters to use.
248  *
249  * @base_params: pointer to basic parameters
250  * @csr: csr flags and addresses that are different across devices
251  * @device_family: the device family
252  * @umac_prph_offset: offset to add to UMAC periphery address
253  * @xtal_latency: power up latency to get the xtal stabilized
254  * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY
255  * @rf_id: need to read rf_id to determine the firmware image
256  * @gen2: 22000 and on transport operation
257  * @mq_rx_supported: multi-queue rx support
258  * @integrated: discrete or integrated
259  * @low_latency_xtal: use the low latency xtal if supported
260  * @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay.
261  * @imr_enabled: use the IMR if supported.
262  */
263 struct iwl_cfg_trans_params {
264 	const struct iwl_base_params *base_params;
265 	enum iwl_device_family device_family;
266 	u32 umac_prph_offset;
267 	u32 xtal_latency;
268 	u32 extra_phy_cfg_flags;
269 	u32 rf_id:1,
270 	    gen2:1,
271 	    mq_rx_supported:1,
272 	    integrated:1,
273 	    low_latency_xtal:1,
274 	    bisr_workaround:1,
275 	    ltr_delay:2,
276 	    imr_enabled:1;
277 };
278 
279 /**
280  * struct iwl_fw_mon_reg - FW monitor register info
281  * @addr: register address
282  * @mask: register mask
283  */
284 struct iwl_fw_mon_reg {
285 	u32 addr;
286 	u32 mask;
287 };
288 
289 /**
290  * struct iwl_fw_mon_regs - FW monitor registers
291  * @write_ptr: write pointer register
292  * @cycle_cnt: cycle count register
293  * @cur_frag: current fragment in use
294  */
295 struct iwl_fw_mon_regs {
296 	struct iwl_fw_mon_reg write_ptr;
297 	struct iwl_fw_mon_reg cycle_cnt;
298 	struct iwl_fw_mon_reg cur_frag;
299 };
300 
301 /**
302  * struct iwl_cfg
303  * @trans: the trans-specific configuration part
304  * @name: Official name of the device
305  * @fw_name_pre: Firmware filename prefix. The api version and extension
306  *	(.ucode) will be added to filename before loading from disk. The
307  *	filename is constructed as <fw_name_pre>-<api>.ucode.
308  * @fw_name_mac: MAC name for this config, the remaining pieces of the
309  *	name will be generated dynamically
310  * @ucode_api_max: Highest version of uCode API supported by driver.
311  * @ucode_api_min: Lowest version of uCode API supported by driver.
312  * @max_inst_size: The maximal length of the fw inst section (only DVM)
313  * @max_data_size: The maximal length of the fw data section (only DVM)
314  * @valid_tx_ant: valid transmit antenna
315  * @valid_rx_ant: valid receive antenna
316  * @non_shared_ant: the antenna that is for WiFi only
317  * @nvm_ver: NVM version
318  * @nvm_calib_ver: NVM calibration version
319  * @lib: pointer to the lib ops
320  * @ht_params: point to ht parameters
321  * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
322  * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
323  * @tx_with_siso_diversity: 1x1 device with tx antenna diversity
324  * @internal_wimax_coex: internal wifi/wimax combo device
325  * @high_temp: Is this NIC is designated to be in high temperature.
326  * @host_interrupt_operation_mode: device needs host interrupt operation
327  *	mode set
328  * @nvm_hw_section_num: the ID of the HW NVM section
329  * @mac_addr_from_csr: read HW address from CSR registers at this offset
330  * @features: hw features, any combination of feature_passlist
331  * @pwr_tx_backoffs: translation table between power limits and backoffs
332  * @max_tx_agg_size: max TX aggregation size of the ADDBA request/response
333  * @dccm_offset: offset from which DCCM begins
334  * @dccm_len: length of DCCM (including runtime stack CCM)
335  * @dccm2_offset: offset from which the second DCCM begins
336  * @dccm2_len: length of the second DCCM
337  * @smem_offset: offset from which the SMEM begins
338  * @smem_len: the length of SMEM
339  * @vht_mu_mimo_supported: VHT MU-MIMO support
340  * @cdb: CDB support
341  * @nvm_type: see &enum iwl_nvm_type
342  * @d3_debug_data_base_addr: base address where D3 debug data is stored
343  * @d3_debug_data_length: length of the D3 debug data
344  * @bisr_workaround: BISR hardware workaround (for 22260 series devices)
345  * @min_txq_size: minimum number of slots required in a TX queue
346  * @uhb_supported: ultra high band channels supported
347  * @min_ba_txq_size: minimum number of slots required in a TX queue which
348  *	based on hardware support (HE - 256, EHT - 1K).
349  * @num_rbds: number of receive buffer descriptors to use
350  *	(only used for multi-queue capable devices)
351  * @mac_addr_csr_base: CSR base register for MAC address access, if not set
352  *	assume 0x380
353  *
354  * We enable the driver to be backward compatible wrt. hardware features.
355  * API differences in uCode shouldn't be handled here but through TLVs
356  * and/or the uCode API version instead.
357  */
358 struct iwl_cfg {
359 	struct iwl_cfg_trans_params trans;
360 	/* params specific to an individual device within a device family */
361 	const char *name;
362 	const char *fw_name_pre;
363 	const char *fw_name_mac;
364 	/* params likely to change within a device family */
365 	const struct iwl_ht_params *ht_params;
366 	const struct iwl_eeprom_params *eeprom_params;
367 	const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
368 	const char *default_nvm_file_C_step;
369 	const struct iwl_tt_params *thermal_params;
370 	enum iwl_led_mode led_mode;
371 	enum iwl_nvm_type nvm_type;
372 	u32 max_data_size;
373 	u32 max_inst_size;
374 	netdev_features_t features;
375 	u32 dccm_offset;
376 	u32 dccm_len;
377 	u32 dccm2_offset;
378 	u32 dccm2_len;
379 	u32 smem_offset;
380 	u32 smem_len;
381 	u16 nvm_ver;
382 	u16 nvm_calib_ver;
383 	u32 rx_with_siso_diversity:1,
384 	    tx_with_siso_diversity:1,
385 	    bt_shared_single_ant:1,
386 	    internal_wimax_coex:1,
387 	    host_interrupt_operation_mode:1,
388 	    high_temp:1,
389 	    mac_addr_from_csr:10,
390 	    lp_xtal_workaround:1,
391 	    apmg_not_supported:1,
392 	    vht_mu_mimo_supported:1,
393 	    cdb:1,
394 	    dbgc_supported:1,
395 	    uhb_supported:1;
396 	u8 valid_tx_ant;
397 	u8 valid_rx_ant;
398 	u8 non_shared_ant;
399 	u8 nvm_hw_section_num;
400 	u8 max_tx_agg_size;
401 	u8 ucode_api_max;
402 	u8 ucode_api_min;
403 	u16 num_rbds;
404 	u32 min_umac_error_event_table;
405 	u32 d3_debug_data_base_addr;
406 	u32 d3_debug_data_length;
407 	u32 min_txq_size;
408 	u32 gp2_reg_addr;
409 	u32 min_ba_txq_size;
410 	const struct iwl_fw_mon_regs mon_dram_regs;
411 	const struct iwl_fw_mon_regs mon_smem_regs;
412 	const struct iwl_fw_mon_regs mon_dbgi_regs;
413 };
414 
415 #define IWL_CFG_ANY (~0)
416 
417 #define IWL_CFG_MAC_TYPE_PU		0x31
418 #define IWL_CFG_MAC_TYPE_TH		0x32
419 #define IWL_CFG_MAC_TYPE_QU		0x33
420 #define IWL_CFG_MAC_TYPE_QUZ		0x35
421 #define IWL_CFG_MAC_TYPE_SO		0x37
422 #define IWL_CFG_MAC_TYPE_SOF		0x43
423 #define IWL_CFG_MAC_TYPE_MA		0x44
424 #define IWL_CFG_MAC_TYPE_BZ		0x46
425 #define IWL_CFG_MAC_TYPE_GL		0x47
426 #define IWL_CFG_MAC_TYPE_SC		0x48
427 
428 #define IWL_CFG_RF_TYPE_TH		0x105
429 #define IWL_CFG_RF_TYPE_TH1		0x108
430 #define IWL_CFG_RF_TYPE_JF2		0x105
431 #define IWL_CFG_RF_TYPE_JF1		0x108
432 #define IWL_CFG_RF_TYPE_HR2		0x10A
433 #define IWL_CFG_RF_TYPE_HR1		0x10C
434 #define IWL_CFG_RF_TYPE_GF		0x10D
435 #define IWL_CFG_RF_TYPE_MR		0x110
436 #define IWL_CFG_RF_TYPE_MS		0x111
437 #define IWL_CFG_RF_TYPE_FM		0x112
438 #define IWL_CFG_RF_TYPE_WH		0x113
439 
440 #define IWL_CFG_RF_ID_TH		0x1
441 #define IWL_CFG_RF_ID_TH1		0x1
442 #define IWL_CFG_RF_ID_JF		0x3
443 #define IWL_CFG_RF_ID_JF1		0x6
444 #define IWL_CFG_RF_ID_JF1_DIV		0xA
445 #define IWL_CFG_RF_ID_HR		0x7
446 #define IWL_CFG_RF_ID_HR1		0x4
447 
448 #define IWL_CFG_NO_160			0x1
449 #define IWL_CFG_160			0x0
450 
451 #define IWL_CFG_CORES_BT		0x0
452 #define IWL_CFG_CORES_BT_GNSS		0x5
453 
454 #define IWL_CFG_NO_CDB			0x0
455 #define IWL_CFG_CDB			0x1
456 
457 #define IWL_CFG_NO_JACKET		0x0
458 #define IWL_CFG_IS_JACKET		0x1
459 
460 #define IWL_SUBDEVICE_RF_ID(subdevice)	((u16)((subdevice) & 0x00F0) >> 4)
461 #define IWL_SUBDEVICE_NO_160(subdevice)	((u16)((subdevice) & 0x0200) >> 9)
462 #define IWL_SUBDEVICE_CORES(subdevice)	((u16)((subdevice) & 0x1C00) >> 10)
463 
464 struct iwl_dev_info {
465 	u16 device;
466 	u16 subdevice;
467 	u16 mac_type;
468 	u16 rf_type;
469 	u8 mac_step;
470 	u8 rf_step;
471 	u8 rf_id;
472 	u8 no_160;
473 	u8 cores;
474 	u8 cdb;
475 	u8 jacket;
476 	const struct iwl_cfg *cfg;
477 	const char *name;
478 };
479 
480 /*
481  * This list declares the config structures for all devices.
482  */
483 extern const struct iwl_cfg_trans_params iwl9000_trans_cfg;
484 extern const struct iwl_cfg_trans_params iwl9560_trans_cfg;
485 extern const struct iwl_cfg_trans_params iwl9560_long_latency_trans_cfg;
486 extern const struct iwl_cfg_trans_params iwl9560_shared_clk_trans_cfg;
487 extern const struct iwl_cfg_trans_params iwl_qu_trans_cfg;
488 extern const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg;
489 extern const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg;
490 extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg;
491 extern const struct iwl_cfg_trans_params iwl_so_trans_cfg;
492 extern const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg;
493 extern const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg;
494 extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg;
495 extern const struct iwl_cfg_trans_params iwl_bz_trans_cfg;
496 extern const struct iwl_cfg_trans_params iwl_sc_trans_cfg;
497 extern const char iwl9162_name[];
498 extern const char iwl9260_name[];
499 extern const char iwl9260_1_name[];
500 extern const char iwl9270_name[];
501 extern const char iwl9461_name[];
502 extern const char iwl9462_name[];
503 extern const char iwl9560_name[];
504 extern const char iwl9162_160_name[];
505 extern const char iwl9260_160_name[];
506 extern const char iwl9270_160_name[];
507 extern const char iwl9461_160_name[];
508 extern const char iwl9462_160_name[];
509 extern const char iwl9560_160_name[];
510 extern const char iwl9260_killer_1550_name[];
511 extern const char iwl9560_killer_1550i_name[];
512 extern const char iwl9560_killer_1550s_name[];
513 extern const char iwl_ax200_name[];
514 extern const char iwl_ax203_name[];
515 extern const char iwl_ax204_name[];
516 extern const char iwl_ax201_name[];
517 extern const char iwl_ax101_name[];
518 extern const char iwl_ax200_killer_1650w_name[];
519 extern const char iwl_ax200_killer_1650x_name[];
520 extern const char iwl_ax201_killer_1650s_name[];
521 extern const char iwl_ax201_killer_1650i_name[];
522 extern const char iwl_ax210_killer_1675w_name[];
523 extern const char iwl_ax210_killer_1675x_name[];
524 extern const char iwl9560_killer_1550i_160_name[];
525 extern const char iwl9560_killer_1550s_160_name[];
526 extern const char iwl_ax211_killer_1675s_name[];
527 extern const char iwl_ax211_killer_1675i_name[];
528 extern const char iwl_ax411_killer_1690s_name[];
529 extern const char iwl_ax411_killer_1690i_name[];
530 extern const char iwl_ax211_name[];
531 extern const char iwl_ax221_name[];
532 extern const char iwl_ax231_name[];
533 extern const char iwl_ax411_name[];
534 extern const char iwl_bz_name[];
535 extern const char iwl_sc_name[];
536 #if IS_ENABLED(CONFIG_IWLDVM)
537 extern const struct iwl_cfg iwl5300_agn_cfg;
538 extern const struct iwl_cfg iwl5100_agn_cfg;
539 extern const struct iwl_cfg iwl5350_agn_cfg;
540 extern const struct iwl_cfg iwl5100_bgn_cfg;
541 extern const struct iwl_cfg iwl5100_abg_cfg;
542 extern const struct iwl_cfg iwl5150_agn_cfg;
543 extern const struct iwl_cfg iwl5150_abg_cfg;
544 extern const struct iwl_cfg iwl6005_2agn_cfg;
545 extern const struct iwl_cfg iwl6005_2abg_cfg;
546 extern const struct iwl_cfg iwl6005_2bg_cfg;
547 extern const struct iwl_cfg iwl6005_2agn_sff_cfg;
548 extern const struct iwl_cfg iwl6005_2agn_d_cfg;
549 extern const struct iwl_cfg iwl6005_2agn_mow1_cfg;
550 extern const struct iwl_cfg iwl6005_2agn_mow2_cfg;
551 extern const struct iwl_cfg iwl1030_bgn_cfg;
552 extern const struct iwl_cfg iwl1030_bg_cfg;
553 extern const struct iwl_cfg iwl6030_2agn_cfg;
554 extern const struct iwl_cfg iwl6030_2abg_cfg;
555 extern const struct iwl_cfg iwl6030_2bgn_cfg;
556 extern const struct iwl_cfg iwl6030_2bg_cfg;
557 extern const struct iwl_cfg iwl6000i_2agn_cfg;
558 extern const struct iwl_cfg iwl6000i_2abg_cfg;
559 extern const struct iwl_cfg iwl6000i_2bg_cfg;
560 extern const struct iwl_cfg iwl6000_3agn_cfg;
561 extern const struct iwl_cfg iwl6050_2agn_cfg;
562 extern const struct iwl_cfg iwl6050_2abg_cfg;
563 extern const struct iwl_cfg iwl6150_bgn_cfg;
564 extern const struct iwl_cfg iwl6150_bg_cfg;
565 extern const struct iwl_cfg iwl1000_bgn_cfg;
566 extern const struct iwl_cfg iwl1000_bg_cfg;
567 extern const struct iwl_cfg iwl100_bgn_cfg;
568 extern const struct iwl_cfg iwl100_bg_cfg;
569 extern const struct iwl_cfg iwl130_bgn_cfg;
570 extern const struct iwl_cfg iwl130_bg_cfg;
571 extern const struct iwl_cfg iwl2000_2bgn_cfg;
572 extern const struct iwl_cfg iwl2000_2bgn_d_cfg;
573 extern const struct iwl_cfg iwl2030_2bgn_cfg;
574 extern const struct iwl_cfg iwl6035_2agn_cfg;
575 extern const struct iwl_cfg iwl6035_2agn_sff_cfg;
576 extern const struct iwl_cfg iwl105_bgn_cfg;
577 extern const struct iwl_cfg iwl105_bgn_d_cfg;
578 extern const struct iwl_cfg iwl135_bgn_cfg;
579 #endif /* CONFIG_IWLDVM */
580 #if IS_ENABLED(CONFIG_IWLMVM)
581 extern const struct iwl_ht_params iwl_22000_ht_params;
582 extern const struct iwl_cfg iwl7260_2ac_cfg;
583 extern const struct iwl_cfg iwl7260_2ac_cfg_high_temp;
584 extern const struct iwl_cfg iwl7260_2n_cfg;
585 extern const struct iwl_cfg iwl7260_n_cfg;
586 extern const struct iwl_cfg iwl3160_2ac_cfg;
587 extern const struct iwl_cfg iwl3160_2n_cfg;
588 extern const struct iwl_cfg iwl3160_n_cfg;
589 extern const struct iwl_cfg iwl3165_2ac_cfg;
590 extern const struct iwl_cfg iwl3168_2ac_cfg;
591 extern const struct iwl_cfg iwl7265_2ac_cfg;
592 extern const struct iwl_cfg iwl7265_2n_cfg;
593 extern const struct iwl_cfg iwl7265_n_cfg;
594 extern const struct iwl_cfg iwl7265d_2ac_cfg;
595 extern const struct iwl_cfg iwl7265d_2n_cfg;
596 extern const struct iwl_cfg iwl7265d_n_cfg;
597 extern const struct iwl_cfg iwl8260_2n_cfg;
598 extern const struct iwl_cfg iwl8260_2ac_cfg;
599 extern const struct iwl_cfg iwl8265_2ac_cfg;
600 extern const struct iwl_cfg iwl8275_2ac_cfg;
601 extern const struct iwl_cfg iwl4165_2ac_cfg;
602 extern const struct iwl_cfg iwl9260_2ac_cfg;
603 extern const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg;
604 extern const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg;
605 extern const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg;
606 extern const struct iwl_cfg iwl9560_2ac_cfg_soc;
607 extern const struct iwl_cfg iwl_qu_b0_hr1_b0;
608 extern const struct iwl_cfg iwl_qu_c0_hr1_b0;
609 extern const struct iwl_cfg iwl_quz_a0_hr1_b0;
610 extern const struct iwl_cfg iwl_qu_b0_hr_b0;
611 extern const struct iwl_cfg iwl_qu_c0_hr_b0;
612 extern const struct iwl_cfg iwl_ax200_cfg_cc;
613 extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
614 extern const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0;
615 extern const struct iwl_cfg iwl_ax201_cfg_quz_hr;
616 extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr;
617 extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr;
618 extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0;
619 extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0;
620 extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0;
621 extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0;
622 extern const struct iwl_cfg killer1650x_2ax_cfg;
623 extern const struct iwl_cfg killer1650w_2ax_cfg;
624 extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0;
625 extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0;
626 extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long;
627 extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0;
628 extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0;
629 extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long;
630 
631 extern const struct iwl_cfg iwl_cfg_ma;
632 
633 extern const struct iwl_cfg iwl_cfg_so_a0_hr_a0;
634 extern const struct iwl_cfg iwl_cfg_so_a0_ms_a0;
635 extern const struct iwl_cfg iwl_cfg_quz_a0_hr_b0;
636 
637 extern const struct iwl_cfg iwl_cfg_bz;
638 extern const struct iwl_cfg iwl_cfg_gl;
639 
640 extern const struct iwl_cfg iwl_cfg_sc;
641 #endif /* CONFIG_IWLMVM */
642 
643 #endif /* __IWL_CONFIG_H__ */
644