1 /******************************************************************************
2  *
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * GPL LICENSE SUMMARY
7  *
8  * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
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10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of version 2 of the GNU General Public License as
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13  *
14  * This program is distributed in the hope that it will be useful, but
15  * WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17  * General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22  * USA
23  *
24  * The full GNU General Public License is included in this distribution
25  * in the file called LICENSE.GPL.
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27  * Contact Information:
28  *  Intel Linux Wireless <ilw@linux.intel.com>
29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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31  * BSD LICENSE
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33  * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
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62  *****************************************************************************/
63 /*
64  * Please use this file (iwl-agn-hw.h) only for hardware-related definitions.
65  */
66 
67 #ifndef __iwl_agn_hw_h__
68 #define __iwl_agn_hw_h__
69 
70 #define IWLAGN_RTC_INST_LOWER_BOUND		(0x000000)
71 #define IWLAGN_RTC_INST_UPPER_BOUND		(0x020000)
72 
73 #define IWLAGN_RTC_DATA_LOWER_BOUND		(0x800000)
74 #define IWLAGN_RTC_DATA_UPPER_BOUND		(0x80C000)
75 
76 #define IWLAGN_RTC_INST_SIZE (IWLAGN_RTC_INST_UPPER_BOUND - \
77 				IWLAGN_RTC_INST_LOWER_BOUND)
78 #define IWLAGN_RTC_DATA_SIZE (IWLAGN_RTC_DATA_UPPER_BOUND - \
79 				IWLAGN_RTC_DATA_LOWER_BOUND)
80 
81 /* RSSI to dBm */
82 #define IWLAGN_RSSI_OFFSET	44
83 
84 /* PCI registers */
85 #define PCI_CFG_RETRY_TIMEOUT	0x041
86 
87 /* PCI register values */
88 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01
89 #define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02
90 
91 #define IWLAGN_DEFAULT_TX_RETRY  15
92 
93 /* Limit range of txpower output target to be between these values */
94 #define IWLAGN_TX_POWER_TARGET_POWER_MIN	(0)	/* 0 dBm: 1 milliwatt */
95 #define IWLAGN_TX_POWER_TARGET_POWER_MAX	(16)	/* 16 dBm */
96 
97 /* EEPROM */
98 #define IWLAGN_EEPROM_IMG_SIZE		2048
99 
100 #define IWLAGN_CMD_FIFO_NUM		7
101 #define IWLAGN_NUM_QUEUES		20
102 #define IWLAGN_NUM_AMPDU_QUEUES		10
103 #define IWLAGN_FIRST_AMPDU_QUEUE	10
104 
105 /* Fixed (non-configurable) rx data from phy */
106 
107 /**
108  * struct iwlagn_schedq_bc_tbl scheduler byte count table
109  *	base physical address provided by SCD_DRAM_BASE_ADDR
110  * @tfd_offset  0-12 - tx command byte count
111  *	       12-16 - station index
112  */
113 struct iwlagn_scd_bc_tbl {
114 	__le16 tfd_offset[TFD_QUEUE_BC_SIZE];
115 } __packed;
116 
117 
118 #endif /* __iwl_agn_hw_h__ */
119