1 /* 2 -------------------------------------------------------------------- 3 i2c-ite.h: Global defines for the I2C controller on board the 4 ITE MIPS processor. 5 -------------------------------------------------------------------- 6 Hai-Pao Fan, MontaVista Software, Inc. 7 hpfan@mvista.com or source@mvista.com 8 9 Copyright 2001 MontaVista Software Inc. 10 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 31 */ 32 33 #ifndef I2C_ITE_H 34 #define I2C_ITE_H 1 35 36 #include <asm/it8172/it8172.h> 37 38 /* I2C Registers */ 39 #define ITE_I2CHCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x30 40 #define ITE_I2CHSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x34 41 #define ITE_I2CSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x38 42 #define ITE_I2CSSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x3c 43 #define ITE_I2CCKCNT IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x48 44 #define ITE_I2CSHDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x4c 45 #define ITE_I2CRSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x50 46 #define ITE_I2CPSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x54 47 48 #define ITE_I2CFDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x70 49 #define ITE_I2CFBCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x74 50 #define ITE_I2CFCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x78 51 #define ITE_I2CFSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x7c 52 53 54 /* Host Control Register ITE_I2CHCR */ 55 #define ITE_I2CHCR_HCE 0x01 /* Enable I2C Host Controller */ 56 #define ITE_I2CHCR_IE 0x02 /* Enable the interrupt after completing 57 the current transaction */ 58 #define ITE_I2CHCR_CP_W 0x00 /* bit2-4 000 - Write */ 59 #define ITE_I2CHCR_CP_R 0x08 /* 010 - Current address read */ 60 #define ITE_I2CHCR_CP_S 0x10 /* 100 - Sequential read */ 61 #define ITE_I2CHCR_ST 0x20 /* Initiates the I2C host controller to execute 62 the command and send the data programmed in 63 all required registers to I2C bus */ 64 #define ITE_CMD ITE_I2CHCR_HCE | ITE_I2CHCR_IE | ITE_I2CHCR_ST 65 #define ITE_WRITE ITE_CMD | ITE_I2CHCR_CP_W 66 #define ITE_READ ITE_CMD | ITE_I2CHCR_CP_R 67 #define ITE_SREAD ITE_CMD | ITE_I2CHCR_CP_S 68 69 /* Host Status Register ITE_I2CHSR */ 70 #define ITE_I2CHSR_DB 0x01 /* Device is busy, receives NACK response except 71 in the first and last bytes */ 72 #define ITE_I2CHSR_DNE 0x02 /* Target address on I2C bus does not exist */ 73 #define ITE_I2CHSR_TDI 0x04 /* R/W Transaction on I2C bus was completed */ 74 #define ITE_I2CHSR_HB 0x08 /* Host controller is processing transactions */ 75 #define ITE_I2CHSR_FER 0x10 /* Error occurs in the FIFO */ 76 77 /* Slave Address Register ITE_I2CSAR */ 78 #define ITE_I2CSAR_SA_MASK 0xfe /* Target I2C device address */ 79 #define ITE_I2CSAR_ASO 0x0100 /* Output 1/0 to I2CAS port when the 80 next slave address is addressed */ 81 82 /* Slave Sub-address Register ITE_I2CSSAR */ 83 #define ITE_I2CSSAR_SUBA_MASK 0xff /* Target I2C device sub-address */ 84 85 /* Clock Counter Register ITE_I2CCKCNT */ 86 #define ITE_I2CCKCNT_STOP 0x00 /* stop I2C clock */ 87 #define ITE_I2CCKCNT_HPCC_MASK 0x7f /* SCL high period counter */ 88 #define ITE_I2CCKCNT_LPCC_MASK 0x7f00 /* SCL low period counter */ 89 90 /* START Hold Time Register ITE_I2CSHDR */ 91 /* value is counted based on 16 MHz internal clock */ 92 #define ITE_I2CSHDR_FM 0x0a /* START condition at fast mode */ 93 #define ITE_I2CSHDR_SM 0x47 /* START contition at standard mode */ 94 95 /* (Repeated) START Setup Time Register ITE_I2CRSUR */ 96 /* value is counted based on 16 MHz internal clock */ 97 #define ITE_I2CRSUR_FM 0x0a /* repeated START condition at fast mode */ 98 #define ITE_I2CRSUR_SM 0x50 /* repeated START condition at standard mode */ 99 100 /* STOP setup Time Register ITE_I2CPSUR */ 101 102 /* FIFO Data Register ITE_I2CFDR */ 103 #define ITE_I2CFDR_MASK 0xff 104 105 /* FIFO Byte Count Register ITE_I2CFBCR */ 106 #define ITE_I2CFBCR_MASK 0x3f 107 108 /* FIFO Control Register ITE_I2CFCR */ 109 #define ITE_I2CFCR_FLUSH 0x01 /* Flush FIFO and reset the FIFO point 110 and I2CFSR */ 111 /* FIFO Status Register ITE_I2CFSR */ 112 #define ITE_I2CFSR_FO 0x01 /* FIFO is overrun when write */ 113 #define ITE_I2CFSR_FU 0x02 /* FIFO is underrun when read */ 114 #define ITE_I2CFSR_FF 0x04 /* FIFO is full when write */ 115 #define ITE_I2CFSR_FE 0x08 /* FIFO is empty when read */ 116 117 #endif /* I2C_ITE_H */ 118