1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 /* Version */ 17 #define RTL_VERSION 18 19 /* instruction pipeline depth */ 20 #define ISP_BRANCHDELAY 5 21 22 /* bus */ 23 #define ISP_BUS_WIDTH 32 24 #define ISP_BUS_ADDR_WIDTH 32 25 #define ISP_BUS_BURST_SIZE 1 26 27 /* data-path */ 28 #define ISP_SCALAR_WIDTH 32 29 #define ISP_SLICE_NELEMS 4 30 #define ISP_VEC_NELEMS 64 31 #define ISP_VEC_ELEMBITS 14 32 #define ISP_VEC_ELEM8BITS 16 33 #define ISP_CLONE_DATAPATH_IS_16 1 34 35 /* memories */ 36 #define ISP_DMEM_DEPTH 4096 37 #define ISP_DMEM_BSEL_DOWNSAMPLE 8 38 #define ISP_VMEM_DEPTH 3072 39 #define ISP_VMEM_BSEL_DOWNSAMPLE 8 40 #define ISP_VMEM_ELEMBITS 14 41 #define ISP_VMEM_ELEM_PRECISION 14 42 #define ISP_PMEM_DEPTH 2048 43 #define ISP_PMEM_WIDTH 640 44 #define ISP_VAMEM_ADDRESS_BITS 12 45 #define ISP_VAMEM_ELEMBITS 12 46 #define ISP_VAMEM_DEPTH 2048 47 #define ISP_VAMEM_ALIGNMENT 2 48 #define ISP_VA_ADDRESS_WIDTH 896 49 #define ISP_VEC_VALSU_LATENCY ISP_VEC_NELEMS 50 #define ISP_HIST_ADDRESS_BITS 12 51 #define ISP_HIST_ALIGNMENT 4 52 #define ISP_HIST_COMP_IN_PREC 12 53 #define ISP_HIST_DEPTH 1024 54 #define ISP_HIST_WIDTH 24 55 #define ISP_HIST_COMPONENTS 4 56 57 /* program counter */ 58 #define ISP_PC_WIDTH 13 59 60 /* Template switches */ 61 #define ISP_SHIELD_INPUT_DMEM 0 62 #define ISP_SHIELD_OUTPUT_DMEM 1 63 #define ISP_SHIELD_INPUT_VMEM 0 64 #define ISP_SHIELD_OUTPUT_VMEM 0 65 #define ISP_SHIELD_INPUT_PMEM 1 66 #define ISP_SHIELD_OUTPUT_PMEM 1 67 #define ISP_SHIELD_INPUT_HIST 1 68 #define ISP_SHIELD_OUTPUT_HIST 1 69 /* When LUT is select the shielding is always on */ 70 #define ISP_SHIELD_INPUT_VAMEM 1 71 #define ISP_SHIELD_OUTPUT_VAMEM 1 72 73 #define ISP_HAS_IRQ 1 74 #define ISP_HAS_SOFT_RESET 1 75 #define ISP_HAS_VEC_DIV 0 76 #define ISP_HAS_VFU_W_2O 1 77 #define ISP_HAS_DEINT3 1 78 #define ISP_HAS_LUT 1 79 #define ISP_HAS_HIST 1 80 #define ISP_HAS_VALSU 1 81 #define ISP_HAS_3rdVALSU 1 82 #define ISP_VRF1_HAS_2P 1 83 84 #define ISP_SRU_GUARDING 1 85 #define ISP_VLSU_GUARDING 1 86 87 #define ISP_VRF_RAM 1 88 #define ISP_SRF_RAM 1 89 90 #define ISP_SPLIT_VMUL_VADD_IS 0 91 #define ISP_RFSPLIT_FPGA 0 92 93 /* RSN or Bus pipelining */ 94 #define ISP_RSN_PIPE 1 95 #define ISP_VSF_BUS_PIPE 0 96 97 /* extra slave port to vmem */ 98 #define ISP_IF_VMEM 0 99 #define ISP_GDC_VMEM 0 100 101 /* Streaming ports */ 102 #define ISP_IF 1 103 #define ISP_IF_B 1 104 #define ISP_GDC 1 105 #define ISP_SCL 1 106 #define ISP_GPFIFO 1 107 #define ISP_SP 1 108 109 /* Removing Issue Slot(s) */ 110 #define ISP_HAS_NOT_SIMD_IS2 0 111 #define ISP_HAS_NOT_SIMD_IS3 0 112 #define ISP_HAS_NOT_SIMD_IS4 0 113 #define ISP_HAS_NOT_SIMD_IS4_VADD 0 114 #define ISP_HAS_NOT_SIMD_IS5 0 115 #define ISP_HAS_NOT_SIMD_IS6 0 116 #define ISP_HAS_NOT_SIMD_IS7 0 117 #define ISP_HAS_NOT_SIMD_IS8 0 118 119 /* ICache */ 120 #define ISP_ICACHE 1 121 #define ISP_ICACHE_ONLY 0 122 #define ISP_ICACHE_PREFETCH 1 123 #define ISP_ICACHE_INDEX_BITS 8 124 #define ISP_ICACHE_SET_BITS 5 125 #define ISP_ICACHE_BLOCKS_PER_SET_BITS 1 126 127 /* Experimental Flags */ 128 #define ISP_EXP_1 0 129 #define ISP_EXP_2 0 130 #define ISP_EXP_3 0 131 #define ISP_EXP_4 0 132 #define ISP_EXP_5 0 133 #define ISP_EXP_6 0 134 135 /* Derived values */ 136 #define ISP_LOG2_PMEM_WIDTH 10 137 #define ISP_VEC_WIDTH 896 138 #define ISP_SLICE_WIDTH 56 139 #define ISP_VMEM_WIDTH 896 140 #define ISP_VMEM_ALIGN 128 141 #define ISP_SIMDLSU 1 142 #define ISP_LSU_IMM_BITS 12 143 144 /* convenient shortcuts for software*/ 145 #define ISP_NWAY ISP_VEC_NELEMS 146 #define NBITS ISP_VEC_ELEMBITS 147 148 #define _isp_ceil_div(a, b) (((a) + (b) - 1) / (b)) 149 150 #define ISP_VEC_ALIGN ISP_VMEM_ALIGN 151 152 /* register file sizes */ 153 #define ISP_RF0_SIZE 64 154 #define ISP_RF1_SIZE 16 155 #define ISP_RF2_SIZE 64 156 #define ISP_RF3_SIZE 4 157 #define ISP_RF4_SIZE 64 158 #define ISP_RF5_SIZE 16 159 #define ISP_RF6_SIZE 16 160 #define ISP_RF7_SIZE 16 161 #define ISP_RF8_SIZE 16 162 #define ISP_RF9_SIZE 16 163 #define ISP_RF10_SIZE 16 164 #define ISP_RF11_SIZE 16 165 166 #define ISP_SRF1_SIZE 4 167 #define ISP_SRF2_SIZE 64 168 #define ISP_SRF3_SIZE 64 169 #define ISP_SRF4_SIZE 32 170 #define ISP_SRF5_SIZE 64 171 #define ISP_FRF0_SIZE 16 172 #define ISP_FRF1_SIZE 4 173 #define ISP_FRF2_SIZE 16 174 #define ISP_FRF3_SIZE 4 175 #define ISP_FRF4_SIZE 4 176 #define ISP_FRF5_SIZE 8 177 #define ISP_FRF6_SIZE 4 178 /* register file read latency */ 179 #define ISP_VRF1_READ_LAT 1 180 #define ISP_VRF2_READ_LAT 1 181 #define ISP_VRF3_READ_LAT 1 182 #define ISP_VRF4_READ_LAT 1 183 #define ISP_VRF5_READ_LAT 1 184 #define ISP_VRF6_READ_LAT 1 185 #define ISP_VRF7_READ_LAT 1 186 #define ISP_VRF8_READ_LAT 1 187 #define ISP_SRF1_READ_LAT 1 188 #define ISP_SRF2_READ_LAT 1 189 #define ISP_SRF3_READ_LAT 1 190 #define ISP_SRF4_READ_LAT 1 191 #define ISP_SRF5_READ_LAT 1 192 #define ISP_SRF5_READ_LAT 1 193 /* immediate sizes */ 194 #define ISP_IS1_IMM_BITS 14 195 #define ISP_IS2_IMM_BITS 13 196 #define ISP_IS3_IMM_BITS 14 197 #define ISP_IS4_IMM_BITS 14 198 #define ISP_IS5_IMM_BITS 9 199 #define ISP_IS6_IMM_BITS 16 200 #define ISP_IS7_IMM_BITS 9 201 #define ISP_IS8_IMM_BITS 16 202 #define ISP_IS9_IMM_BITS 11 203 /* fifo depths */ 204 #define ISP_IF_FIFO_DEPTH 0 205 #define ISP_IF_B_FIFO_DEPTH 0 206 #define ISP_DMA_FIFO_DEPTH 0 207 #define ISP_OF_FIFO_DEPTH 0 208 #define ISP_GDC_FIFO_DEPTH 0 209 #define ISP_SCL_FIFO_DEPTH 0 210 #define ISP_GPFIFO_FIFO_DEPTH 0 211 #define ISP_SP_FIFO_DEPTH 0 212