1 /* 2 * ispreg.h 3 * 4 * TI OMAP3 ISP - Registers definitions 5 * 6 * Copyright (C) 2010 Nokia Corporation 7 * Copyright (C) 2009 Texas Instruments, Inc 8 * 9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 * Sakari Ailus <sakari.ailus@iki.fi> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 24 * 02110-1301 USA 25 */ 26 27 #ifndef OMAP3_ISP_REG_H 28 #define OMAP3_ISP_REG_H 29 30 #include <plat/omap34xx.h> 31 32 33 #define CM_CAM_MCLK_HZ 172800000 /* Hz */ 34 35 /* ISP Submodules offset */ 36 37 #define OMAP3ISP_REG_BASE OMAP3430_ISP_BASE 38 #define OMAP3ISP_REG(offset) (OMAP3ISP_REG_BASE + (offset)) 39 40 #define OMAP3ISP_CCP2_REG_OFFSET 0x0400 41 #define OMAP3ISP_CCP2_REG_BASE (OMAP3ISP_REG_BASE + \ 42 OMAP3ISP_CCP2_REG_OFFSET) 43 #define OMAP3ISP_CCP2_REG(offset) (OMAP3ISP_CCP2_REG_BASE + (offset)) 44 45 #define OMAP3ISP_CCDC_REG_OFFSET 0x0600 46 #define OMAP3ISP_CCDC_REG_BASE (OMAP3ISP_REG_BASE + \ 47 OMAP3ISP_CCDC_REG_OFFSET) 48 #define OMAP3ISP_CCDC_REG(offset) (OMAP3ISP_CCDC_REG_BASE + (offset)) 49 50 #define OMAP3ISP_HIST_REG_OFFSET 0x0A00 51 #define OMAP3ISP_HIST_REG_BASE (OMAP3ISP_REG_BASE + \ 52 OMAP3ISP_HIST_REG_OFFSET) 53 #define OMAP3ISP_HIST_REG(offset) (OMAP3ISP_HIST_REG_BASE + (offset)) 54 55 #define OMAP3ISP_H3A_REG_OFFSET 0x0C00 56 #define OMAP3ISP_H3A_REG_BASE (OMAP3ISP_REG_BASE + \ 57 OMAP3ISP_H3A_REG_OFFSET) 58 #define OMAP3ISP_H3A_REG(offset) (OMAP3ISP_H3A_REG_BASE + (offset)) 59 60 #define OMAP3ISP_PREV_REG_OFFSET 0x0E00 61 #define OMAP3ISP_PREV_REG_BASE (OMAP3ISP_REG_BASE + \ 62 OMAP3ISP_PREV_REG_OFFSET) 63 #define OMAP3ISP_PREV_REG(offset) (OMAP3ISP_PREV_REG_BASE + (offset)) 64 65 #define OMAP3ISP_RESZ_REG_OFFSET 0x1000 66 #define OMAP3ISP_RESZ_REG_BASE (OMAP3ISP_REG_BASE + \ 67 OMAP3ISP_RESZ_REG_OFFSET) 68 #define OMAP3ISP_RESZ_REG(offset) (OMAP3ISP_RESZ_REG_BASE + (offset)) 69 70 #define OMAP3ISP_SBL_REG_OFFSET 0x1200 71 #define OMAP3ISP_SBL_REG_BASE (OMAP3ISP_REG_BASE + \ 72 OMAP3ISP_SBL_REG_OFFSET) 73 #define OMAP3ISP_SBL_REG(offset) (OMAP3ISP_SBL_REG_BASE + (offset)) 74 75 #define OMAP3ISP_CSI2A_REGS1_REG_OFFSET 0x1800 76 #define OMAP3ISP_CSI2A_REGS1_REG_BASE (OMAP3ISP_REG_BASE + \ 77 OMAP3ISP_CSI2A_REGS1_REG_OFFSET) 78 #define OMAP3ISP_CSI2A_REGS1_REG(offset) \ 79 (OMAP3ISP_CSI2A_REGS1_REG_BASE + (offset)) 80 81 #define OMAP3ISP_CSIPHY2_REG_OFFSET 0x1970 82 #define OMAP3ISP_CSIPHY2_REG_BASE (OMAP3ISP_REG_BASE + \ 83 OMAP3ISP_CSIPHY2_REG_OFFSET) 84 #define OMAP3ISP_CSIPHY2_REG(offset) (OMAP3ISP_CSIPHY2_REG_BASE + (offset)) 85 86 #define OMAP3ISP_CSI2A_REGS2_REG_OFFSET 0x19C0 87 #define OMAP3ISP_CSI2A_REGS2_REG_BASE (OMAP3ISP_REG_BASE + \ 88 OMAP3ISP_CSI2A_REGS2_REG_OFFSET) 89 #define OMAP3ISP_CSI2A_REGS2_REG(offset) \ 90 (OMAP3ISP_CSI2A_REGS2_REG_BASE + (offset)) 91 92 #define OMAP3ISP_CSI2C_REGS1_REG_OFFSET 0x1C00 93 #define OMAP3ISP_CSI2C_REGS1_REG_BASE (OMAP3ISP_REG_BASE + \ 94 OMAP3ISP_CSI2C_REGS1_REG_OFFSET) 95 #define OMAP3ISP_CSI2C_REGS1_REG(offset) \ 96 (OMAP3ISP_CSI2C_REGS1_REG_BASE + (offset)) 97 98 #define OMAP3ISP_CSIPHY1_REG_OFFSET 0x1D70 99 #define OMAP3ISP_CSIPHY1_REG_BASE (OMAP3ISP_REG_BASE + \ 100 OMAP3ISP_CSIPHY1_REG_OFFSET) 101 #define OMAP3ISP_CSIPHY1_REG(offset) (OMAP3ISP_CSIPHY1_REG_BASE + (offset)) 102 103 #define OMAP3ISP_CSI2C_REGS2_REG_OFFSET 0x1DC0 104 #define OMAP3ISP_CSI2C_REGS2_REG_BASE (OMAP3ISP_REG_BASE + \ 105 OMAP3ISP_CSI2C_REGS2_REG_OFFSET) 106 #define OMAP3ISP_CSI2C_REGS2_REG(offset) \ 107 (OMAP3ISP_CSI2C_REGS2_REG_BASE + (offset)) 108 109 /* ISP module register offset */ 110 111 #define ISP_REVISION (0x000) 112 #define ISP_SYSCONFIG (0x004) 113 #define ISP_SYSSTATUS (0x008) 114 #define ISP_IRQ0ENABLE (0x00C) 115 #define ISP_IRQ0STATUS (0x010) 116 #define ISP_IRQ1ENABLE (0x014) 117 #define ISP_IRQ1STATUS (0x018) 118 #define ISP_TCTRL_GRESET_LENGTH (0x030) 119 #define ISP_TCTRL_PSTRB_REPLAY (0x034) 120 #define ISP_CTRL (0x040) 121 #define ISP_SECURE (0x044) 122 #define ISP_TCTRL_CTRL (0x050) 123 #define ISP_TCTRL_FRAME (0x054) 124 #define ISP_TCTRL_PSTRB_DELAY (0x058) 125 #define ISP_TCTRL_STRB_DELAY (0x05C) 126 #define ISP_TCTRL_SHUT_DELAY (0x060) 127 #define ISP_TCTRL_PSTRB_LENGTH (0x064) 128 #define ISP_TCTRL_STRB_LENGTH (0x068) 129 #define ISP_TCTRL_SHUT_LENGTH (0x06C) 130 #define ISP_PING_PONG_ADDR (0x070) 131 #define ISP_PING_PONG_MEM_RANGE (0x074) 132 #define ISP_PING_PONG_BUF_SIZE (0x078) 133 134 /* CCP2 receiver registers */ 135 136 #define ISPCCP2_REVISION (0x000) 137 #define ISPCCP2_SYSCONFIG (0x004) 138 #define ISPCCP2_SYSCONFIG_SOFT_RESET (1 << 1) 139 #define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1 140 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12 141 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \ 142 (0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT) 143 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO \ 144 (0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT) 145 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \ 146 (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT) 147 #define ISPCCP2_SYSSTATUS (0x008) 148 #define ISPCCP2_SYSSTATUS_RESET_DONE (1 << 0) 149 #define ISPCCP2_LC01_IRQENABLE (0x00C) 150 #define ISPCCP2_LC01_IRQSTATUS (0x010) 151 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ (1 << 11) 152 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ (1 << 10) 153 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ (1 << 9) 154 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ (1 << 8) 155 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ (1 << 7) 156 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ (1 << 5) 157 #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ (1 << 4) 158 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ (1 << 3) 159 #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ (1 << 2) 160 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ (1 << 1) 161 #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ (1 << 0) 162 163 #define ISPCCP2_LC23_IRQENABLE (0x014) 164 #define ISPCCP2_LC23_IRQSTATUS (0x018) 165 #define ISPCCP2_LCM_IRQENABLE (0x02C) 166 #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ (1 << 0) 167 #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ (1 << 1) 168 #define ISPCCP2_LCM_IRQSTATUS (0x030) 169 #define ISPCCP2_CTRL (0x040) 170 #define ISPCCP2_CTRL_IF_EN (1 << 0) 171 #define ISPCCP2_CTRL_PHY_SEL (1 << 1) 172 #define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1) 173 #define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1) 174 #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1 175 #define ISPCCP2_CTRL_PHY_SEL_SHIFT 1 176 #define ISPCCP2_CTRL_IO_OUT_SEL (1 << 2) 177 #define ISPCCP2_CTRL_MODE (1 << 4) 178 #define ISPCCP2_CTRL_VP_CLK_FORCE_ON (1 << 9) 179 #define ISPCCP2_CTRL_INV (1 << 10) 180 #define ISPCCP2_CTRL_INV_MASK 0x1 181 #define ISPCCP2_CTRL_INV_SHIFT 10 182 #define ISPCCP2_CTRL_VP_ONLY_EN (1 << 11) 183 #define ISPCCP2_CTRL_VP_CLK_POL (1 << 12) 184 #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15 185 #define ISPCCP2_CTRL_VPCLK_DIV_MASK 0x1ffff /* [31:15] */ 186 #define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT 8 /* 3430 bits */ 187 #define ISPCCP2_CTRL_VP_OUT_CTRL_MASK 0x3 /* 3430 bits */ 188 #define ISPCCP2_DBG (0x044) 189 #define ISPCCP2_GNQ (0x048) 190 #define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x)) 191 #define ISPCCP2_LCx_CTRL_CHAN_EN (1 << 0) 192 #define ISPCCP2_LCx_CTRL_CRC_EN (1 << 19) 193 #define ISPCCP2_LCx_CTRL_CRC_MASK 0x1 194 #define ISPCCP2_LCx_CTRL_CRC_SHIFT 2 195 #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 19 196 #define ISPCCP2_LCx_CTRL_REGION_EN (1 << 1) 197 #define ISPCCP2_LCx_CTRL_REGION_MASK 0x1 198 #define ISPCCP2_LCx_CTRL_REGION_SHIFT 1 199 #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f 200 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0 0x2 201 #define ISPCCP2_LCx_CTRL_FORMAT_MASK 0x1f 202 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT 0x3 203 #define ISPCCP2_LCx_CODE(x) ((0x054)+0x30*(x)) 204 #define ISPCCP2_LCx_STAT_START(x) ((0x058)+0x30*(x)) 205 #define ISPCCP2_LCx_STAT_SIZE(x) ((0x05C)+0x30*(x)) 206 #define ISPCCP2_LCx_SOF_ADDR(x) ((0x060)+0x30*(x)) 207 #define ISPCCP2_LCx_EOF_ADDR(x) ((0x064)+0x30*(x)) 208 #define ISPCCP2_LCx_DAT_START(x) ((0x068)+0x30*(x)) 209 #define ISPCCP2_LCx_DAT_SIZE(x) ((0x06C)+0x30*(x)) 210 #define ISPCCP2_LCx_DAT_MASK 0xFFF 211 #define ISPCCP2_LCx_DAT_SHIFT 16 212 #define ISPCCP2_LCx_DAT_PING_ADDR(x) ((0x070)+0x30*(x)) 213 #define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x)) 214 #define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x)) 215 #define ISPCCP2_LCM_CTRL (0x1D0) 216 #define ISPCCP2_LCM_CTRL_CHAN_EN (1 << 0) 217 #define ISPCCP2_LCM_CTRL_DST_PORT (1 << 2) 218 #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT 2 219 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT 3 220 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11 221 #define ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT 5 222 #define ISPCCP2_LCM_CTRL_BURST_SIZE_MASK 0x7 223 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT 16 224 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7 225 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT 20 226 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3 227 #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED (1 << 22) 228 #define ISPCCP2_LCM_CTRL_SRC_PACK (1 << 23) 229 #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT 24 230 #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7 231 #define ISPCCP2_LCM_VSIZE (0x1D4) 232 #define ISPCCP2_LCM_VSIZE_SHIFT 16 233 #define ISPCCP2_LCM_HSIZE (0x1D8) 234 #define ISPCCP2_LCM_HSIZE_SHIFT 16 235 #define ISPCCP2_LCM_PREFETCH (0x1DC) 236 #define ISPCCP2_LCM_PREFETCH_SHIFT 3 237 #define ISPCCP2_LCM_SRC_ADDR (0x1E0) 238 #define ISPCCP2_LCM_SRC_OFST (0x1E4) 239 #define ISPCCP2_LCM_DST_ADDR (0x1E8) 240 #define ISPCCP2_LCM_DST_OFST (0x1EC) 241 242 /* CCDC module register offset */ 243 244 #define ISPCCDC_PID (0x000) 245 #define ISPCCDC_PCR (0x004) 246 #define ISPCCDC_SYN_MODE (0x008) 247 #define ISPCCDC_HD_VD_WID (0x00C) 248 #define ISPCCDC_PIX_LINES (0x010) 249 #define ISPCCDC_HORZ_INFO (0x014) 250 #define ISPCCDC_VERT_START (0x018) 251 #define ISPCCDC_VERT_LINES (0x01C) 252 #define ISPCCDC_CULLING (0x020) 253 #define ISPCCDC_HSIZE_OFF (0x024) 254 #define ISPCCDC_SDOFST (0x028) 255 #define ISPCCDC_SDR_ADDR (0x02C) 256 #define ISPCCDC_CLAMP (0x030) 257 #define ISPCCDC_DCSUB (0x034) 258 #define ISPCCDC_COLPTN (0x038) 259 #define ISPCCDC_BLKCMP (0x03C) 260 #define ISPCCDC_FPC (0x040) 261 #define ISPCCDC_FPC_ADDR (0x044) 262 #define ISPCCDC_VDINT (0x048) 263 #define ISPCCDC_ALAW (0x04C) 264 #define ISPCCDC_REC656IF (0x050) 265 #define ISPCCDC_CFG (0x054) 266 #define ISPCCDC_FMTCFG (0x058) 267 #define ISPCCDC_FMT_HORZ (0x05C) 268 #define ISPCCDC_FMT_VERT (0x060) 269 #define ISPCCDC_FMT_ADDR0 (0x064) 270 #define ISPCCDC_FMT_ADDR1 (0x068) 271 #define ISPCCDC_FMT_ADDR2 (0x06C) 272 #define ISPCCDC_FMT_ADDR3 (0x070) 273 #define ISPCCDC_FMT_ADDR4 (0x074) 274 #define ISPCCDC_FMT_ADDR5 (0x078) 275 #define ISPCCDC_FMT_ADDR6 (0x07C) 276 #define ISPCCDC_FMT_ADDR7 (0x080) 277 #define ISPCCDC_PRGEVEN0 (0x084) 278 #define ISPCCDC_PRGEVEN1 (0x088) 279 #define ISPCCDC_PRGODD0 (0x08C) 280 #define ISPCCDC_PRGODD1 (0x090) 281 #define ISPCCDC_VP_OUT (0x094) 282 283 #define ISPCCDC_LSC_CONFIG (0x098) 284 #define ISPCCDC_LSC_INITIAL (0x09C) 285 #define ISPCCDC_LSC_TABLE_BASE (0x0A0) 286 #define ISPCCDC_LSC_TABLE_OFFSET (0x0A4) 287 288 /* SBL */ 289 #define ISPSBL_PCR 0x4 290 #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF (1 << 16) 291 #define ISPSBL_PCR_H3A_AF_WBL_OVF (1 << 17) 292 #define ISPSBL_PCR_RSZ4_WBL_OVF (1 << 18) 293 #define ISPSBL_PCR_RSZ3_WBL_OVF (1 << 19) 294 #define ISPSBL_PCR_RSZ2_WBL_OVF (1 << 20) 295 #define ISPSBL_PCR_RSZ1_WBL_OVF (1 << 21) 296 #define ISPSBL_PCR_PRV_WBL_OVF (1 << 22) 297 #define ISPSBL_PCR_CCDC_WBL_OVF (1 << 23) 298 #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF (1 << 24) 299 #define ISPSBL_PCR_CSIA_WBL_OVF (1 << 25) 300 #define ISPSBL_PCR_CSIB_WBL_OVF (1 << 26) 301 #define ISPSBL_CCDC_WR_0 (0x028) 302 #define ISPSBL_CCDC_WR_0_DATA_READY (1 << 21) 303 #define ISPSBL_CCDC_WR_1 (0x02C) 304 #define ISPSBL_CCDC_WR_2 (0x030) 305 #define ISPSBL_CCDC_WR_3 (0x034) 306 307 #define ISPSBL_SDR_REQ_EXP 0xF8 308 #define ISPSBL_SDR_REQ_HIST_EXP_SHIFT 0 309 #define ISPSBL_SDR_REQ_HIST_EXP_MASK (0x3FF) 310 #define ISPSBL_SDR_REQ_RSZ_EXP_SHIFT 10 311 #define ISPSBL_SDR_REQ_RSZ_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_RSZ_EXP_SHIFT) 312 #define ISPSBL_SDR_REQ_PRV_EXP_SHIFT 20 313 #define ISPSBL_SDR_REQ_PRV_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_PRV_EXP_SHIFT) 314 315 /* Histogram registers */ 316 #define ISPHIST_PID (0x000) 317 #define ISPHIST_PCR (0x004) 318 #define ISPHIST_CNT (0x008) 319 #define ISPHIST_WB_GAIN (0x00C) 320 #define ISPHIST_R0_HORZ (0x010) 321 #define ISPHIST_R0_VERT (0x014) 322 #define ISPHIST_R1_HORZ (0x018) 323 #define ISPHIST_R1_VERT (0x01C) 324 #define ISPHIST_R2_HORZ (0x020) 325 #define ISPHIST_R2_VERT (0x024) 326 #define ISPHIST_R3_HORZ (0x028) 327 #define ISPHIST_R3_VERT (0x02C) 328 #define ISPHIST_ADDR (0x030) 329 #define ISPHIST_DATA (0x034) 330 #define ISPHIST_RADD (0x038) 331 #define ISPHIST_RADD_OFF (0x03C) 332 #define ISPHIST_H_V_INFO (0x040) 333 334 /* H3A module registers */ 335 #define ISPH3A_PID (0x000) 336 #define ISPH3A_PCR (0x004) 337 #define ISPH3A_AEWWIN1 (0x04C) 338 #define ISPH3A_AEWINSTART (0x050) 339 #define ISPH3A_AEWINBLK (0x054) 340 #define ISPH3A_AEWSUBWIN (0x058) 341 #define ISPH3A_AEWBUFST (0x05C) 342 #define ISPH3A_AFPAX1 (0x008) 343 #define ISPH3A_AFPAX2 (0x00C) 344 #define ISPH3A_AFPAXSTART (0x010) 345 #define ISPH3A_AFIIRSH (0x014) 346 #define ISPH3A_AFBUFST (0x018) 347 #define ISPH3A_AFCOEF010 (0x01C) 348 #define ISPH3A_AFCOEF032 (0x020) 349 #define ISPH3A_AFCOEF054 (0x024) 350 #define ISPH3A_AFCOEF076 (0x028) 351 #define ISPH3A_AFCOEF098 (0x02C) 352 #define ISPH3A_AFCOEF0010 (0x030) 353 #define ISPH3A_AFCOEF110 (0x034) 354 #define ISPH3A_AFCOEF132 (0x038) 355 #define ISPH3A_AFCOEF154 (0x03C) 356 #define ISPH3A_AFCOEF176 (0x040) 357 #define ISPH3A_AFCOEF198 (0x044) 358 #define ISPH3A_AFCOEF1010 (0x048) 359 360 #define ISPPRV_PCR (0x004) 361 #define ISPPRV_HORZ_INFO (0x008) 362 #define ISPPRV_VERT_INFO (0x00C) 363 #define ISPPRV_RSDR_ADDR (0x010) 364 #define ISPPRV_RADR_OFFSET (0x014) 365 #define ISPPRV_DSDR_ADDR (0x018) 366 #define ISPPRV_DRKF_OFFSET (0x01C) 367 #define ISPPRV_WSDR_ADDR (0x020) 368 #define ISPPRV_WADD_OFFSET (0x024) 369 #define ISPPRV_AVE (0x028) 370 #define ISPPRV_HMED (0x02C) 371 #define ISPPRV_NF (0x030) 372 #define ISPPRV_WB_DGAIN (0x034) 373 #define ISPPRV_WBGAIN (0x038) 374 #define ISPPRV_WBSEL (0x03C) 375 #define ISPPRV_CFA (0x040) 376 #define ISPPRV_BLKADJOFF (0x044) 377 #define ISPPRV_RGB_MAT1 (0x048) 378 #define ISPPRV_RGB_MAT2 (0x04C) 379 #define ISPPRV_RGB_MAT3 (0x050) 380 #define ISPPRV_RGB_MAT4 (0x054) 381 #define ISPPRV_RGB_MAT5 (0x058) 382 #define ISPPRV_RGB_OFF1 (0x05C) 383 #define ISPPRV_RGB_OFF2 (0x060) 384 #define ISPPRV_CSC0 (0x064) 385 #define ISPPRV_CSC1 (0x068) 386 #define ISPPRV_CSC2 (0x06C) 387 #define ISPPRV_CSC_OFFSET (0x070) 388 #define ISPPRV_CNT_BRT (0x074) 389 #define ISPPRV_CSUP (0x078) 390 #define ISPPRV_SETUP_YC (0x07C) 391 #define ISPPRV_SET_TBL_ADDR (0x080) 392 #define ISPPRV_SET_TBL_DATA (0x084) 393 #define ISPPRV_CDC_THR0 (0x090) 394 #define ISPPRV_CDC_THR1 (ISPPRV_CDC_THR0 + (0x4)) 395 #define ISPPRV_CDC_THR2 (ISPPRV_CDC_THR0 + (0x4) * 2) 396 #define ISPPRV_CDC_THR3 (ISPPRV_CDC_THR0 + (0x4) * 3) 397 398 #define ISPPRV_REDGAMMA_TABLE_ADDR 0x0000 399 #define ISPPRV_GREENGAMMA_TABLE_ADDR 0x0400 400 #define ISPPRV_BLUEGAMMA_TABLE_ADDR 0x0800 401 #define ISPPRV_NF_TABLE_ADDR 0x0C00 402 #define ISPPRV_YENH_TABLE_ADDR 0x1000 403 #define ISPPRV_CFA_TABLE_ADDR 0x1400 404 405 #define ISPRSZ_MIN_OUTPUT 64 406 #define ISPRSZ_MAX_OUTPUT 3312 407 408 /* Resizer module register offset */ 409 #define ISPRSZ_PID (0x000) 410 #define ISPRSZ_PCR (0x004) 411 #define ISPRSZ_CNT (0x008) 412 #define ISPRSZ_OUT_SIZE (0x00C) 413 #define ISPRSZ_IN_START (0x010) 414 #define ISPRSZ_IN_SIZE (0x014) 415 #define ISPRSZ_SDR_INADD (0x018) 416 #define ISPRSZ_SDR_INOFF (0x01C) 417 #define ISPRSZ_SDR_OUTADD (0x020) 418 #define ISPRSZ_SDR_OUTOFF (0x024) 419 #define ISPRSZ_HFILT10 (0x028) 420 #define ISPRSZ_HFILT32 (0x02C) 421 #define ISPRSZ_HFILT54 (0x030) 422 #define ISPRSZ_HFILT76 (0x034) 423 #define ISPRSZ_HFILT98 (0x038) 424 #define ISPRSZ_HFILT1110 (0x03C) 425 #define ISPRSZ_HFILT1312 (0x040) 426 #define ISPRSZ_HFILT1514 (0x044) 427 #define ISPRSZ_HFILT1716 (0x048) 428 #define ISPRSZ_HFILT1918 (0x04C) 429 #define ISPRSZ_HFILT2120 (0x050) 430 #define ISPRSZ_HFILT2322 (0x054) 431 #define ISPRSZ_HFILT2524 (0x058) 432 #define ISPRSZ_HFILT2726 (0x05C) 433 #define ISPRSZ_HFILT2928 (0x060) 434 #define ISPRSZ_HFILT3130 (0x064) 435 #define ISPRSZ_VFILT10 (0x068) 436 #define ISPRSZ_VFILT32 (0x06C) 437 #define ISPRSZ_VFILT54 (0x070) 438 #define ISPRSZ_VFILT76 (0x074) 439 #define ISPRSZ_VFILT98 (0x078) 440 #define ISPRSZ_VFILT1110 (0x07C) 441 #define ISPRSZ_VFILT1312 (0x080) 442 #define ISPRSZ_VFILT1514 (0x084) 443 #define ISPRSZ_VFILT1716 (0x088) 444 #define ISPRSZ_VFILT1918 (0x08C) 445 #define ISPRSZ_VFILT2120 (0x090) 446 #define ISPRSZ_VFILT2322 (0x094) 447 #define ISPRSZ_VFILT2524 (0x098) 448 #define ISPRSZ_VFILT2726 (0x09C) 449 #define ISPRSZ_VFILT2928 (0x0A0) 450 #define ISPRSZ_VFILT3130 (0x0A4) 451 #define ISPRSZ_YENH (0x0A8) 452 453 #define ISP_INT_CLR 0xFF113F11 454 #define ISPPRV_PCR_EN 1 455 #define ISPPRV_PCR_BUSY (1 << 1) 456 #define ISPPRV_PCR_SOURCE (1 << 2) 457 #define ISPPRV_PCR_ONESHOT (1 << 3) 458 #define ISPPRV_PCR_WIDTH (1 << 4) 459 #define ISPPRV_PCR_INVALAW (1 << 5) 460 #define ISPPRV_PCR_DRKFEN (1 << 6) 461 #define ISPPRV_PCR_DRKFCAP (1 << 7) 462 #define ISPPRV_PCR_HMEDEN (1 << 8) 463 #define ISPPRV_PCR_NFEN (1 << 9) 464 #define ISPPRV_PCR_CFAEN (1 << 10) 465 #define ISPPRV_PCR_CFAFMT_SHIFT 11 466 #define ISPPRV_PCR_CFAFMT_MASK 0x7800 467 #define ISPPRV_PCR_CFAFMT_BAYER (0 << 11) 468 #define ISPPRV_PCR_CFAFMT_SONYVGA (1 << 11) 469 #define ISPPRV_PCR_CFAFMT_RGBFOVEON (2 << 11) 470 #define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11) 471 #define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11) 472 #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11) 473 #define ISPPRV_PCR_YNENHEN (1 << 15) 474 #define ISPPRV_PCR_SUPEN (1 << 16) 475 #define ISPPRV_PCR_YCPOS_SHIFT 17 476 #define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17) 477 #define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17) 478 #define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17) 479 #define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17) 480 #define ISPPRV_PCR_RSZPORT (1 << 19) 481 #define ISPPRV_PCR_SDRPORT (1 << 20) 482 #define ISPPRV_PCR_SCOMP_EN (1 << 21) 483 #define ISPPRV_PCR_SCOMP_SFT_SHIFT (22) 484 #define ISPPRV_PCR_SCOMP_SFT_MASK (7 << 22) 485 #define ISPPRV_PCR_GAMMA_BYPASS (1 << 26) 486 #define ISPPRV_PCR_DCOREN (1 << 27) 487 #define ISPPRV_PCR_DCCOUP (1 << 28) 488 #define ISPPRV_PCR_DRK_FAIL (1 << 31) 489 490 #define ISPPRV_HORZ_INFO_EPH_SHIFT 0 491 #define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff 492 #define ISPPRV_HORZ_INFO_SPH_SHIFT 16 493 #define ISPPRV_HORZ_INFO_SPH_MASK 0x3fff0 494 495 #define ISPPRV_VERT_INFO_ELV_SHIFT 0 496 #define ISPPRV_VERT_INFO_ELV_MASK 0x3fff 497 #define ISPPRV_VERT_INFO_SLV_SHIFT 16 498 #define ISPPRV_VERT_INFO_SLV_MASK 0x3fff0 499 500 #define ISPPRV_AVE_EVENDIST_SHIFT 2 501 #define ISPPRV_AVE_EVENDIST_1 0x0 502 #define ISPPRV_AVE_EVENDIST_2 0x1 503 #define ISPPRV_AVE_EVENDIST_3 0x2 504 #define ISPPRV_AVE_EVENDIST_4 0x3 505 #define ISPPRV_AVE_ODDDIST_SHIFT 4 506 #define ISPPRV_AVE_ODDDIST_1 0x0 507 #define ISPPRV_AVE_ODDDIST_2 0x1 508 #define ISPPRV_AVE_ODDDIST_3 0x2 509 #define ISPPRV_AVE_ODDDIST_4 0x3 510 511 #define ISPPRV_HMED_THRESHOLD_SHIFT 0 512 #define ISPPRV_HMED_EVENDIST (1 << 8) 513 #define ISPPRV_HMED_ODDDIST (1 << 9) 514 515 #define ISPPRV_WBGAIN_COEF0_SHIFT 0 516 #define ISPPRV_WBGAIN_COEF1_SHIFT 8 517 #define ISPPRV_WBGAIN_COEF2_SHIFT 16 518 #define ISPPRV_WBGAIN_COEF3_SHIFT 24 519 520 #define ISPPRV_WBSEL_COEF0 0x0 521 #define ISPPRV_WBSEL_COEF1 0x1 522 #define ISPPRV_WBSEL_COEF2 0x2 523 #define ISPPRV_WBSEL_COEF3 0x3 524 525 #define ISPPRV_WBSEL_N0_0_SHIFT 0 526 #define ISPPRV_WBSEL_N0_1_SHIFT 2 527 #define ISPPRV_WBSEL_N0_2_SHIFT 4 528 #define ISPPRV_WBSEL_N0_3_SHIFT 6 529 #define ISPPRV_WBSEL_N1_0_SHIFT 8 530 #define ISPPRV_WBSEL_N1_1_SHIFT 10 531 #define ISPPRV_WBSEL_N1_2_SHIFT 12 532 #define ISPPRV_WBSEL_N1_3_SHIFT 14 533 #define ISPPRV_WBSEL_N2_0_SHIFT 16 534 #define ISPPRV_WBSEL_N2_1_SHIFT 18 535 #define ISPPRV_WBSEL_N2_2_SHIFT 20 536 #define ISPPRV_WBSEL_N2_3_SHIFT 22 537 #define ISPPRV_WBSEL_N3_0_SHIFT 24 538 #define ISPPRV_WBSEL_N3_1_SHIFT 26 539 #define ISPPRV_WBSEL_N3_2_SHIFT 28 540 #define ISPPRV_WBSEL_N3_3_SHIFT 30 541 542 #define ISPPRV_CFA_GRADTH_HOR_SHIFT 0 543 #define ISPPRV_CFA_GRADTH_VER_SHIFT 8 544 545 #define ISPPRV_BLKADJOFF_B_SHIFT 0 546 #define ISPPRV_BLKADJOFF_G_SHIFT 8 547 #define ISPPRV_BLKADJOFF_R_SHIFT 16 548 549 #define ISPPRV_RGB_MAT1_MTX_RR_SHIFT 0 550 #define ISPPRV_RGB_MAT1_MTX_GR_SHIFT 16 551 552 #define ISPPRV_RGB_MAT2_MTX_BR_SHIFT 0 553 #define ISPPRV_RGB_MAT2_MTX_RG_SHIFT 16 554 555 #define ISPPRV_RGB_MAT3_MTX_GG_SHIFT 0 556 #define ISPPRV_RGB_MAT3_MTX_BG_SHIFT 16 557 558 #define ISPPRV_RGB_MAT4_MTX_RB_SHIFT 0 559 #define ISPPRV_RGB_MAT4_MTX_GB_SHIFT 16 560 561 #define ISPPRV_RGB_MAT5_MTX_BB_SHIFT 0 562 563 #define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT 0 564 #define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT 16 565 566 #define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT 0 567 568 #define ISPPRV_CSC0_RY_SHIFT 0 569 #define ISPPRV_CSC0_GY_SHIFT 10 570 #define ISPPRV_CSC0_BY_SHIFT 20 571 572 #define ISPPRV_CSC1_RCB_SHIFT 0 573 #define ISPPRV_CSC1_GCB_SHIFT 10 574 #define ISPPRV_CSC1_BCB_SHIFT 20 575 576 #define ISPPRV_CSC2_RCR_SHIFT 0 577 #define ISPPRV_CSC2_GCR_SHIFT 10 578 #define ISPPRV_CSC2_BCR_SHIFT 20 579 580 #define ISPPRV_CSC_OFFSET_CR_SHIFT 0 581 #define ISPPRV_CSC_OFFSET_CB_SHIFT 8 582 #define ISPPRV_CSC_OFFSET_Y_SHIFT 16 583 584 #define ISPPRV_CNT_BRT_BRT_SHIFT 0 585 #define ISPPRV_CNT_BRT_CNT_SHIFT 8 586 587 #define ISPPRV_CONTRAST_MAX 0x10 588 #define ISPPRV_CONTRAST_MIN 0xFF 589 #define ISPPRV_BRIGHT_MIN 0x00 590 #define ISPPRV_BRIGHT_MAX 0xFF 591 592 #define ISPPRV_CSUP_CSUPG_SHIFT 0 593 #define ISPPRV_CSUP_THRES_SHIFT 8 594 #define ISPPRV_CSUP_HPYF_SHIFT 16 595 596 #define ISPPRV_SETUP_YC_MINC_SHIFT 0 597 #define ISPPRV_SETUP_YC_MAXC_SHIFT 8 598 #define ISPPRV_SETUP_YC_MINY_SHIFT 16 599 #define ISPPRV_SETUP_YC_MAXY_SHIFT 24 600 #define ISPPRV_YC_MAX 0xFF 601 #define ISPPRV_YC_MIN 0x0 602 603 /* Define bit fields within selected registers */ 604 #define ISP_REVISION_SHIFT 0 605 606 #define ISP_SYSCONFIG_AUTOIDLE (1 << 0) 607 #define ISP_SYSCONFIG_SOFTRESET (1 << 1) 608 #define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12 609 #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0 610 #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1 611 #define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x2 612 613 #define ISP_SYSSTATUS_RESETDONE 0 614 615 #define IRQ0ENABLE_CSIA_IRQ (1 << 0) 616 #define IRQ0ENABLE_CSIC_IRQ (1 << 1) 617 #define IRQ0ENABLE_CCP2_LCM_IRQ (1 << 3) 618 #define IRQ0ENABLE_CCP2_LC0_IRQ (1 << 4) 619 #define IRQ0ENABLE_CCP2_LC1_IRQ (1 << 5) 620 #define IRQ0ENABLE_CCP2_LC2_IRQ (1 << 6) 621 #define IRQ0ENABLE_CCP2_LC3_IRQ (1 << 7) 622 #define IRQ0ENABLE_CSIB_IRQ (IRQ0ENABLE_CCP2_LCM_IRQ | \ 623 IRQ0ENABLE_CCP2_LC0_IRQ | \ 624 IRQ0ENABLE_CCP2_LC1_IRQ | \ 625 IRQ0ENABLE_CCP2_LC2_IRQ | \ 626 IRQ0ENABLE_CCP2_LC3_IRQ) 627 628 #define IRQ0ENABLE_CCDC_VD0_IRQ (1 << 8) 629 #define IRQ0ENABLE_CCDC_VD1_IRQ (1 << 9) 630 #define IRQ0ENABLE_CCDC_VD2_IRQ (1 << 10) 631 #define IRQ0ENABLE_CCDC_ERR_IRQ (1 << 11) 632 #define IRQ0ENABLE_H3A_AF_DONE_IRQ (1 << 12) 633 #define IRQ0ENABLE_H3A_AWB_DONE_IRQ (1 << 13) 634 #define IRQ0ENABLE_HIST_DONE_IRQ (1 << 16) 635 #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ (1 << 17) 636 #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ (1 << 18) 637 #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ (1 << 19) 638 #define IRQ0ENABLE_PRV_DONE_IRQ (1 << 20) 639 #define IRQ0ENABLE_RSZ_DONE_IRQ (1 << 24) 640 #define IRQ0ENABLE_OVF_IRQ (1 << 25) 641 #define IRQ0ENABLE_PING_IRQ (1 << 26) 642 #define IRQ0ENABLE_PONG_IRQ (1 << 27) 643 #define IRQ0ENABLE_MMU_ERR_IRQ (1 << 28) 644 #define IRQ0ENABLE_OCP_ERR_IRQ (1 << 29) 645 #define IRQ0ENABLE_SEC_ERR_IRQ (1 << 30) 646 #define IRQ0ENABLE_HS_VS_IRQ (1 << 31) 647 648 #define IRQ0STATUS_CSIA_IRQ (1 << 0) 649 #define IRQ0STATUS_CSI2C_IRQ (1 << 1) 650 #define IRQ0STATUS_CCP2_LCM_IRQ (1 << 3) 651 #define IRQ0STATUS_CCP2_LC0_IRQ (1 << 4) 652 #define IRQ0STATUS_CSIB_IRQ (IRQ0STATUS_CCP2_LCM_IRQ | \ 653 IRQ0STATUS_CCP2_LC0_IRQ) 654 655 #define IRQ0STATUS_CSIB_LC1_IRQ (1 << 5) 656 #define IRQ0STATUS_CSIB_LC2_IRQ (1 << 6) 657 #define IRQ0STATUS_CSIB_LC3_IRQ (1 << 7) 658 #define IRQ0STATUS_CCDC_VD0_IRQ (1 << 8) 659 #define IRQ0STATUS_CCDC_VD1_IRQ (1 << 9) 660 #define IRQ0STATUS_CCDC_VD2_IRQ (1 << 10) 661 #define IRQ0STATUS_CCDC_ERR_IRQ (1 << 11) 662 #define IRQ0STATUS_H3A_AF_DONE_IRQ (1 << 12) 663 #define IRQ0STATUS_H3A_AWB_DONE_IRQ (1 << 13) 664 #define IRQ0STATUS_HIST_DONE_IRQ (1 << 16) 665 #define IRQ0STATUS_CCDC_LSC_DONE_IRQ (1 << 17) 666 #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ (1 << 18) 667 #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ (1 << 19) 668 #define IRQ0STATUS_PRV_DONE_IRQ (1 << 20) 669 #define IRQ0STATUS_RSZ_DONE_IRQ (1 << 24) 670 #define IRQ0STATUS_OVF_IRQ (1 << 25) 671 #define IRQ0STATUS_PING_IRQ (1 << 26) 672 #define IRQ0STATUS_PONG_IRQ (1 << 27) 673 #define IRQ0STATUS_MMU_ERR_IRQ (1 << 28) 674 #define IRQ0STATUS_OCP_ERR_IRQ (1 << 29) 675 #define IRQ0STATUS_SEC_ERR_IRQ (1 << 30) 676 #define IRQ0STATUS_HS_VS_IRQ (1 << 31) 677 678 #define TCTRL_GRESET_LEN 0 679 680 #define TCTRL_PSTRB_REPLAY_DELAY 0 681 #define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT 25 682 683 #define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL 0x0 684 #define ISPCTRL_PAR_SER_CLK_SEL_CSIA 0x1 685 #define ISPCTRL_PAR_SER_CLK_SEL_CSIB 0x2 686 #define ISPCTRL_PAR_SER_CLK_SEL_CSIC 0x3 687 #define ISPCTRL_PAR_SER_CLK_SEL_MASK 0x3 688 689 #define ISPCTRL_PAR_BRIDGE_SHIFT 2 690 #define ISPCTRL_PAR_BRIDGE_DISABLE (0x0 << 2) 691 #define ISPCTRL_PAR_BRIDGE_LENDIAN (0x2 << 2) 692 #define ISPCTRL_PAR_BRIDGE_BENDIAN (0x3 << 2) 693 #define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2) 694 695 #define ISPCTRL_PAR_CLK_POL_SHIFT 4 696 #define ISPCTRL_PAR_CLK_POL_INV (1 << 4) 697 #define ISPCTRL_PING_PONG_EN (1 << 5) 698 #define ISPCTRL_SHIFT_SHIFT 6 699 #define ISPCTRL_SHIFT_0 (0x0 << 6) 700 #define ISPCTRL_SHIFT_2 (0x1 << 6) 701 #define ISPCTRL_SHIFT_4 (0x2 << 6) 702 #define ISPCTRL_SHIFT_MASK (0x3 << 6) 703 704 #define ISPCTRL_CCDC_CLK_EN (1 << 8) 705 #define ISPCTRL_SCMP_CLK_EN (1 << 9) 706 #define ISPCTRL_H3A_CLK_EN (1 << 10) 707 #define ISPCTRL_HIST_CLK_EN (1 << 11) 708 #define ISPCTRL_PREV_CLK_EN (1 << 12) 709 #define ISPCTRL_RSZ_CLK_EN (1 << 13) 710 #define ISPCTRL_SYNC_DETECT_SHIFT 14 711 #define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT) 712 #define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT) 713 #define ISPCTRL_SYNC_DETECT_VSFALL (0x2 << ISPCTRL_SYNC_DETECT_SHIFT) 714 #define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) 715 #define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) 716 717 #define ISPCTRL_CCDC_RAM_EN (1 << 16) 718 #define ISPCTRL_PREV_RAM_EN (1 << 17) 719 #define ISPCTRL_SBL_RD_RAM_EN (1 << 18) 720 #define ISPCTRL_SBL_WR1_RAM_EN (1 << 19) 721 #define ISPCTRL_SBL_WR0_RAM_EN (1 << 20) 722 #define ISPCTRL_SBL_AUTOIDLE (1 << 21) 723 #define ISPCTRL_SBL_SHARED_WPORTC (1 << 26) 724 #define ISPCTRL_SBL_SHARED_RPORTA (1 << 27) 725 #define ISPCTRL_SBL_SHARED_RPORTB (1 << 28) 726 #define ISPCTRL_JPEG_FLUSH (1 << 30) 727 #define ISPCTRL_CCDC_FLUSH (1 << 31) 728 729 #define ISPSECURE_SECUREMODE 0 730 731 #define ISPTCTRL_CTRL_DIV_LOW 0x0 732 #define ISPTCTRL_CTRL_DIV_HIGH 0x1 733 #define ISPTCTRL_CTRL_DIV_BYPASS 0x1F 734 735 #define ISPTCTRL_CTRL_DIVA_SHIFT 0 736 #define ISPTCTRL_CTRL_DIVA_MASK (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT) 737 738 #define ISPTCTRL_CTRL_DIVB_SHIFT 5 739 #define ISPTCTRL_CTRL_DIVB_MASK (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT) 740 741 #define ISPTCTRL_CTRL_DIVC_SHIFT 10 742 #define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10) 743 744 #define ISPTCTRL_CTRL_SHUTEN (1 << 21) 745 #define ISPTCTRL_CTRL_PSTRBEN (1 << 22) 746 #define ISPTCTRL_CTRL_STRBEN (1 << 23) 747 #define ISPTCTRL_CTRL_SHUTPOL (1 << 24) 748 #define ISPTCTRL_CTRL_STRBPSTRBPOL (1 << 26) 749 750 #define ISPTCTRL_CTRL_INSEL_SHIFT 27 751 #define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27) 752 #define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27) 753 #define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27) 754 755 #define ISPTCTRL_CTRL_GRESETEn (1 << 29) 756 #define ISPTCTRL_CTRL_GRESETPOL (1 << 30) 757 #define ISPTCTRL_CTRL_GRESETDIR (1 << 31) 758 759 #define ISPTCTRL_FRAME_SHUT_SHIFT 0 760 #define ISPTCTRL_FRAME_PSTRB_SHIFT 6 761 #define ISPTCTRL_FRAME_STRB_SHIFT 12 762 763 #define ISPCCDC_PID_PREV_SHIFT 0 764 #define ISPCCDC_PID_CID_SHIFT 8 765 #define ISPCCDC_PID_TID_SHIFT 16 766 767 #define ISPCCDC_PCR_EN 1 768 #define ISPCCDC_PCR_BUSY (1 << 1) 769 770 #define ISPCCDC_SYN_MODE_VDHDOUT 0x1 771 #define ISPCCDC_SYN_MODE_FLDOUT (1 << 1) 772 #define ISPCCDC_SYN_MODE_VDPOL (1 << 2) 773 #define ISPCCDC_SYN_MODE_HDPOL (1 << 3) 774 #define ISPCCDC_SYN_MODE_FLDPOL (1 << 4) 775 #define ISPCCDC_SYN_MODE_EXWEN (1 << 5) 776 #define ISPCCDC_SYN_MODE_DATAPOL (1 << 6) 777 #define ISPCCDC_SYN_MODE_FLDMODE (1 << 7) 778 #define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8) 779 #define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8) 780 #define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8) 781 #define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8) 782 #define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8) 783 #define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8) 784 #define ISPCCDC_SYN_MODE_PACK8 (1 << 11) 785 #define ISPCCDC_SYN_MODE_INPMOD_MASK (3 << 12) 786 #define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12) 787 #define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12) 788 #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12) 789 #define ISPCCDC_SYN_MODE_LPF (1 << 14) 790 #define ISPCCDC_SYN_MODE_FLDSTAT (1 << 15) 791 #define ISPCCDC_SYN_MODE_VDHDEN (1 << 16) 792 #define ISPCCDC_SYN_MODE_WEN (1 << 17) 793 #define ISPCCDC_SYN_MODE_VP2SDR (1 << 18) 794 #define ISPCCDC_SYN_MODE_SDR2RSZ (1 << 19) 795 796 #define ISPCCDC_HD_VD_WID_VDW_SHIFT 0 797 #define ISPCCDC_HD_VD_WID_HDW_SHIFT 16 798 799 #define ISPCCDC_PIX_LINES_HLPRF_SHIFT 0 800 #define ISPCCDC_PIX_LINES_PPLN_SHIFT 16 801 802 #define ISPCCDC_HORZ_INFO_NPH_SHIFT 0 803 #define ISPCCDC_HORZ_INFO_NPH_MASK 0x00007fff 804 #define ISPCCDC_HORZ_INFO_SPH_SHIFT 16 805 #define ISPCCDC_HORZ_INFO_SPH_MASK 0x7fff0000 806 807 #define ISPCCDC_VERT_START_SLV1_SHIFT 0 808 #define ISPCCDC_VERT_START_SLV0_SHIFT 16 809 #define ISPCCDC_VERT_START_SLV0_MASK 0x7fff0000 810 811 #define ISPCCDC_VERT_LINES_NLV_SHIFT 0 812 #define ISPCCDC_VERT_LINES_NLV_MASK 0x00007fff 813 814 #define ISPCCDC_CULLING_CULV_SHIFT 0 815 #define ISPCCDC_CULLING_CULHODD_SHIFT 16 816 #define ISPCCDC_CULLING_CULHEVN_SHIFT 24 817 818 #define ISPCCDC_HSIZE_OFF_SHIFT 0 819 820 #define ISPCCDC_SDOFST_FINV (1 << 14) 821 #define ISPCCDC_SDOFST_FOFST_1L 0 822 #define ISPCCDC_SDOFST_FOFST_4L (3 << 12) 823 #define ISPCCDC_SDOFST_LOFST3_SHIFT 0 824 #define ISPCCDC_SDOFST_LOFST2_SHIFT 3 825 #define ISPCCDC_SDOFST_LOFST1_SHIFT 6 826 #define ISPCCDC_SDOFST_LOFST0_SHIFT 9 827 #define EVENEVEN 1 828 #define ODDEVEN 2 829 #define EVENODD 3 830 #define ODDODD 4 831 832 #define ISPCCDC_CLAMP_OBGAIN_SHIFT 0 833 #define ISPCCDC_CLAMP_OBST_SHIFT 10 834 #define ISPCCDC_CLAMP_OBSLN_SHIFT 25 835 #define ISPCCDC_CLAMP_OBSLEN_SHIFT 28 836 #define ISPCCDC_CLAMP_CLAMPEN (1 << 31) 837 838 #define ISPCCDC_COLPTN_R_Ye 0x0 839 #define ISPCCDC_COLPTN_Gr_Cy 0x1 840 #define ISPCCDC_COLPTN_Gb_G 0x2 841 #define ISPCCDC_COLPTN_B_Mg 0x3 842 #define ISPCCDC_COLPTN_CP0PLC0_SHIFT 0 843 #define ISPCCDC_COLPTN_CP0PLC1_SHIFT 2 844 #define ISPCCDC_COLPTN_CP0PLC2_SHIFT 4 845 #define ISPCCDC_COLPTN_CP0PLC3_SHIFT 6 846 #define ISPCCDC_COLPTN_CP1PLC0_SHIFT 8 847 #define ISPCCDC_COLPTN_CP1PLC1_SHIFT 10 848 #define ISPCCDC_COLPTN_CP1PLC2_SHIFT 12 849 #define ISPCCDC_COLPTN_CP1PLC3_SHIFT 14 850 #define ISPCCDC_COLPTN_CP2PLC0_SHIFT 16 851 #define ISPCCDC_COLPTN_CP2PLC1_SHIFT 18 852 #define ISPCCDC_COLPTN_CP2PLC2_SHIFT 20 853 #define ISPCCDC_COLPTN_CP2PLC3_SHIFT 22 854 #define ISPCCDC_COLPTN_CP3PLC0_SHIFT 24 855 #define ISPCCDC_COLPTN_CP3PLC1_SHIFT 26 856 #define ISPCCDC_COLPTN_CP3PLC2_SHIFT 28 857 #define ISPCCDC_COLPTN_CP3PLC3_SHIFT 30 858 859 #define ISPCCDC_BLKCMP_B_MG_SHIFT 0 860 #define ISPCCDC_BLKCMP_GB_G_SHIFT 8 861 #define ISPCCDC_BLKCMP_GR_CY_SHIFT 16 862 #define ISPCCDC_BLKCMP_R_YE_SHIFT 24 863 864 #define ISPCCDC_FPC_FPNUM_SHIFT 0 865 #define ISPCCDC_FPC_FPCEN (1 << 15) 866 #define ISPCCDC_FPC_FPERR (1 << 16) 867 868 #define ISPCCDC_VDINT_1_SHIFT 0 869 #define ISPCCDC_VDINT_1_MASK 0x00007fff 870 #define ISPCCDC_VDINT_0_SHIFT 16 871 #define ISPCCDC_VDINT_0_MASK 0x7fff0000 872 873 #define ISPCCDC_ALAW_GWDI_12_3 (0x3 << 0) 874 #define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0) 875 #define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0) 876 #define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0) 877 #define ISPCCDC_ALAW_CCDTBL (1 << 3) 878 879 #define ISPCCDC_REC656IF_R656ON 1 880 #define ISPCCDC_REC656IF_ECCFVH (1 << 1) 881 882 #define ISPCCDC_CFG_BW656 (1 << 5) 883 #define ISPCCDC_CFG_FIDMD_SHIFT 6 884 #define ISPCCDC_CFG_WENLOG (1 << 8) 885 #define ISPCCDC_CFG_WENLOG_AND (0 << 8) 886 #define ISPCCDC_CFG_WENLOG_OR (1 << 8) 887 #define ISPCCDC_CFG_Y8POS (1 << 11) 888 #define ISPCCDC_CFG_BSWD (1 << 12) 889 #define ISPCCDC_CFG_MSBINVI (1 << 13) 890 #define ISPCCDC_CFG_VDLC (1 << 15) 891 892 #define ISPCCDC_FMTCFG_FMTEN 0x1 893 #define ISPCCDC_FMTCFG_LNALT (1 << 1) 894 #define ISPCCDC_FMTCFG_LNUM_SHIFT 2 895 #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4 896 #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8 897 #define ISPCCDC_FMTCFG_VPIN_MASK 0x00007000 898 #define ISPCCDC_FMTCFG_VPIN_12_3 (0x3 << 12) 899 #define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12) 900 #define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12) 901 #define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12) 902 #define ISPCCDC_FMTCFG_VPEN (1 << 15) 903 904 #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000 905 #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16 906 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2 (0x0 << 16) 907 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 (0x1 << 16) 908 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4 (0x2 << 16) 909 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5 (0x3 << 16) 910 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6 (0x4 << 16) 911 912 #define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT 0 913 #define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT 16 914 915 #define ISPCCDC_FMT_VERT_FMTLNV_SHIFT 0 916 #define ISPCCDC_FMT_VERT_FMTSLV_SHIFT 16 917 918 #define ISPCCDC_FMT_HORZ_FMTSPH_MASK 0x1fff0000 919 #define ISPCCDC_FMT_HORZ_FMTLNH_MASK 0x00001fff 920 921 #define ISPCCDC_FMT_VERT_FMTSLV_MASK 0x1fff0000 922 #define ISPCCDC_FMT_VERT_FMTLNV_MASK 0x00001fff 923 924 #define ISPCCDC_VP_OUT_HORZ_ST_SHIFT 0 925 #define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT 4 926 #define ISPCCDC_VP_OUT_VERT_NUM_SHIFT 17 927 928 #define ISPRSZ_PID_PREV_SHIFT 0 929 #define ISPRSZ_PID_CID_SHIFT 8 930 #define ISPRSZ_PID_TID_SHIFT 16 931 932 #define ISPRSZ_PCR_ENABLE (1 << 0) 933 #define ISPRSZ_PCR_BUSY (1 << 1) 934 #define ISPRSZ_PCR_ONESHOT (1 << 2) 935 936 #define ISPRSZ_CNT_HRSZ_SHIFT 0 937 #define ISPRSZ_CNT_HRSZ_MASK \ 938 (0x3FF << ISPRSZ_CNT_HRSZ_SHIFT) 939 #define ISPRSZ_CNT_VRSZ_SHIFT 10 940 #define ISPRSZ_CNT_VRSZ_MASK \ 941 (0x3FF << ISPRSZ_CNT_VRSZ_SHIFT) 942 #define ISPRSZ_CNT_HSTPH_SHIFT 20 943 #define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT) 944 #define ISPRSZ_CNT_VSTPH_SHIFT 23 945 #define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT) 946 #define ISPRSZ_CNT_YCPOS (1 << 26) 947 #define ISPRSZ_CNT_INPTYP (1 << 27) 948 #define ISPRSZ_CNT_INPSRC (1 << 28) 949 #define ISPRSZ_CNT_CBILIN (1 << 29) 950 951 #define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0 952 #define ISPRSZ_OUT_SIZE_HORZ_MASK \ 953 (0xFFF << ISPRSZ_OUT_SIZE_HORZ_SHIFT) 954 #define ISPRSZ_OUT_SIZE_VERT_SHIFT 16 955 #define ISPRSZ_OUT_SIZE_VERT_MASK \ 956 (0xFFF << ISPRSZ_OUT_SIZE_VERT_SHIFT) 957 958 #define ISPRSZ_IN_START_HORZ_ST_SHIFT 0 959 #define ISPRSZ_IN_START_HORZ_ST_MASK \ 960 (0x1FFF << ISPRSZ_IN_START_HORZ_ST_SHIFT) 961 #define ISPRSZ_IN_START_VERT_ST_SHIFT 16 962 #define ISPRSZ_IN_START_VERT_ST_MASK \ 963 (0x1FFF << ISPRSZ_IN_START_VERT_ST_SHIFT) 964 965 #define ISPRSZ_IN_SIZE_HORZ_SHIFT 0 966 #define ISPRSZ_IN_SIZE_HORZ_MASK \ 967 (0x1FFF << ISPRSZ_IN_SIZE_HORZ_SHIFT) 968 #define ISPRSZ_IN_SIZE_VERT_SHIFT 16 969 #define ISPRSZ_IN_SIZE_VERT_MASK \ 970 (0x1FFF << ISPRSZ_IN_SIZE_VERT_SHIFT) 971 972 #define ISPRSZ_SDR_INADD_ADDR_SHIFT 0 973 #define ISPRSZ_SDR_INADD_ADDR_MASK 0xFFFFFFFF 974 975 #define ISPRSZ_SDR_INOFF_OFFSET_SHIFT 0 976 #define ISPRSZ_SDR_INOFF_OFFSET_MASK \ 977 (0xFFFF << ISPRSZ_SDR_INOFF_OFFSET_SHIFT) 978 979 #define ISPRSZ_SDR_OUTADD_ADDR_SHIFT 0 980 #define ISPRSZ_SDR_OUTADD_ADDR_MASK 0xFFFFFFFF 981 982 983 #define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT 0 984 #define ISPRSZ_SDR_OUTOFF_OFFSET_MASK \ 985 (0xFFFF << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT) 986 987 #define ISPRSZ_HFILT_COEF0_SHIFT 0 988 #define ISPRSZ_HFILT_COEF0_MASK \ 989 (0x3FF << ISPRSZ_HFILT_COEF0_SHIFT) 990 #define ISPRSZ_HFILT_COEF1_SHIFT 16 991 #define ISPRSZ_HFILT_COEF1_MASK \ 992 (0x3FF << ISPRSZ_HFILT_COEF1_SHIFT) 993 994 #define ISPRSZ_HFILT32_COEF2_SHIFT 0 995 #define ISPRSZ_HFILT32_COEF2_MASK 0x3FF 996 #define ISPRSZ_HFILT32_COEF3_SHIFT 16 997 #define ISPRSZ_HFILT32_COEF3_MASK 0x3FF0000 998 999 #define ISPRSZ_HFILT54_COEF4_SHIFT 0 1000 #define ISPRSZ_HFILT54_COEF4_MASK 0x3FF 1001 #define ISPRSZ_HFILT54_COEF5_SHIFT 16 1002 #define ISPRSZ_HFILT54_COEF5_MASK 0x3FF0000 1003 1004 #define ISPRSZ_HFILT76_COEFF6_SHIFT 0 1005 #define ISPRSZ_HFILT76_COEFF6_MASK 0x3FF 1006 #define ISPRSZ_HFILT76_COEFF7_SHIFT 16 1007 #define ISPRSZ_HFILT76_COEFF7_MASK 0x3FF0000 1008 1009 #define ISPRSZ_HFILT98_COEFF8_SHIFT 0 1010 #define ISPRSZ_HFILT98_COEFF8_MASK 0x3FF 1011 #define ISPRSZ_HFILT98_COEFF9_SHIFT 16 1012 #define ISPRSZ_HFILT98_COEFF9_MASK 0x3FF0000 1013 1014 #define ISPRSZ_HFILT1110_COEF10_SHIFT 0 1015 #define ISPRSZ_HFILT1110_COEF10_MASK 0x3FF 1016 #define ISPRSZ_HFILT1110_COEF11_SHIFT 16 1017 #define ISPRSZ_HFILT1110_COEF11_MASK 0x3FF0000 1018 1019 #define ISPRSZ_HFILT1312_COEFF12_SHIFT 0 1020 #define ISPRSZ_HFILT1312_COEFF12_MASK 0x3FF 1021 #define ISPRSZ_HFILT1312_COEFF13_SHIFT 16 1022 #define ISPRSZ_HFILT1312_COEFF13_MASK 0x3FF0000 1023 1024 #define ISPRSZ_HFILT1514_COEFF14_SHIFT 0 1025 #define ISPRSZ_HFILT1514_COEFF14_MASK 0x3FF 1026 #define ISPRSZ_HFILT1514_COEFF15_SHIFT 16 1027 #define ISPRSZ_HFILT1514_COEFF15_MASK 0x3FF0000 1028 1029 #define ISPRSZ_HFILT1716_COEF16_SHIFT 0 1030 #define ISPRSZ_HFILT1716_COEF16_MASK 0x3FF 1031 #define ISPRSZ_HFILT1716_COEF17_SHIFT 16 1032 #define ISPRSZ_HFILT1716_COEF17_MASK 0x3FF0000 1033 1034 #define ISPRSZ_HFILT1918_COEF18_SHIFT 0 1035 #define ISPRSZ_HFILT1918_COEF18_MASK 0x3FF 1036 #define ISPRSZ_HFILT1918_COEF19_SHIFT 16 1037 #define ISPRSZ_HFILT1918_COEF19_MASK 0x3FF0000 1038 1039 #define ISPRSZ_HFILT2120_COEF20_SHIFT 0 1040 #define ISPRSZ_HFILT2120_COEF20_MASK 0x3FF 1041 #define ISPRSZ_HFILT2120_COEF21_SHIFT 16 1042 #define ISPRSZ_HFILT2120_COEF21_MASK 0x3FF0000 1043 1044 #define ISPRSZ_HFILT2322_COEF22_SHIFT 0 1045 #define ISPRSZ_HFILT2322_COEF22_MASK 0x3FF 1046 #define ISPRSZ_HFILT2322_COEF23_SHIFT 16 1047 #define ISPRSZ_HFILT2322_COEF23_MASK 0x3FF0000 1048 1049 #define ISPRSZ_HFILT2524_COEF24_SHIFT 0 1050 #define ISPRSZ_HFILT2524_COEF24_MASK 0x3FF 1051 #define ISPRSZ_HFILT2524_COEF25_SHIFT 16 1052 #define ISPRSZ_HFILT2524_COEF25_MASK 0x3FF0000 1053 1054 #define ISPRSZ_HFILT2726_COEF26_SHIFT 0 1055 #define ISPRSZ_HFILT2726_COEF26_MASK 0x3FF 1056 #define ISPRSZ_HFILT2726_COEF27_SHIFT 16 1057 #define ISPRSZ_HFILT2726_COEF27_MASK 0x3FF0000 1058 1059 #define ISPRSZ_HFILT2928_COEF28_SHIFT 0 1060 #define ISPRSZ_HFILT2928_COEF28_MASK 0x3FF 1061 #define ISPRSZ_HFILT2928_COEF29_SHIFT 16 1062 #define ISPRSZ_HFILT2928_COEF29_MASK 0x3FF0000 1063 1064 #define ISPRSZ_HFILT3130_COEF30_SHIFT 0 1065 #define ISPRSZ_HFILT3130_COEF30_MASK 0x3FF 1066 #define ISPRSZ_HFILT3130_COEF31_SHIFT 16 1067 #define ISPRSZ_HFILT3130_COEF31_MASK 0x3FF0000 1068 1069 #define ISPRSZ_VFILT_COEF0_SHIFT 0 1070 #define ISPRSZ_VFILT_COEF0_MASK \ 1071 (0x3FF << ISPRSZ_VFILT_COEF0_SHIFT) 1072 #define ISPRSZ_VFILT_COEF1_SHIFT 16 1073 #define ISPRSZ_VFILT_COEF1_MASK \ 1074 (0x3FF << ISPRSZ_VFILT_COEF1_SHIFT) 1075 1076 #define ISPRSZ_VFILT10_COEF0_SHIFT 0 1077 #define ISPRSZ_VFILT10_COEF0_MASK 0x3FF 1078 #define ISPRSZ_VFILT10_COEF1_SHIFT 16 1079 #define ISPRSZ_VFILT10_COEF1_MASK 0x3FF0000 1080 1081 #define ISPRSZ_VFILT32_COEF2_SHIFT 0 1082 #define ISPRSZ_VFILT32_COEF2_MASK 0x3FF 1083 #define ISPRSZ_VFILT32_COEF3_SHIFT 16 1084 #define ISPRSZ_VFILT32_COEF3_MASK 0x3FF0000 1085 1086 #define ISPRSZ_VFILT54_COEF4_SHIFT 0 1087 #define ISPRSZ_VFILT54_COEF4_MASK 0x3FF 1088 #define ISPRSZ_VFILT54_COEF5_SHIFT 16 1089 #define ISPRSZ_VFILT54_COEF5_MASK 0x3FF0000 1090 1091 #define ISPRSZ_VFILT76_COEFF6_SHIFT 0 1092 #define ISPRSZ_VFILT76_COEFF6_MASK 0x3FF 1093 #define ISPRSZ_VFILT76_COEFF7_SHIFT 16 1094 #define ISPRSZ_VFILT76_COEFF7_MASK 0x3FF0000 1095 1096 #define ISPRSZ_VFILT98_COEFF8_SHIFT 0 1097 #define ISPRSZ_VFILT98_COEFF8_MASK 0x3FF 1098 #define ISPRSZ_VFILT98_COEFF9_SHIFT 16 1099 #define ISPRSZ_VFILT98_COEFF9_MASK 0x3FF0000 1100 1101 #define ISPRSZ_VFILT1110_COEF10_SHIFT 0 1102 #define ISPRSZ_VFILT1110_COEF10_MASK 0x3FF 1103 #define ISPRSZ_VFILT1110_COEF11_SHIFT 16 1104 #define ISPRSZ_VFILT1110_COEF11_MASK 0x3FF0000 1105 1106 #define ISPRSZ_VFILT1312_COEFF12_SHIFT 0 1107 #define ISPRSZ_VFILT1312_COEFF12_MASK 0x3FF 1108 #define ISPRSZ_VFILT1312_COEFF13_SHIFT 16 1109 #define ISPRSZ_VFILT1312_COEFF13_MASK 0x3FF0000 1110 1111 #define ISPRSZ_VFILT1514_COEFF14_SHIFT 0 1112 #define ISPRSZ_VFILT1514_COEFF14_MASK 0x3FF 1113 #define ISPRSZ_VFILT1514_COEFF15_SHIFT 16 1114 #define ISPRSZ_VFILT1514_COEFF15_MASK 0x3FF0000 1115 1116 #define ISPRSZ_VFILT1716_COEF16_SHIFT 0 1117 #define ISPRSZ_VFILT1716_COEF16_MASK 0x3FF 1118 #define ISPRSZ_VFILT1716_COEF17_SHIFT 16 1119 #define ISPRSZ_VFILT1716_COEF17_MASK 0x3FF0000 1120 1121 #define ISPRSZ_VFILT1918_COEF18_SHIFT 0 1122 #define ISPRSZ_VFILT1918_COEF18_MASK 0x3FF 1123 #define ISPRSZ_VFILT1918_COEF19_SHIFT 16 1124 #define ISPRSZ_VFILT1918_COEF19_MASK 0x3FF0000 1125 1126 #define ISPRSZ_VFILT2120_COEF20_SHIFT 0 1127 #define ISPRSZ_VFILT2120_COEF20_MASK 0x3FF 1128 #define ISPRSZ_VFILT2120_COEF21_SHIFT 16 1129 #define ISPRSZ_VFILT2120_COEF21_MASK 0x3FF0000 1130 1131 #define ISPRSZ_VFILT2322_COEF22_SHIFT 0 1132 #define ISPRSZ_VFILT2322_COEF22_MASK 0x3FF 1133 #define ISPRSZ_VFILT2322_COEF23_SHIFT 16 1134 #define ISPRSZ_VFILT2322_COEF23_MASK 0x3FF0000 1135 1136 #define ISPRSZ_VFILT2524_COEF24_SHIFT 0 1137 #define ISPRSZ_VFILT2524_COEF24_MASK 0x3FF 1138 #define ISPRSZ_VFILT2524_COEF25_SHIFT 16 1139 #define ISPRSZ_VFILT2524_COEF25_MASK 0x3FF0000 1140 1141 #define ISPRSZ_VFILT2726_COEF26_SHIFT 0 1142 #define ISPRSZ_VFILT2726_COEF26_MASK 0x3FF 1143 #define ISPRSZ_VFILT2726_COEF27_SHIFT 16 1144 #define ISPRSZ_VFILT2726_COEF27_MASK 0x3FF0000 1145 1146 #define ISPRSZ_VFILT2928_COEF28_SHIFT 0 1147 #define ISPRSZ_VFILT2928_COEF28_MASK 0x3FF 1148 #define ISPRSZ_VFILT2928_COEF29_SHIFT 16 1149 #define ISPRSZ_VFILT2928_COEF29_MASK 0x3FF0000 1150 1151 #define ISPRSZ_VFILT3130_COEF30_SHIFT 0 1152 #define ISPRSZ_VFILT3130_COEF30_MASK 0x3FF 1153 #define ISPRSZ_VFILT3130_COEF31_SHIFT 16 1154 #define ISPRSZ_VFILT3130_COEF31_MASK 0x3FF0000 1155 1156 #define ISPRSZ_YENH_CORE_SHIFT 0 1157 #define ISPRSZ_YENH_CORE_MASK \ 1158 (0xFF << ISPRSZ_YENH_CORE_SHIFT) 1159 #define ISPRSZ_YENH_SLOP_SHIFT 8 1160 #define ISPRSZ_YENH_SLOP_MASK \ 1161 (0xF << ISPRSZ_YENH_SLOP_SHIFT) 1162 #define ISPRSZ_YENH_GAIN_SHIFT 12 1163 #define ISPRSZ_YENH_GAIN_MASK \ 1164 (0xF << ISPRSZ_YENH_GAIN_SHIFT) 1165 #define ISPRSZ_YENH_ALGO_SHIFT 16 1166 #define ISPRSZ_YENH_ALGO_MASK \ 1167 (0x3 << ISPRSZ_YENH_ALGO_SHIFT) 1168 1169 #define ISPH3A_PCR_AEW_ALAW_EN_SHIFT 1 1170 #define ISPH3A_PCR_AF_MED_TH_SHIFT 3 1171 #define ISPH3A_PCR_AF_RGBPOS_SHIFT 11 1172 #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22 1173 #define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000 1174 #define ISPH3A_PCR_BUSYAF (1 << 15) 1175 #define ISPH3A_PCR_BUSYAEAWB (1 << 18) 1176 1177 #define ISPH3A_AEWWIN1_WINHC_SHIFT 0 1178 #define ISPH3A_AEWWIN1_WINHC_MASK 0x3F 1179 #define ISPH3A_AEWWIN1_WINVC_SHIFT 6 1180 #define ISPH3A_AEWWIN1_WINVC_MASK 0x1FC0 1181 #define ISPH3A_AEWWIN1_WINW_SHIFT 13 1182 #define ISPH3A_AEWWIN1_WINW_MASK 0xFE000 1183 #define ISPH3A_AEWWIN1_WINH_SHIFT 24 1184 #define ISPH3A_AEWWIN1_WINH_MASK 0x7F000000 1185 1186 #define ISPH3A_AEWINSTART_WINSH_SHIFT 0 1187 #define ISPH3A_AEWINSTART_WINSH_MASK 0x0FFF 1188 #define ISPH3A_AEWINSTART_WINSV_SHIFT 16 1189 #define ISPH3A_AEWINSTART_WINSV_MASK 0x0FFF0000 1190 1191 #define ISPH3A_AEWINBLK_WINH_SHIFT 0 1192 #define ISPH3A_AEWINBLK_WINH_MASK 0x7F 1193 #define ISPH3A_AEWINBLK_WINSV_SHIFT 16 1194 #define ISPH3A_AEWINBLK_WINSV_MASK 0x0FFF0000 1195 1196 #define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT 0 1197 #define ISPH3A_AEWSUBWIN_AEWINCH_MASK 0x0F 1198 #define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT 8 1199 #define ISPH3A_AEWSUBWIN_AEWINCV_MASK 0x0F00 1200 1201 #define ISPHIST_PCR_ENABLE_SHIFT 0 1202 #define ISPHIST_PCR_ENABLE_MASK 0x01 1203 #define ISPHIST_PCR_ENABLE (1 << ISPHIST_PCR_ENABLE_SHIFT) 1204 #define ISPHIST_PCR_BUSY 0x02 1205 1206 #define ISPHIST_CNT_DATASIZE_SHIFT 8 1207 #define ISPHIST_CNT_DATASIZE_MASK 0x0100 1208 #define ISPHIST_CNT_CLEAR_SHIFT 7 1209 #define ISPHIST_CNT_CLEAR_MASK 0x080 1210 #define ISPHIST_CNT_CLEAR (1 << ISPHIST_CNT_CLEAR_SHIFT) 1211 #define ISPHIST_CNT_CFA_SHIFT 6 1212 #define ISPHIST_CNT_CFA_MASK 0x040 1213 #define ISPHIST_CNT_BINS_SHIFT 4 1214 #define ISPHIST_CNT_BINS_MASK 0x030 1215 #define ISPHIST_CNT_SOURCE_SHIFT 3 1216 #define ISPHIST_CNT_SOURCE_MASK 0x08 1217 #define ISPHIST_CNT_SHIFT_SHIFT 0 1218 #define ISPHIST_CNT_SHIFT_MASK 0x07 1219 1220 #define ISPHIST_WB_GAIN_WG00_SHIFT 24 1221 #define ISPHIST_WB_GAIN_WG00_MASK 0xFF000000 1222 #define ISPHIST_WB_GAIN_WG01_SHIFT 16 1223 #define ISPHIST_WB_GAIN_WG01_MASK 0xFF0000 1224 #define ISPHIST_WB_GAIN_WG02_SHIFT 8 1225 #define ISPHIST_WB_GAIN_WG02_MASK 0xFF00 1226 #define ISPHIST_WB_GAIN_WG03_SHIFT 0 1227 #define ISPHIST_WB_GAIN_WG03_MASK 0xFF 1228 1229 #define ISPHIST_REG_START_END_MASK 0x3FFF 1230 #define ISPHIST_REG_START_SHIFT 16 1231 #define ISPHIST_REG_END_SHIFT 0 1232 #define ISPHIST_REG_START_MASK (ISPHIST_REG_START_END_MASK << \ 1233 ISPHIST_REG_START_SHIFT) 1234 #define ISPHIST_REG_END_MASK (ISPHIST_REG_START_END_MASK << \ 1235 ISPHIST_REG_END_SHIFT) 1236 1237 #define ISPHIST_REG_MASK (ISPHIST_REG_START_MASK | \ 1238 ISPHIST_REG_END_MASK) 1239 1240 #define ISPHIST_ADDR_SHIFT 0 1241 #define ISPHIST_ADDR_MASK 0x3FF 1242 1243 #define ISPHIST_DATA_SHIFT 0 1244 #define ISPHIST_DATA_MASK 0xFFFFF 1245 1246 #define ISPHIST_RADD_SHIFT 0 1247 #define ISPHIST_RADD_MASK 0xFFFFFFFF 1248 1249 #define ISPHIST_RADD_OFF_SHIFT 0 1250 #define ISPHIST_RADD_OFF_MASK 0xFFFF 1251 1252 #define ISPHIST_HV_INFO_HSIZE_SHIFT 16 1253 #define ISPHIST_HV_INFO_HSIZE_MASK 0x3FFF0000 1254 #define ISPHIST_HV_INFO_VSIZE_SHIFT 0 1255 #define ISPHIST_HV_INFO_VSIZE_MASK 0x3FFF 1256 1257 #define ISPHIST_HV_INFO_MASK 0x3FFF3FFF 1258 1259 #define ISPCCDC_LSC_ENABLE 1 1260 #define ISPCCDC_LSC_BUSY (1 << 7) 1261 #define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700 1262 #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8 1263 #define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800 1264 #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12 1265 #define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE 1266 #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1 1267 #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK (1<<6) 1268 1269 #define ISPCCDC_LSC_INITIAL_X_MASK 0x3F 1270 #define ISPCCDC_LSC_INITIAL_X_SHIFT 0 1271 #define ISPCCDC_LSC_INITIAL_Y_MASK 0x3F0000 1272 #define ISPCCDC_LSC_INITIAL_Y_SHIFT 16 1273 1274 /* ----------------------------------------------------------------------------- 1275 * CSI2 receiver registers (ES2.0) 1276 */ 1277 1278 #define ISPCSI2_REVISION (0x000) 1279 #define ISPCSI2_SYSCONFIG (0x010) 1280 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12 1281 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK \ 1282 (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) 1283 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE \ 1284 (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) 1285 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO \ 1286 (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) 1287 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \ 1288 (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) 1289 #define ISPCSI2_SYSCONFIG_SOFT_RESET (1 << 1) 1290 #define ISPCSI2_SYSCONFIG_AUTO_IDLE (1 << 0) 1291 1292 #define ISPCSI2_SYSSTATUS (0x014) 1293 #define ISPCSI2_SYSSTATUS_RESET_DONE (1 << 0) 1294 1295 #define ISPCSI2_IRQSTATUS (0x018) 1296 #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ (1 << 14) 1297 #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ (1 << 13) 1298 #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 12) 1299 #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11) 1300 #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ (1 << 10) 1301 #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ (1 << 9) 1302 #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ (1 << 8) 1303 #define ISPCSI2_IRQSTATUS_CONTEXT(n) (1 << (n)) 1304 1305 #define ISPCSI2_IRQENABLE (0x01c) 1306 #define ISPCSI2_CTRL (0x040) 1307 #define ISPCSI2_CTRL_VP_CLK_EN (1 << 15) 1308 #define ISPCSI2_CTRL_VP_ONLY_EN (1 << 11) 1309 #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8 1310 #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK \ 1311 (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT) 1312 #define ISPCSI2_CTRL_DBG_EN (1 << 7) 1313 #define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5 1314 #define ISPCSI2_CTRL_BURST_SIZE_MASK \ 1315 (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT) 1316 #define ISPCSI2_CTRL_FRAME (1 << 3) 1317 #define ISPCSI2_CTRL_ECC_EN (1 << 2) 1318 #define ISPCSI2_CTRL_SECURE (1 << 1) 1319 #define ISPCSI2_CTRL_IF_EN (1 << 0) 1320 1321 #define ISPCSI2_DBG_H (0x044) 1322 #define ISPCSI2_GNQ (0x048) 1323 #define ISPCSI2_PHY_CFG (0x050) 1324 #define ISPCSI2_PHY_CFG_RESET_CTRL (1 << 30) 1325 #define ISPCSI2_PHY_CFG_RESET_DONE (1 << 29) 1326 #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT 27 1327 #define ISPCSI2_PHY_CFG_PWR_CMD_MASK \ 1328 (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) 1329 #define ISPCSI2_PHY_CFG_PWR_CMD_OFF \ 1330 (0x0 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) 1331 #define ISPCSI2_PHY_CFG_PWR_CMD_ON \ 1332 (0x1 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) 1333 #define ISPCSI2_PHY_CFG_PWR_CMD_ULPW \ 1334 (0x2 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) 1335 #define ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT 25 1336 #define ISPCSI2_PHY_CFG_PWR_STATUS_MASK \ 1337 (0x3 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) 1338 #define ISPCSI2_PHY_CFG_PWR_STATUS_OFF \ 1339 (0x0 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) 1340 #define ISPCSI2_PHY_CFG_PWR_STATUS_ON \ 1341 (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) 1342 #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW \ 1343 (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) 1344 #define ISPCSI2_PHY_CFG_PWR_AUTO (1 << 24) 1345 1346 #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) (3 + ((n) * 4)) 1347 #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) \ 1348 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n)) 1349 #define ISPCSI2_PHY_CFG_DATA_POL_PN(n) \ 1350 (0x0 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n)) 1351 #define ISPCSI2_PHY_CFG_DATA_POL_NP(n) \ 1352 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n)) 1353 1354 #define ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n) ((n) * 4) 1355 #define ISPCSI2_PHY_CFG_DATA_POSITION_MASK(n) \ 1356 (0x7 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) 1357 #define ISPCSI2_PHY_CFG_DATA_POSITION_NC(n) \ 1358 (0x0 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) 1359 #define ISPCSI2_PHY_CFG_DATA_POSITION_1(n) \ 1360 (0x1 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) 1361 #define ISPCSI2_PHY_CFG_DATA_POSITION_2(n) \ 1362 (0x2 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) 1363 #define ISPCSI2_PHY_CFG_DATA_POSITION_3(n) \ 1364 (0x3 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) 1365 #define ISPCSI2_PHY_CFG_DATA_POSITION_4(n) \ 1366 (0x4 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) 1367 #define ISPCSI2_PHY_CFG_DATA_POSITION_5(n) \ 1368 (0x5 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) 1369 1370 #define ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT 3 1371 #define ISPCSI2_PHY_CFG_CLOCK_POL_MASK \ 1372 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT) 1373 #define ISPCSI2_PHY_CFG_CLOCK_POL_PN \ 1374 (0x0 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT) 1375 #define ISPCSI2_PHY_CFG_CLOCK_POL_NP \ 1376 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT) 1377 1378 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT 0 1379 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK \ 1380 (0x7 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) 1381 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_1 \ 1382 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) 1383 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_2 \ 1384 (0x2 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) 1385 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_3 \ 1386 (0x3 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) 1387 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_4 \ 1388 (0x4 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) 1389 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_5 \ 1390 (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) 1391 1392 #define ISPCSI2_PHY_IRQSTATUS (0x054) 1393 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT (1 << 26) 1394 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER (1 << 25) 1395 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 (1 << 24) 1396 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 (1 << 23) 1397 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 (1 << 22) 1398 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 (1 << 21) 1399 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 (1 << 20) 1400 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 (1 << 19) 1401 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 (1 << 18) 1402 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 (1 << 17) 1403 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 (1 << 16) 1404 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 (1 << 15) 1405 #define ISPCSI2_PHY_IRQSTATUS_ERRESC5 (1 << 14) 1406 #define ISPCSI2_PHY_IRQSTATUS_ERRESC4 (1 << 13) 1407 #define ISPCSI2_PHY_IRQSTATUS_ERRESC3 (1 << 12) 1408 #define ISPCSI2_PHY_IRQSTATUS_ERRESC2 (1 << 11) 1409 #define ISPCSI2_PHY_IRQSTATUS_ERRESC1 (1 << 10) 1410 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 (1 << 9) 1411 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 (1 << 8) 1412 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 (1 << 7) 1413 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 (1 << 6) 1414 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 (1 << 5) 1415 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 (1 << 4) 1416 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 (1 << 3) 1417 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 (1 << 2) 1418 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 (1 << 1) 1419 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 1 1420 1421 #define ISPCSI2_SHORT_PACKET (0x05c) 1422 #define ISPCSI2_PHY_IRQENABLE (0x060) 1423 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT (1 << 26) 1424 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER (1 << 25) 1425 #define ISPCSI2_PHY_IRQENABLE_STATEULPM5 (1 << 24) 1426 #define ISPCSI2_PHY_IRQENABLE_STATEULPM4 (1 << 23) 1427 #define ISPCSI2_PHY_IRQENABLE_STATEULPM3 (1 << 22) 1428 #define ISPCSI2_PHY_IRQENABLE_STATEULPM2 (1 << 21) 1429 #define ISPCSI2_PHY_IRQENABLE_STATEULPM1 (1 << 20) 1430 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 (1 << 19) 1431 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 (1 << 18) 1432 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 (1 << 17) 1433 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 (1 << 16) 1434 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 (1 << 15) 1435 #define ISPCSI2_PHY_IRQENABLE_ERRESC5 (1 << 14) 1436 #define ISPCSI2_PHY_IRQENABLE_ERRESC4 (1 << 13) 1437 #define ISPCSI2_PHY_IRQENABLE_ERRESC3 (1 << 12) 1438 #define ISPCSI2_PHY_IRQENABLE_ERRESC2 (1 << 11) 1439 #define ISPCSI2_PHY_IRQENABLE_ERRESC1 (1 << 10) 1440 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 (1 << 9) 1441 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 (1 << 8) 1442 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 (1 << 7) 1443 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 (1 << 6) 1444 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 (1 << 5) 1445 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 (1 << 4) 1446 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 (1 << 3) 1447 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 (1 << 2) 1448 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 (1 << 1) 1449 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 (1 << 0) 1450 1451 #define ISPCSI2_DBG_P (0x068) 1452 #define ISPCSI2_TIMING (0x06c) 1453 #define ISPCSI2_TIMING_FORCE_RX_MODE_IO(n) (1 << ((16 * ((n) - 1)) + 15)) 1454 #define ISPCSI2_TIMING_STOP_STATE_X16_IO(n) (1 << ((16 * ((n) - 1)) + 14)) 1455 #define ISPCSI2_TIMING_STOP_STATE_X4_IO(n) (1 << ((16 * ((n) - 1)) + 13)) 1456 #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n) (16 * ((n) - 1)) 1457 #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(n) \ 1458 (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n)) 1459 1460 #define ISPCSI2_CTX_CTRL1(n) ((0x070) + 0x20 * (n)) 1461 #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8 1462 #define ISPCSI2_CTX_CTRL1_COUNT_MASK \ 1463 (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT) 1464 #define ISPCSI2_CTX_CTRL1_EOF_EN (1 << 7) 1465 #define ISPCSI2_CTX_CTRL1_EOL_EN (1 << 6) 1466 #define ISPCSI2_CTX_CTRL1_CS_EN (1 << 5) 1467 #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK (1 << 4) 1468 #define ISPCSI2_CTX_CTRL1_PING_PONG (1 << 3) 1469 #define ISPCSI2_CTX_CTRL1_CTX_EN (1 << 0) 1470 1471 #define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n)) 1472 #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13 1473 #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK \ 1474 (0x3 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT) 1475 #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11 1476 #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \ 1477 (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT) 1478 #define ISPCSI2_CTX_CTRL2_DPCM_PRED (1 << 10) 1479 #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0 1480 #define ISPCSI2_CTX_CTRL2_FORMAT_MASK \ 1481 (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT) 1482 #define ISPCSI2_CTX_CTRL2_FRAME_SHIFT 16 1483 #define ISPCSI2_CTX_CTRL2_FRAME_MASK \ 1484 (0xffff << ISPCSI2_CTX_CTRL2_FRAME_SHIFT) 1485 1486 #define ISPCSI2_CTX_DAT_OFST(n) ((0x078) + 0x20 * (n)) 1487 #define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT 0 1488 #define ISPCSI2_CTX_DAT_OFST_OFST_MASK \ 1489 (0x1ffe0 << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT) 1490 1491 #define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n)) 1492 #define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n)) 1493 #define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n)) 1494 #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ (1 << 8) 1495 #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ (1 << 7) 1496 #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ (1 << 6) 1497 #define ISPCSI2_CTX_IRQENABLE_CS_IRQ (1 << 5) 1498 #define ISPCSI2_CTX_IRQENABLE_LE_IRQ (1 << 3) 1499 #define ISPCSI2_CTX_IRQENABLE_LS_IRQ (1 << 2) 1500 #define ISPCSI2_CTX_IRQENABLE_FE_IRQ (1 << 1) 1501 #define ISPCSI2_CTX_IRQENABLE_FS_IRQ (1 << 0) 1502 1503 #define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n)) 1504 #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 8) 1505 #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ (1 << 7) 1506 #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ (1 << 6) 1507 #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ (1 << 5) 1508 #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ (1 << 3) 1509 #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ (1 << 2) 1510 #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ (1 << 1) 1511 #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ (1 << 0) 1512 1513 #define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n)) 1514 #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5 1515 #define ISPCSI2_CTX_CTRL3_ALPHA_MASK \ 1516 (0x3fff << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT) 1517 1518 /* This instance is for OMAP3630 only */ 1519 #define ISPCSI2_CTX_TRANSCODEH(n) (0x000 + 0x8 * (n)) 1520 #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT 16 1521 #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_MASK \ 1522 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT) 1523 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT 0 1524 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_MASK \ 1525 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT) 1526 #define ISPCSI2_CTX_TRANSCODEV(n) (0x004 + 0x8 * (n)) 1527 #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT 16 1528 #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_MASK \ 1529 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT) 1530 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT 0 1531 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_MASK \ 1532 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT) 1533 1534 /* ----------------------------------------------------------------------------- 1535 * CSI PHY registers 1536 */ 1537 1538 #define ISPCSIPHY_REG0 (0x000) 1539 #define ISPCSIPHY_REG0_THS_TERM_SHIFT 8 1540 #define ISPCSIPHY_REG0_THS_TERM_MASK \ 1541 (0xff << ISPCSIPHY_REG0_THS_TERM_SHIFT) 1542 #define ISPCSIPHY_REG0_THS_SETTLE_SHIFT 0 1543 #define ISPCSIPHY_REG0_THS_SETTLE_MASK \ 1544 (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT) 1545 1546 #define ISPCSIPHY_REG1 (0x004) 1547 #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK (1 << 29) 1548 /* This field is for OMAP3630 only */ 1549 #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS (1 << 25) 1550 #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT 18 1551 #define ISPCSIPHY_REG1_TCLK_TERM_MASK \ 1552 (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT) 1553 #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_SHIFT 10 1554 #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_MASK \ 1555 (0xff << ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN) 1556 /* This field is for OMAP3430 only */ 1557 #define ISPCSIPHY_REG1_TCLK_MISS_SHIFT 8 1558 #define ISPCSIPHY_REG1_TCLK_MISS_MASK \ 1559 (0x3 << ISPCSIPHY_REG1_TCLK_MISS_SHIFT) 1560 /* This field is for OMAP3630 only */ 1561 #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT 8 1562 #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_MASK \ 1563 (0x3 << ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT) 1564 #define ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT 0 1565 #define ISPCSIPHY_REG1_TCLK_SETTLE_MASK \ 1566 (0xff << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT) 1567 1568 /* This register is for OMAP3630 only */ 1569 #define ISPCSIPHY_REG2 (0x008) 1570 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT 30 1571 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK \ 1572 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT) 1573 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT 28 1574 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK \ 1575 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT) 1576 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT 26 1577 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK \ 1578 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT) 1579 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT 24 1580 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK \ 1581 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT) 1582 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT 0 1583 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_MASK \ 1584 (0x7fffff << ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT) 1585 1586 #endif /* OMAP3_ISP_REG_H */ 1587