1 /*
2 * Common prep/pmac/chrp boot and setup code.
3 */
4
5 #include <linux/module.h>
6 #include <linux/string.h>
7 #include <linux/sched.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/reboot.h>
11 #include <linux/delay.h>
12 #include <linux/initrd.h>
13 #include <linux/tty.h>
14 #include <linux/bootmem.h>
15 #include <linux/seq_file.h>
16 #include <linux/root_dev.h>
17 #include <linux/cpu.h>
18 #include <linux/console.h>
19 #include <linux/memblock.h>
20
21 #include <asm/io.h>
22 #include <asm/prom.h>
23 #include <asm/processor.h>
24 #include <asm/pgtable.h>
25 #include <asm/setup.h>
26 #include <asm/smp.h>
27 #include <asm/elf.h>
28 #include <asm/cputable.h>
29 #include <asm/bootx.h>
30 #include <asm/btext.h>
31 #include <asm/machdep.h>
32 #include <asm/uaccess.h>
33 #include <asm/pmac_feature.h>
34 #include <asm/sections.h>
35 #include <asm/nvram.h>
36 #include <asm/xmon.h>
37 #include <asm/time.h>
38 #include <asm/serial.h>
39 #include <asm/udbg.h>
40 #include <asm/mmu_context.h>
41
42 #include "setup.h"
43
44 #define DBG(fmt...)
45
46 extern void bootx_init(unsigned long r4, unsigned long phys);
47
48 int boot_cpuid = -1;
49 EXPORT_SYMBOL_GPL(boot_cpuid);
50 int boot_cpuid_phys;
51 EXPORT_SYMBOL_GPL(boot_cpuid_phys);
52
53 int smp_hw_index[NR_CPUS];
54
55 unsigned long ISA_DMA_THRESHOLD;
56 unsigned int DMA_MODE_READ;
57 unsigned int DMA_MODE_WRITE;
58
59 #ifdef CONFIG_VGA_CONSOLE
60 unsigned long vgacon_remap_base;
61 EXPORT_SYMBOL(vgacon_remap_base);
62 #endif
63
64 /*
65 * These are used in binfmt_elf.c to put aux entries on the stack
66 * for each elf executable being started.
67 */
68 int dcache_bsize;
69 int icache_bsize;
70 int ucache_bsize;
71
72 /*
73 * We're called here very early in the boot. We determine the machine
74 * type and call the appropriate low-level setup functions.
75 * -- Cort <cort@fsmlabs.com>
76 *
77 * Note that the kernel may be running at an address which is different
78 * from the address that it was linked at, so we must use RELOC/PTRRELOC
79 * to access static data (including strings). -- paulus
80 */
early_init(unsigned long dt_ptr)81 notrace unsigned long __init early_init(unsigned long dt_ptr)
82 {
83 unsigned long offset = reloc_offset();
84 struct cpu_spec *spec;
85
86 /* First zero the BSS -- use memset_io, some platforms don't have
87 * caches on yet */
88 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
89 __bss_stop - __bss_start);
90
91 /*
92 * Identify the CPU type and fix up code sections
93 * that depend on which cpu we have.
94 */
95 spec = identify_cpu(offset, mfspr(SPRN_PVR));
96
97 do_feature_fixups(spec->cpu_features,
98 PTRRELOC(&__start___ftr_fixup),
99 PTRRELOC(&__stop___ftr_fixup));
100
101 do_feature_fixups(spec->mmu_features,
102 PTRRELOC(&__start___mmu_ftr_fixup),
103 PTRRELOC(&__stop___mmu_ftr_fixup));
104
105 do_lwsync_fixups(spec->cpu_features,
106 PTRRELOC(&__start___lwsync_fixup),
107 PTRRELOC(&__stop___lwsync_fixup));
108
109 do_final_fixups();
110
111 return KERNELBASE + offset;
112 }
113
114
115 /*
116 * Find out what kind of machine we're on and save any data we need
117 * from the early boot process (devtree is copied on pmac by prom_init()).
118 * This is called very early on the boot process, after a minimal
119 * MMU environment has been set up but before MMU_init is called.
120 */
machine_init(u64 dt_ptr)121 notrace void __init machine_init(u64 dt_ptr)
122 {
123 lockdep_init();
124
125 /* Enable early debugging if any specified (see udbg.h) */
126 udbg_early_init();
127
128 /* Do some early initialization based on the flat device tree */
129 early_init_devtree(__va(dt_ptr));
130
131 early_init_mmu();
132
133 probe_machine();
134
135 setup_kdump_trampoline();
136
137 #ifdef CONFIG_6xx
138 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
139 cpu_has_feature(CPU_FTR_CAN_NAP))
140 ppc_md.power_save = ppc6xx_idle;
141 #endif
142
143 #ifdef CONFIG_E500
144 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
145 cpu_has_feature(CPU_FTR_CAN_NAP))
146 ppc_md.power_save = e500_idle;
147 #endif
148 if (ppc_md.progress)
149 ppc_md.progress("id mach(): done", 0x200);
150 }
151
152 #ifdef CONFIG_BOOKE_WDT
153 extern u32 booke_wdt_enabled;
154 extern u32 booke_wdt_period;
155
156 /* Checks wdt=x and wdt_period=xx command-line option */
early_parse_wdt(char * p)157 notrace int __init early_parse_wdt(char *p)
158 {
159 if (p && strncmp(p, "0", 1) != 0)
160 booke_wdt_enabled = 1;
161
162 return 0;
163 }
164 early_param("wdt", early_parse_wdt);
165
early_parse_wdt_period(char * p)166 int __init early_parse_wdt_period (char *p)
167 {
168 if (p)
169 booke_wdt_period = simple_strtoul(p, NULL, 0);
170
171 return 0;
172 }
173 early_param("wdt_period", early_parse_wdt_period);
174 #endif /* CONFIG_BOOKE_WDT */
175
176 /* Checks "l2cr=xxxx" command-line option */
ppc_setup_l2cr(char * str)177 int __init ppc_setup_l2cr(char *str)
178 {
179 if (cpu_has_feature(CPU_FTR_L2CR)) {
180 unsigned long val = simple_strtoul(str, NULL, 0);
181 printk(KERN_INFO "l2cr set to %lx\n", val);
182 _set_L2CR(0); /* force invalidate by disable cache */
183 _set_L2CR(val); /* and enable it */
184 }
185 return 1;
186 }
187 __setup("l2cr=", ppc_setup_l2cr);
188
189 /* Checks "l3cr=xxxx" command-line option */
ppc_setup_l3cr(char * str)190 int __init ppc_setup_l3cr(char *str)
191 {
192 if (cpu_has_feature(CPU_FTR_L3CR)) {
193 unsigned long val = simple_strtoul(str, NULL, 0);
194 printk(KERN_INFO "l3cr set to %lx\n", val);
195 _set_L3CR(val); /* and enable it */
196 }
197 return 1;
198 }
199 __setup("l3cr=", ppc_setup_l3cr);
200
201 #ifdef CONFIG_GENERIC_NVRAM
202
203 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
nvram_read_byte(int addr)204 unsigned char nvram_read_byte(int addr)
205 {
206 if (ppc_md.nvram_read_val)
207 return ppc_md.nvram_read_val(addr);
208 return 0xff;
209 }
210 EXPORT_SYMBOL(nvram_read_byte);
211
nvram_write_byte(unsigned char val,int addr)212 void nvram_write_byte(unsigned char val, int addr)
213 {
214 if (ppc_md.nvram_write_val)
215 ppc_md.nvram_write_val(addr, val);
216 }
217 EXPORT_SYMBOL(nvram_write_byte);
218
nvram_get_size(void)219 ssize_t nvram_get_size(void)
220 {
221 if (ppc_md.nvram_size)
222 return ppc_md.nvram_size();
223 return -1;
224 }
225 EXPORT_SYMBOL(nvram_get_size);
226
nvram_sync(void)227 void nvram_sync(void)
228 {
229 if (ppc_md.nvram_sync)
230 ppc_md.nvram_sync();
231 }
232 EXPORT_SYMBOL(nvram_sync);
233
234 #endif /* CONFIG_NVRAM */
235
ppc_init(void)236 int __init ppc_init(void)
237 {
238 /* clear the progress line */
239 if (ppc_md.progress)
240 ppc_md.progress(" ", 0xffff);
241
242 /* call platform init */
243 if (ppc_md.init != NULL) {
244 ppc_md.init();
245 }
246 return 0;
247 }
248
249 arch_initcall(ppc_init);
250
irqstack_early_init(void)251 static void __init irqstack_early_init(void)
252 {
253 unsigned int i;
254
255 /* interrupt stacks must be in lowmem, we get that for free on ppc32
256 * as the memblock is limited to lowmem by default */
257 for_each_possible_cpu(i) {
258 softirq_ctx[i] = (struct thread_info *)
259 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
260 hardirq_ctx[i] = (struct thread_info *)
261 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
262 }
263 }
264
265 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
exc_lvl_early_init(void)266 static void __init exc_lvl_early_init(void)
267 {
268 unsigned int i, hw_cpu;
269
270 /* interrupt stacks must be in lowmem, we get that for free on ppc32
271 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
272 for_each_possible_cpu(i) {
273 hw_cpu = get_hard_smp_processor_id(i);
274 critirq_ctx[hw_cpu] = (struct thread_info *)
275 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
276 #ifdef CONFIG_BOOKE
277 dbgirq_ctx[hw_cpu] = (struct thread_info *)
278 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
279 mcheckirq_ctx[hw_cpu] = (struct thread_info *)
280 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
281 #endif
282 }
283 }
284 #else
285 #define exc_lvl_early_init()
286 #endif
287
288 /* Warning, IO base is not yet inited */
setup_arch(char ** cmdline_p)289 void __init setup_arch(char **cmdline_p)
290 {
291 *cmdline_p = cmd_line;
292
293 /* so udelay does something sensible, assume <= 1000 bogomips */
294 loops_per_jiffy = 500000000 / HZ;
295
296 unflatten_device_tree();
297 check_for_initrd();
298
299 if (ppc_md.init_early)
300 ppc_md.init_early();
301
302 find_legacy_serial_ports();
303
304 smp_setup_cpu_maps();
305
306 /* Register early console */
307 register_early_udbg_console();
308
309 xmon_setup();
310
311 /*
312 * Set cache line size based on type of cpu as a default.
313 * Systems with OF can look in the properties on the cpu node(s)
314 * for a possibly more accurate value.
315 */
316 dcache_bsize = cur_cpu_spec->dcache_bsize;
317 icache_bsize = cur_cpu_spec->icache_bsize;
318 ucache_bsize = 0;
319 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
320 ucache_bsize = icache_bsize = dcache_bsize;
321
322 /* reboot on panic */
323 panic_timeout = 180;
324
325 if (ppc_md.panic)
326 setup_panic();
327
328 init_mm.start_code = (unsigned long)_stext;
329 init_mm.end_code = (unsigned long) _etext;
330 init_mm.end_data = (unsigned long) _edata;
331 init_mm.brk = klimit;
332
333 exc_lvl_early_init();
334
335 irqstack_early_init();
336
337 /* set up the bootmem stuff with available memory */
338 do_init_bootmem();
339 if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
340
341 #ifdef CONFIG_DUMMY_CONSOLE
342 conswitchp = &dummy_con;
343 #endif
344
345 if (ppc_md.setup_arch)
346 ppc_md.setup_arch();
347 if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
348
349 paging_init();
350
351 /* Initialize the MMU context management stuff */
352 mmu_context_init();
353
354 }
355