1 /*
2 * ohci1394.h - driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Gord Peters <GordPeters@smarttech.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #ifndef _OHCI1394_H
22 #define _OHCI1394_H
23
24 #include <asm/io.h>
25
26 #include "ieee1394_types.h"
27 #include <asm/io.h>
28
29 #define OHCI1394_DRIVER_NAME "ohci1394"
30
31 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
32 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
33 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
34 #define OHCI1394_MAX_SELF_ID_ERRORS 16
35
36 #define AR_REQ_NUM_DESC 4 /* number of AR req descriptors */
37 #define AR_REQ_BUF_SIZE PAGE_SIZE /* size of AR req buffers */
38 #define AR_REQ_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
39
40 #define AR_RESP_NUM_DESC 4 /* number of AR resp descriptors */
41 #define AR_RESP_BUF_SIZE PAGE_SIZE /* size of AR resp buffers */
42 #define AR_RESP_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
43
44 #define IR_NUM_DESC 16 /* number of IR descriptors */
45 #define IR_BUF_SIZE PAGE_SIZE /* 4096 bytes/buffer */
46 #define IR_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
47
48 #define IT_NUM_DESC 16 /* number of IT descriptors */
49
50 #define AT_REQ_NUM_DESC 32 /* number of AT req descriptors */
51 #define AT_RESP_NUM_DESC 32 /* number of AT resp descriptors */
52
53 #define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */
54
55 #define OHCI_CONFIG_ROM_LEN 1024 /* Length of the mapped configrom space */
56
57 #define OHCI1394_SI_DMA_BUF_SIZE 8192 /* length of the selfid buffer */
58
59 /* PCI configuration space addresses */
60 #define OHCI1394_PCI_HCI_Control 0x40
61
62 struct dma_cmd {
63 u32 control;
64 u32 address;
65 u32 branchAddress;
66 u32 status;
67 };
68
69 /*
70 * FIXME:
71 * It is important that a single at_dma_prg does not cross a page boundary
72 * The proper way to do it would be to do the check dynamically as the
73 * programs are inserted into the AT fifo.
74 */
75 struct at_dma_prg {
76 struct dma_cmd begin;
77 quadlet_t data[4];
78 struct dma_cmd end;
79 quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
80 };
81
82 /* identify whether a DMA context is asynchronous or isochronous */
83 enum context_type { DMA_CTX_ASYNC_REQ, DMA_CTX_ASYNC_RESP, DMA_CTX_ISO };
84
85 /* DMA receive context */
86 struct dma_rcv_ctx {
87 struct ti_ohci *ohci;
88 enum context_type type;
89 int ctx;
90 unsigned int num_desc;
91
92 unsigned int buf_size;
93 unsigned int split_buf_size;
94
95 /* dma block descriptors */
96 struct dma_cmd **prg_cpu;
97 dma_addr_t *prg_bus;
98 struct pci_pool *prg_pool;
99
100 /* dma buffers */
101 quadlet_t **buf_cpu;
102 dma_addr_t *buf_bus;
103
104 unsigned int buf_ind;
105 unsigned int buf_offset;
106 quadlet_t *spb;
107 spinlock_t lock;
108 struct tasklet_struct task;
109 int ctrlClear;
110 int ctrlSet;
111 int cmdPtr;
112 int ctxtMatch;
113 };
114
115 /* DMA transmit context */
116 struct dma_trm_ctx {
117 struct ti_ohci *ohci;
118 enum context_type type;
119 int ctx;
120 unsigned int num_desc;
121
122 /* dma block descriptors */
123 struct at_dma_prg **prg_cpu;
124 dma_addr_t *prg_bus;
125 struct pci_pool *prg_pool;
126
127 unsigned int prg_ind;
128 unsigned int sent_ind;
129 int free_prgs;
130 quadlet_t *branchAddrPtr;
131
132 /* list of packets inserted in the AT FIFO */
133 struct list_head fifo_list;
134
135 /* list of pending packets to be inserted in the AT FIFO */
136 struct list_head pending_list;
137
138 spinlock_t lock;
139 struct tasklet_struct task;
140 int ctrlClear;
141 int ctrlSet;
142 int cmdPtr;
143 };
144
145 struct ohci1394_iso_tasklet {
146 struct tasklet_struct tasklet;
147 struct list_head link;
148 int context;
149 enum { OHCI_ISO_TRANSMIT, OHCI_ISO_RECEIVE,
150 OHCI_ISO_MULTICHANNEL_RECEIVE } type;
151 };
152
153 struct ti_ohci {
154 int id; /* sequential card number */
155
156 struct pci_dev *dev;
157
158 enum {
159 OHCI_INIT_ALLOC_HOST,
160 OHCI_INIT_HAVE_MEM_REGION,
161 OHCI_INIT_HAVE_IOMAPPING,
162 OHCI_INIT_HAVE_CONFIG_ROM_BUFFER,
163 OHCI_INIT_HAVE_SELFID_BUFFER,
164 OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE,
165 OHCI_INIT_HAVE_IRQ,
166 OHCI_INIT_DONE,
167 } init_state;
168
169 /* remapped memory spaces */
170 void *registers;
171
172 /* dma buffer for self-id packets */
173 quadlet_t *selfid_buf_cpu;
174 dma_addr_t selfid_buf_bus;
175
176 /* buffer for csr config rom */
177 quadlet_t *csr_config_rom_cpu;
178 dma_addr_t csr_config_rom_bus;
179 int csr_config_rom_length;
180
181 unsigned int max_packet_size;
182
183 /* async receive */
184 struct dma_rcv_ctx ar_resp_context;
185 struct dma_rcv_ctx ar_req_context;
186
187 /* async transmit */
188 struct dma_trm_ctx at_resp_context;
189 struct dma_trm_ctx at_req_context;
190
191 /* iso receive */
192 int nb_iso_rcv_ctx;
193 unsigned long ir_ctx_usage; /* use test_and_set_bit() for atomicity */
194 unsigned long ir_multichannel_used; /* ditto */
195 spinlock_t IR_channel_lock;
196
197 /* iso receive (legacy API) */
198 u64 ir_legacy_channels; /* note: this differs from ISO_channel_usage;
199 it only accounts for channels listened to
200 by the legacy API, so that we can know when
201 it is safe to free the legacy API context */
202
203 struct dma_rcv_ctx ir_legacy_context;
204 struct ohci1394_iso_tasklet ir_legacy_tasklet;
205
206 /* iso transmit */
207 int nb_iso_xmit_ctx;
208 unsigned long it_ctx_usage; /* use test_and_set_bit() for atomicity */
209
210 /* iso transmit (legacy API) */
211 struct dma_trm_ctx it_legacy_context;
212 struct ohci1394_iso_tasklet it_legacy_tasklet;
213
214 u64 ISO_channel_usage;
215
216 /* IEEE-1394 part follows */
217 struct hpsb_host *host;
218
219 int phyid, isroot;
220
221 spinlock_t phy_reg_lock;
222 spinlock_t event_lock;
223
224 int self_id_errors;
225
226 /* Tasklets for iso receive and transmit, used by video1394,
227 * amdtp and dv1394 */
228
229 struct list_head iso_tasklet_list;
230 spinlock_t iso_tasklet_list_lock;
231
232 /* Swap the selfid buffer? */
233 unsigned int selfid_swap:1;
234 /* Some Apple chipset seem to swap incoming headers for us */
235 unsigned int no_swap_incoming:1;
236
237 /* Force extra paranoia checking on bus-reset handling */
238 unsigned int check_busreset:1;
239 };
240
cross_bound(unsigned long addr,unsigned int size)241 static inline int cross_bound(unsigned long addr, unsigned int size)
242 {
243 int cross=0;
244 if (size>PAGE_SIZE) {
245 cross = size/PAGE_SIZE;
246 size -= cross*PAGE_SIZE;
247 }
248 if ((PAGE_SIZE-addr%PAGE_SIZE)<size)
249 cross++;
250 return cross;
251 }
252
253 /*
254 * Register read and write helper functions.
255 */
reg_write(const struct ti_ohci * ohci,int offset,u32 data)256 static inline void reg_write(const struct ti_ohci *ohci, int offset, u32 data)
257 {
258 writel(data, ohci->registers + offset);
259 }
260
reg_read(const struct ti_ohci * ohci,int offset)261 static inline u32 reg_read(const struct ti_ohci *ohci, int offset)
262 {
263 return readl(ohci->registers + offset);
264 }
265
266
267 /* 2 KiloBytes of register space */
268 #define OHCI1394_REGISTER_SIZE 0x800
269
270 /* Offsets relative to context bases defined below */
271
272 #define OHCI1394_ContextControlSet 0x000
273 #define OHCI1394_ContextControlClear 0x004
274 #define OHCI1394_ContextCommandPtr 0x00C
275
276 /* register map */
277 #define OHCI1394_Version 0x000
278 #define OHCI1394_GUID_ROM 0x004
279 #define OHCI1394_ATRetries 0x008
280 #define OHCI1394_CSRData 0x00C
281 #define OHCI1394_CSRCompareData 0x010
282 #define OHCI1394_CSRControl 0x014
283 #define OHCI1394_ConfigROMhdr 0x018
284 #define OHCI1394_BusID 0x01C
285 #define OHCI1394_BusOptions 0x020
286 #define OHCI1394_GUIDHi 0x024
287 #define OHCI1394_GUIDLo 0x028
288 #define OHCI1394_ConfigROMmap 0x034
289 #define OHCI1394_PostedWriteAddressLo 0x038
290 #define OHCI1394_PostedWriteAddressHi 0x03C
291 #define OHCI1394_VendorID 0x040
292 #define OHCI1394_HCControlSet 0x050
293 #define OHCI1394_HCControlClear 0x054
294 #define OHCI1394_HCControl_noByteSwap 0x40000000
295 #define OHCI1394_HCControl_programPhyEnable 0x00800000
296 #define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000
297 #define OHCI1394_HCControl_LPS 0x00080000
298 #define OHCI1394_HCControl_postedWriteEnable 0x00040000
299 #define OHCI1394_HCControl_linkEnable 0x00020000
300 #define OHCI1394_HCControl_softReset 0x00010000
301 #define OHCI1394_SelfIDBuffer 0x064
302 #define OHCI1394_SelfIDCount 0x068
303 #define OHCI1394_IRMultiChanMaskHiSet 0x070
304 #define OHCI1394_IRMultiChanMaskHiClear 0x074
305 #define OHCI1394_IRMultiChanMaskLoSet 0x078
306 #define OHCI1394_IRMultiChanMaskLoClear 0x07C
307 #define OHCI1394_IntEventSet 0x080
308 #define OHCI1394_IntEventClear 0x084
309 #define OHCI1394_IntMaskSet 0x088
310 #define OHCI1394_IntMaskClear 0x08C
311 #define OHCI1394_IsoXmitIntEventSet 0x090
312 #define OHCI1394_IsoXmitIntEventClear 0x094
313 #define OHCI1394_IsoXmitIntMaskSet 0x098
314 #define OHCI1394_IsoXmitIntMaskClear 0x09C
315 #define OHCI1394_IsoRecvIntEventSet 0x0A0
316 #define OHCI1394_IsoRecvIntEventClear 0x0A4
317 #define OHCI1394_IsoRecvIntMaskSet 0x0A8
318 #define OHCI1394_IsoRecvIntMaskClear 0x0AC
319 #define OHCI1394_InitialBandwidthAvailable 0x0B0
320 #define OHCI1394_InitialChannelsAvailableHi 0x0B4
321 #define OHCI1394_InitialChannelsAvailableLo 0x0B8
322 #define OHCI1394_FairnessControl 0x0DC
323 #define OHCI1394_LinkControlSet 0x0E0
324 #define OHCI1394_LinkControlClear 0x0E4
325 #define OHCI1394_NodeID 0x0E8
326 #define OHCI1394_PhyControl 0x0EC
327 #define OHCI1394_IsochronousCycleTimer 0x0F0
328 #define OHCI1394_AsReqFilterHiSet 0x100
329 #define OHCI1394_AsReqFilterHiClear 0x104
330 #define OHCI1394_AsReqFilterLoSet 0x108
331 #define OHCI1394_AsReqFilterLoClear 0x10C
332 #define OHCI1394_PhyReqFilterHiSet 0x110
333 #define OHCI1394_PhyReqFilterHiClear 0x114
334 #define OHCI1394_PhyReqFilterLoSet 0x118
335 #define OHCI1394_PhyReqFilterLoClear 0x11C
336 #define OHCI1394_PhyUpperBound 0x120
337
338 #define OHCI1394_AsReqTrContextBase 0x180
339 #define OHCI1394_AsReqTrContextControlSet 0x180
340 #define OHCI1394_AsReqTrContextControlClear 0x184
341 #define OHCI1394_AsReqTrCommandPtr 0x18C
342
343 #define OHCI1394_AsRspTrContextBase 0x1A0
344 #define OHCI1394_AsRspTrContextControlSet 0x1A0
345 #define OHCI1394_AsRspTrContextControlClear 0x1A4
346 #define OHCI1394_AsRspTrCommandPtr 0x1AC
347
348 #define OHCI1394_AsReqRcvContextBase 0x1C0
349 #define OHCI1394_AsReqRcvContextControlSet 0x1C0
350 #define OHCI1394_AsReqRcvContextControlClear 0x1C4
351 #define OHCI1394_AsReqRcvCommandPtr 0x1CC
352
353 #define OHCI1394_AsRspRcvContextBase 0x1E0
354 #define OHCI1394_AsRspRcvContextControlSet 0x1E0
355 #define OHCI1394_AsRspRcvContextControlClear 0x1E4
356 #define OHCI1394_AsRspRcvCommandPtr 0x1EC
357
358 /* Isochronous transmit registers */
359 /* Add (16 * n) for context n */
360 #define OHCI1394_IsoXmitContextBase 0x200
361 #define OHCI1394_IsoXmitContextControlSet 0x200
362 #define OHCI1394_IsoXmitContextControlClear 0x204
363 #define OHCI1394_IsoXmitCommandPtr 0x20C
364
365 /* Isochronous receive registers */
366 /* Add (32 * n) for context n */
367 #define OHCI1394_IsoRcvContextBase 0x400
368 #define OHCI1394_IsoRcvContextControlSet 0x400
369 #define OHCI1394_IsoRcvContextControlClear 0x404
370 #define OHCI1394_IsoRcvCommandPtr 0x40C
371 #define OHCI1394_IsoRcvContextMatch 0x410
372
373 /* Interrupts Mask/Events */
374
375 #define OHCI1394_reqTxComplete 0x00000001
376 #define OHCI1394_respTxComplete 0x00000002
377 #define OHCI1394_ARRQ 0x00000004
378 #define OHCI1394_ARRS 0x00000008
379 #define OHCI1394_RQPkt 0x00000010
380 #define OHCI1394_RSPkt 0x00000020
381 #define OHCI1394_isochTx 0x00000040
382 #define OHCI1394_isochRx 0x00000080
383 #define OHCI1394_postedWriteErr 0x00000100
384 #define OHCI1394_lockRespErr 0x00000200
385 #define OHCI1394_selfIDComplete 0x00010000
386 #define OHCI1394_busReset 0x00020000
387 #define OHCI1394_phy 0x00080000
388 #define OHCI1394_cycleSynch 0x00100000
389 #define OHCI1394_cycle64Seconds 0x00200000
390 #define OHCI1394_cycleLost 0x00400000
391 #define OHCI1394_cycleInconsistent 0x00800000
392 #define OHCI1394_unrecoverableError 0x01000000
393 #define OHCI1394_cycleTooLong 0x02000000
394 #define OHCI1394_phyRegRcvd 0x04000000
395 #define OHCI1394_masterIntEnable 0x80000000
396
397 /* DMA Control flags */
398 #define DMA_CTL_OUTPUT_MORE 0x00000000
399 #define DMA_CTL_OUTPUT_LAST 0x10000000
400 #define DMA_CTL_INPUT_MORE 0x20000000
401 #define DMA_CTL_INPUT_LAST 0x30000000
402 #define DMA_CTL_UPDATE 0x08000000
403 #define DMA_CTL_IMMEDIATE 0x02000000
404 #define DMA_CTL_IRQ 0x00300000
405 #define DMA_CTL_BRANCH 0x000c0000
406 #define DMA_CTL_WAIT 0x00030000
407
408 /* OHCI evt_* error types, table 3-2 of the OHCI 1.1 spec. */
409 #define EVT_NO_STATUS 0x0 /* No event status */
410 #define EVT_RESERVED_A 0x1 /* Reserved, not used !!! */
411 #define EVT_LONG_PACKET 0x2 /* The revc data was longer than the buf */
412 #define EVT_MISSING_ACK 0x3 /* A subaction gap was detected before an ack
413 arrived, or recv'd ack had a parity error */
414 #define EVT_UNDERRUN 0x4 /* Underrun on corresponding FIFO, packet
415 truncated */
416 #define EVT_OVERRUN 0x5 /* A recv FIFO overflowed on reception of ISO
417 packet */
418 #define EVT_DESCRIPTOR_READ 0x6 /* An unrecoverable error occurred while host was
419 reading a descriptor block */
420 #define EVT_DATA_READ 0x7 /* An error occurred while host controller was
421 attempting to read from host memory in the data
422 stage of descriptor processing */
423 #define EVT_DATA_WRITE 0x8 /* An error occurred while host controller was
424 attempting to write either during the data stage
425 of descriptor processing, or when processing a single
426 16-bit host memory write */
427 #define EVT_BUS_RESET 0x9 /* Identifies a PHY packet in the recv buffer as
428 being a synthesized bus reset packet */
429 #define EVT_TIMEOUT 0xa /* Indicates that the asynchronous transmit response
430 packet expired and was not transmitted, or that an
431 IT DMA context experienced a skip processing overflow */
432 #define EVT_TCODE_ERR 0xb /* A bad tCode is associated with this packet.
433 The packet was flushed */
434 #define EVT_RESERVED_B 0xc /* Reserved, not used !!! */
435 #define EVT_RESERVED_C 0xd /* Reserved, not used !!! */
436 #define EVT_UNKNOWN 0xe /* An error condition has occurred that cannot be
437 represented by any other event codes defined herein. */
438 #define EVT_FLUSHED 0xf /* Send by the link side of output FIFO when asynchronous
439 packets are being flushed due to a bus reset. */
440
441 #define OHCI1394_TCODE_PHY 0xE
442
443 void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet,
444 int type,
445 void (*func)(unsigned long),
446 unsigned long data);
447 int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
448 struct ohci1394_iso_tasklet *tasklet);
449 void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
450 struct ohci1394_iso_tasklet *tasklet);
451
452 /* returns zero if successful, one if DMA context is locked up */
453 int ohci1394_stop_context (struct ti_ohci *ohci, int reg, char *msg);
454 struct ti_ohci *ohci1394_get_struct(int card_num);
455
456 #endif
457