1 #ifndef _LINUX_IRQ_H
2 #define _LINUX_IRQ_H
3 
4 /*
5  * Please do not include this file in generic code.  There is currently
6  * no requirement for any architecture to implement anything held
7  * within this file.
8  *
9  * Thanks. --rmk
10  */
11 
12 #include <linux/smp.h>
13 
14 #ifndef CONFIG_S390
15 
16 #include <linux/linkage.h>
17 #include <linux/cache.h>
18 #include <linux/spinlock.h>
19 #include <linux/cpumask.h>
20 #include <linux/gfp.h>
21 #include <linux/irqreturn.h>
22 #include <linux/irqnr.h>
23 #include <linux/errno.h>
24 #include <linux/topology.h>
25 #include <linux/wait.h>
26 
27 #include <asm/irq.h>
28 #include <asm/ptrace.h>
29 #include <asm/irq_regs.h>
30 
31 struct seq_file;
32 struct module;
33 struct irq_desc;
34 struct irq_data;
35 typedef	void (*irq_flow_handler_t)(unsigned int irq,
36 					    struct irq_desc *desc);
37 typedef	void (*irq_preflow_handler_t)(struct irq_data *data);
38 
39 /*
40  * IRQ line status.
41  *
42  * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
43  *
44  * IRQ_TYPE_NONE		- default, unspecified type
45  * IRQ_TYPE_EDGE_RISING		- rising edge triggered
46  * IRQ_TYPE_EDGE_FALLING	- falling edge triggered
47  * IRQ_TYPE_EDGE_BOTH		- rising and falling edge triggered
48  * IRQ_TYPE_LEVEL_HIGH		- high level triggered
49  * IRQ_TYPE_LEVEL_LOW		- low level triggered
50  * IRQ_TYPE_LEVEL_MASK		- Mask to filter out the level bits
51  * IRQ_TYPE_SENSE_MASK		- Mask for all the above bits
52  * IRQ_TYPE_DEFAULT		- For use by some PICs to ask irq_set_type
53  *				  to setup the HW to a sane default (used
54  *                                by irqdomain map() callbacks to synchronize
55  *                                the HW state and SW flags for a newly
56  *                                allocated descriptor).
57  *
58  * IRQ_TYPE_PROBE		- Special flag for probing in progress
59  *
60  * Bits which can be modified via irq_set/clear/modify_status_flags()
61  * IRQ_LEVEL			- Interrupt is level type. Will be also
62  *				  updated in the code when the above trigger
63  *				  bits are modified via irq_set_irq_type()
64  * IRQ_PER_CPU			- Mark an interrupt PER_CPU. Will protect
65  *				  it from affinity setting
66  * IRQ_NOPROBE			- Interrupt cannot be probed by autoprobing
67  * IRQ_NOREQUEST		- Interrupt cannot be requested via
68  *				  request_irq()
69  * IRQ_NOTHREAD			- Interrupt cannot be threaded
70  * IRQ_NOAUTOEN			- Interrupt is not automatically enabled in
71  *				  request/setup_irq()
72  * IRQ_NO_BALANCING		- Interrupt cannot be balanced (affinity set)
73  * IRQ_MOVE_PCNTXT		- Interrupt can be migrated from process context
74  * IRQ_NESTED_TRHEAD		- Interrupt nests into another thread
75  * IRQ_PER_CPU_DEVID		- Dev_id is a per-cpu variable
76  */
77 enum {
78 	IRQ_TYPE_NONE		= 0x00000000,
79 	IRQ_TYPE_EDGE_RISING	= 0x00000001,
80 	IRQ_TYPE_EDGE_FALLING	= 0x00000002,
81 	IRQ_TYPE_EDGE_BOTH	= (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
82 	IRQ_TYPE_LEVEL_HIGH	= 0x00000004,
83 	IRQ_TYPE_LEVEL_LOW	= 0x00000008,
84 	IRQ_TYPE_LEVEL_MASK	= (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
85 	IRQ_TYPE_SENSE_MASK	= 0x0000000f,
86 	IRQ_TYPE_DEFAULT	= IRQ_TYPE_SENSE_MASK,
87 
88 	IRQ_TYPE_PROBE		= 0x00000010,
89 
90 	IRQ_LEVEL		= (1 <<  8),
91 	IRQ_PER_CPU		= (1 <<  9),
92 	IRQ_NOPROBE		= (1 << 10),
93 	IRQ_NOREQUEST		= (1 << 11),
94 	IRQ_NOAUTOEN		= (1 << 12),
95 	IRQ_NO_BALANCING	= (1 << 13),
96 	IRQ_MOVE_PCNTXT		= (1 << 14),
97 	IRQ_NESTED_THREAD	= (1 << 15),
98 	IRQ_NOTHREAD		= (1 << 16),
99 	IRQ_PER_CPU_DEVID	= (1 << 17),
100 };
101 
102 #define IRQF_MODIFY_MASK	\
103 	(IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
104 	 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
105 	 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID)
106 
107 #define IRQ_NO_BALANCING_MASK	(IRQ_PER_CPU | IRQ_NO_BALANCING)
108 
109 /*
110  * Return value for chip->irq_set_affinity()
111  *
112  * IRQ_SET_MASK_OK	- OK, core updates irq_data.affinity
113  * IRQ_SET_MASK_NOCPY	- OK, chip did update irq_data.affinity
114  */
115 enum {
116 	IRQ_SET_MASK_OK = 0,
117 	IRQ_SET_MASK_OK_NOCOPY,
118 };
119 
120 struct msi_desc;
121 struct irq_domain;
122 
123 /**
124  * struct irq_data - per irq and irq chip data passed down to chip functions
125  * @irq:		interrupt number
126  * @hwirq:		hardware interrupt number, local to the interrupt domain
127  * @node:		node index useful for balancing
128  * @state_use_accessors: status information for irq chip functions.
129  *			Use accessor functions to deal with it
130  * @chip:		low level interrupt hardware access
131  * @domain:		Interrupt translation domain; responsible for mapping
132  *			between hwirq number and linux irq number.
133  * @handler_data:	per-IRQ data for the irq_chip methods
134  * @chip_data:		platform-specific per-chip private data for the chip
135  *			methods, to allow shared chip implementations
136  * @msi_desc:		MSI descriptor
137  * @affinity:		IRQ affinity on SMP
138  *
139  * The fields here need to overlay the ones in irq_desc until we
140  * cleaned up the direct references and switched everything over to
141  * irq_data.
142  */
143 struct irq_data {
144 	unsigned int		irq;
145 	unsigned long		hwirq;
146 	unsigned int		node;
147 	unsigned int		state_use_accessors;
148 	struct irq_chip		*chip;
149 	struct irq_domain	*domain;
150 	void			*handler_data;
151 	void			*chip_data;
152 	struct msi_desc		*msi_desc;
153 #ifdef CONFIG_SMP
154 	cpumask_var_t		affinity;
155 #endif
156 };
157 
158 /*
159  * Bit masks for irq_data.state
160  *
161  * IRQD_TRIGGER_MASK		- Mask for the trigger type bits
162  * IRQD_SETAFFINITY_PENDING	- Affinity setting is pending
163  * IRQD_NO_BALANCING		- Balancing disabled for this IRQ
164  * IRQD_PER_CPU			- Interrupt is per cpu
165  * IRQD_AFFINITY_SET		- Interrupt affinity was set
166  * IRQD_LEVEL			- Interrupt is level triggered
167  * IRQD_WAKEUP_STATE		- Interrupt is configured for wakeup
168  *				  from suspend
169  * IRDQ_MOVE_PCNTXT		- Interrupt can be moved in process
170  *				  context
171  * IRQD_IRQ_DISABLED		- Disabled state of the interrupt
172  * IRQD_IRQ_MASKED		- Masked state of the interrupt
173  * IRQD_IRQ_INPROGRESS		- In progress state of the interrupt
174  */
175 enum {
176 	IRQD_TRIGGER_MASK		= 0xf,
177 	IRQD_SETAFFINITY_PENDING	= (1 <<  8),
178 	IRQD_NO_BALANCING		= (1 << 10),
179 	IRQD_PER_CPU			= (1 << 11),
180 	IRQD_AFFINITY_SET		= (1 << 12),
181 	IRQD_LEVEL			= (1 << 13),
182 	IRQD_WAKEUP_STATE		= (1 << 14),
183 	IRQD_MOVE_PCNTXT		= (1 << 15),
184 	IRQD_IRQ_DISABLED		= (1 << 16),
185 	IRQD_IRQ_MASKED			= (1 << 17),
186 	IRQD_IRQ_INPROGRESS		= (1 << 18),
187 };
188 
irqd_is_setaffinity_pending(struct irq_data * d)189 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
190 {
191 	return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
192 }
193 
irqd_is_per_cpu(struct irq_data * d)194 static inline bool irqd_is_per_cpu(struct irq_data *d)
195 {
196 	return d->state_use_accessors & IRQD_PER_CPU;
197 }
198 
irqd_can_balance(struct irq_data * d)199 static inline bool irqd_can_balance(struct irq_data *d)
200 {
201 	return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
202 }
203 
irqd_affinity_was_set(struct irq_data * d)204 static inline bool irqd_affinity_was_set(struct irq_data *d)
205 {
206 	return d->state_use_accessors & IRQD_AFFINITY_SET;
207 }
208 
irqd_mark_affinity_was_set(struct irq_data * d)209 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
210 {
211 	d->state_use_accessors |= IRQD_AFFINITY_SET;
212 }
213 
irqd_get_trigger_type(struct irq_data * d)214 static inline u32 irqd_get_trigger_type(struct irq_data *d)
215 {
216 	return d->state_use_accessors & IRQD_TRIGGER_MASK;
217 }
218 
219 /*
220  * Must only be called inside irq_chip.irq_set_type() functions.
221  */
irqd_set_trigger_type(struct irq_data * d,u32 type)222 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
223 {
224 	d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
225 	d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
226 }
227 
irqd_is_level_type(struct irq_data * d)228 static inline bool irqd_is_level_type(struct irq_data *d)
229 {
230 	return d->state_use_accessors & IRQD_LEVEL;
231 }
232 
irqd_is_wakeup_set(struct irq_data * d)233 static inline bool irqd_is_wakeup_set(struct irq_data *d)
234 {
235 	return d->state_use_accessors & IRQD_WAKEUP_STATE;
236 }
237 
irqd_can_move_in_process_context(struct irq_data * d)238 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
239 {
240 	return d->state_use_accessors & IRQD_MOVE_PCNTXT;
241 }
242 
irqd_irq_disabled(struct irq_data * d)243 static inline bool irqd_irq_disabled(struct irq_data *d)
244 {
245 	return d->state_use_accessors & IRQD_IRQ_DISABLED;
246 }
247 
irqd_irq_masked(struct irq_data * d)248 static inline bool irqd_irq_masked(struct irq_data *d)
249 {
250 	return d->state_use_accessors & IRQD_IRQ_MASKED;
251 }
252 
irqd_irq_inprogress(struct irq_data * d)253 static inline bool irqd_irq_inprogress(struct irq_data *d)
254 {
255 	return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
256 }
257 
258 /*
259  * Functions for chained handlers which can be enabled/disabled by the
260  * standard disable_irq/enable_irq calls. Must be called with
261  * irq_desc->lock held.
262  */
irqd_set_chained_irq_inprogress(struct irq_data * d)263 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
264 {
265 	d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
266 }
267 
irqd_clr_chained_irq_inprogress(struct irq_data * d)268 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
269 {
270 	d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
271 }
272 
irqd_to_hwirq(struct irq_data * d)273 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
274 {
275 	return d->hwirq;
276 }
277 
278 /**
279  * struct irq_chip - hardware interrupt chip descriptor
280  *
281  * @name:		name for /proc/interrupts
282  * @irq_startup:	start up the interrupt (defaults to ->enable if NULL)
283  * @irq_shutdown:	shut down the interrupt (defaults to ->disable if NULL)
284  * @irq_enable:		enable the interrupt (defaults to chip->unmask if NULL)
285  * @irq_disable:	disable the interrupt
286  * @irq_ack:		start of a new interrupt
287  * @irq_mask:		mask an interrupt source
288  * @irq_mask_ack:	ack and mask an interrupt source
289  * @irq_unmask:		unmask an interrupt source
290  * @irq_eoi:		end of interrupt
291  * @irq_set_affinity:	set the CPU affinity on SMP machines
292  * @irq_retrigger:	resend an IRQ to the CPU
293  * @irq_set_type:	set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
294  * @irq_set_wake:	enable/disable power-management wake-on of an IRQ
295  * @irq_bus_lock:	function to lock access to slow bus (i2c) chips
296  * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
297  * @irq_cpu_online:	configure an interrupt source for a secondary CPU
298  * @irq_cpu_offline:	un-configure an interrupt source for a secondary CPU
299  * @irq_suspend:	function called from core code on suspend once per chip
300  * @irq_resume:		function called from core code on resume once per chip
301  * @irq_pm_shutdown:	function called from core code on shutdown once per chip
302  * @irq_print_chip:	optional to print special chip info in show_interrupts
303  * @flags:		chip specific flags
304  *
305  * @release:		release function solely used by UML
306  */
307 struct irq_chip {
308 	const char	*name;
309 	unsigned int	(*irq_startup)(struct irq_data *data);
310 	void		(*irq_shutdown)(struct irq_data *data);
311 	void		(*irq_enable)(struct irq_data *data);
312 	void		(*irq_disable)(struct irq_data *data);
313 
314 	void		(*irq_ack)(struct irq_data *data);
315 	void		(*irq_mask)(struct irq_data *data);
316 	void		(*irq_mask_ack)(struct irq_data *data);
317 	void		(*irq_unmask)(struct irq_data *data);
318 	void		(*irq_eoi)(struct irq_data *data);
319 
320 	int		(*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
321 	int		(*irq_retrigger)(struct irq_data *data);
322 	int		(*irq_set_type)(struct irq_data *data, unsigned int flow_type);
323 	int		(*irq_set_wake)(struct irq_data *data, unsigned int on);
324 
325 	void		(*irq_bus_lock)(struct irq_data *data);
326 	void		(*irq_bus_sync_unlock)(struct irq_data *data);
327 
328 	void		(*irq_cpu_online)(struct irq_data *data);
329 	void		(*irq_cpu_offline)(struct irq_data *data);
330 
331 	void		(*irq_suspend)(struct irq_data *data);
332 	void		(*irq_resume)(struct irq_data *data);
333 	void		(*irq_pm_shutdown)(struct irq_data *data);
334 
335 	void		(*irq_print_chip)(struct irq_data *data, struct seq_file *p);
336 
337 	unsigned long	flags;
338 
339 	/* Currently used only by UML, might disappear one day.*/
340 #ifdef CONFIG_IRQ_RELEASE_METHOD
341 	void		(*release)(unsigned int irq, void *dev_id);
342 #endif
343 };
344 
345 /*
346  * irq_chip specific flags
347  *
348  * IRQCHIP_SET_TYPE_MASKED:	Mask before calling chip.irq_set_type()
349  * IRQCHIP_EOI_IF_HANDLED:	Only issue irq_eoi() when irq was handled
350  * IRQCHIP_MASK_ON_SUSPEND:	Mask non wake irqs in the suspend path
351  * IRQCHIP_ONOFFLINE_ENABLED:	Only call irq_on/off_line callbacks
352  *				when irq enabled
353  * IRQCHIP_SKIP_SET_WAKE:	Skip chip.irq_set_wake(), for this irq chip
354  */
355 enum {
356 	IRQCHIP_SET_TYPE_MASKED		= (1 <<  0),
357 	IRQCHIP_EOI_IF_HANDLED		= (1 <<  1),
358 	IRQCHIP_MASK_ON_SUSPEND		= (1 <<  2),
359 	IRQCHIP_ONOFFLINE_ENABLED	= (1 <<  3),
360 	IRQCHIP_SKIP_SET_WAKE		= (1 <<  4),
361 };
362 
363 /* This include will go away once we isolated irq_desc usage to core code */
364 #include <linux/irqdesc.h>
365 
366 /*
367  * Pick up the arch-dependent methods:
368  */
369 #include <asm/hw_irq.h>
370 
371 #ifndef NR_IRQS_LEGACY
372 # define NR_IRQS_LEGACY 0
373 #endif
374 
375 #ifndef ARCH_IRQ_INIT_FLAGS
376 # define ARCH_IRQ_INIT_FLAGS	0
377 #endif
378 
379 #define IRQ_DEFAULT_INIT_FLAGS	ARCH_IRQ_INIT_FLAGS
380 
381 struct irqaction;
382 extern int setup_irq(unsigned int irq, struct irqaction *new);
383 extern void remove_irq(unsigned int irq, struct irqaction *act);
384 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
385 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
386 
387 extern void irq_cpu_online(void);
388 extern void irq_cpu_offline(void);
389 extern int __irq_set_affinity_locked(struct irq_data *data,  const struct cpumask *cpumask);
390 
391 #ifdef CONFIG_GENERIC_HARDIRQS
392 
393 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
394 void irq_move_irq(struct irq_data *data);
395 void irq_move_masked_irq(struct irq_data *data);
396 #else
irq_move_irq(struct irq_data * data)397 static inline void irq_move_irq(struct irq_data *data) { }
irq_move_masked_irq(struct irq_data * data)398 static inline void irq_move_masked_irq(struct irq_data *data) { }
399 #endif
400 
401 extern int no_irq_affinity;
402 
403 /*
404  * Built-in IRQ handlers for various IRQ types,
405  * callable via desc->handle_irq()
406  */
407 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
408 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
409 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
410 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
411 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
412 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
413 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
414 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
415 extern void handle_nested_irq(unsigned int irq);
416 
417 /* Handling of unhandled and spurious interrupts: */
418 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
419 			   irqreturn_t action_ret);
420 
421 
422 /* Enable/disable irq debugging output: */
423 extern int noirqdebug_setup(char *str);
424 
425 /* Checks whether the interrupt can be requested by request_irq(): */
426 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
427 
428 /* Dummy irq-chip implementations: */
429 extern struct irq_chip no_irq_chip;
430 extern struct irq_chip dummy_irq_chip;
431 
432 extern void
433 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
434 			      irq_flow_handler_t handle, const char *name);
435 
irq_set_chip_and_handler(unsigned int irq,struct irq_chip * chip,irq_flow_handler_t handle)436 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
437 					    irq_flow_handler_t handle)
438 {
439 	irq_set_chip_and_handler_name(irq, chip, handle, NULL);
440 }
441 
442 extern int irq_set_percpu_devid(unsigned int irq);
443 
444 extern void
445 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
446 		  const char *name);
447 
448 static inline void
irq_set_handler(unsigned int irq,irq_flow_handler_t handle)449 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
450 {
451 	__irq_set_handler(irq, handle, 0, NULL);
452 }
453 
454 /*
455  * Set a highlevel chained flow handler for a given IRQ.
456  * (a chained handler is automatically enabled and set to
457  *  IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
458  */
459 static inline void
irq_set_chained_handler(unsigned int irq,irq_flow_handler_t handle)460 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
461 {
462 	__irq_set_handler(irq, handle, 1, NULL);
463 }
464 
465 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
466 
irq_set_status_flags(unsigned int irq,unsigned long set)467 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
468 {
469 	irq_modify_status(irq, 0, set);
470 }
471 
irq_clear_status_flags(unsigned int irq,unsigned long clr)472 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
473 {
474 	irq_modify_status(irq, clr, 0);
475 }
476 
irq_set_noprobe(unsigned int irq)477 static inline void irq_set_noprobe(unsigned int irq)
478 {
479 	irq_modify_status(irq, 0, IRQ_NOPROBE);
480 }
481 
irq_set_probe(unsigned int irq)482 static inline void irq_set_probe(unsigned int irq)
483 {
484 	irq_modify_status(irq, IRQ_NOPROBE, 0);
485 }
486 
irq_set_nothread(unsigned int irq)487 static inline void irq_set_nothread(unsigned int irq)
488 {
489 	irq_modify_status(irq, 0, IRQ_NOTHREAD);
490 }
491 
irq_set_thread(unsigned int irq)492 static inline void irq_set_thread(unsigned int irq)
493 {
494 	irq_modify_status(irq, IRQ_NOTHREAD, 0);
495 }
496 
irq_set_nested_thread(unsigned int irq,bool nest)497 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
498 {
499 	if (nest)
500 		irq_set_status_flags(irq, IRQ_NESTED_THREAD);
501 	else
502 		irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
503 }
504 
irq_set_percpu_devid_flags(unsigned int irq)505 static inline void irq_set_percpu_devid_flags(unsigned int irq)
506 {
507 	irq_set_status_flags(irq,
508 			     IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
509 			     IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
510 }
511 
512 /* Handle dynamic irq creation and destruction */
513 extern unsigned int create_irq_nr(unsigned int irq_want, int node);
514 extern int create_irq(void);
515 extern void destroy_irq(unsigned int irq);
516 
517 /*
518  * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and
519  * irq_free_desc instead.
520  */
521 extern void dynamic_irq_cleanup(unsigned int irq);
dynamic_irq_init(unsigned int irq)522 static inline void dynamic_irq_init(unsigned int irq)
523 {
524 	dynamic_irq_cleanup(irq);
525 }
526 
527 /* Set/get chip/data for an IRQ: */
528 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
529 extern int irq_set_handler_data(unsigned int irq, void *data);
530 extern int irq_set_chip_data(unsigned int irq, void *data);
531 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
532 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
533 extern struct irq_data *irq_get_irq_data(unsigned int irq);
534 
irq_get_chip(unsigned int irq)535 static inline struct irq_chip *irq_get_chip(unsigned int irq)
536 {
537 	struct irq_data *d = irq_get_irq_data(irq);
538 	return d ? d->chip : NULL;
539 }
540 
irq_data_get_irq_chip(struct irq_data * d)541 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
542 {
543 	return d->chip;
544 }
545 
irq_get_chip_data(unsigned int irq)546 static inline void *irq_get_chip_data(unsigned int irq)
547 {
548 	struct irq_data *d = irq_get_irq_data(irq);
549 	return d ? d->chip_data : NULL;
550 }
551 
irq_data_get_irq_chip_data(struct irq_data * d)552 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
553 {
554 	return d->chip_data;
555 }
556 
irq_get_handler_data(unsigned int irq)557 static inline void *irq_get_handler_data(unsigned int irq)
558 {
559 	struct irq_data *d = irq_get_irq_data(irq);
560 	return d ? d->handler_data : NULL;
561 }
562 
irq_data_get_irq_handler_data(struct irq_data * d)563 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
564 {
565 	return d->handler_data;
566 }
567 
irq_get_msi_desc(unsigned int irq)568 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
569 {
570 	struct irq_data *d = irq_get_irq_data(irq);
571 	return d ? d->msi_desc : NULL;
572 }
573 
irq_data_get_msi(struct irq_data * d)574 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
575 {
576 	return d->msi_desc;
577 }
578 
579 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
580 		struct module *owner);
581 
582 /* use macros to avoid needing export.h for THIS_MODULE */
583 #define irq_alloc_descs(irq, from, cnt, node)	\
584 	__irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
585 
586 #define irq_alloc_desc(node)			\
587 	irq_alloc_descs(-1, 0, 1, node)
588 
589 #define irq_alloc_desc_at(at, node)		\
590 	irq_alloc_descs(at, at, 1, node)
591 
592 #define irq_alloc_desc_from(from, node)		\
593 	irq_alloc_descs(-1, from, 1, node)
594 
595 void irq_free_descs(unsigned int irq, unsigned int cnt);
596 int irq_reserve_irqs(unsigned int from, unsigned int cnt);
597 
irq_free_desc(unsigned int irq)598 static inline void irq_free_desc(unsigned int irq)
599 {
600 	irq_free_descs(irq, 1);
601 }
602 
irq_reserve_irq(unsigned int irq)603 static inline int irq_reserve_irq(unsigned int irq)
604 {
605 	return irq_reserve_irqs(irq, 1);
606 }
607 
608 #ifndef irq_reg_writel
609 # define irq_reg_writel(val, addr)	writel(val, addr)
610 #endif
611 #ifndef irq_reg_readl
612 # define irq_reg_readl(addr)		readl(addr)
613 #endif
614 
615 /**
616  * struct irq_chip_regs - register offsets for struct irq_gci
617  * @enable:	Enable register offset to reg_base
618  * @disable:	Disable register offset to reg_base
619  * @mask:	Mask register offset to reg_base
620  * @ack:	Ack register offset to reg_base
621  * @eoi:	Eoi register offset to reg_base
622  * @type:	Type configuration register offset to reg_base
623  * @polarity:	Polarity configuration register offset to reg_base
624  */
625 struct irq_chip_regs {
626 	unsigned long		enable;
627 	unsigned long		disable;
628 	unsigned long		mask;
629 	unsigned long		ack;
630 	unsigned long		eoi;
631 	unsigned long		type;
632 	unsigned long		polarity;
633 };
634 
635 /**
636  * struct irq_chip_type - Generic interrupt chip instance for a flow type
637  * @chip:		The real interrupt chip which provides the callbacks
638  * @regs:		Register offsets for this chip
639  * @handler:		Flow handler associated with this chip
640  * @type:		Chip can handle these flow types
641  *
642  * A irq_generic_chip can have several instances of irq_chip_type when
643  * it requires different functions and register offsets for different
644  * flow types.
645  */
646 struct irq_chip_type {
647 	struct irq_chip		chip;
648 	struct irq_chip_regs	regs;
649 	irq_flow_handler_t	handler;
650 	u32			type;
651 };
652 
653 /**
654  * struct irq_chip_generic - Generic irq chip data structure
655  * @lock:		Lock to protect register and cache data access
656  * @reg_base:		Register base address (virtual)
657  * @irq_base:		Interrupt base nr for this chip
658  * @irq_cnt:		Number of interrupts handled by this chip
659  * @mask_cache:		Cached mask register
660  * @type_cache:		Cached type register
661  * @polarity_cache:	Cached polarity register
662  * @wake_enabled:	Interrupt can wakeup from suspend
663  * @wake_active:	Interrupt is marked as an wakeup from suspend source
664  * @num_ct:		Number of available irq_chip_type instances (usually 1)
665  * @private:		Private data for non generic chip callbacks
666  * @list:		List head for keeping track of instances
667  * @chip_types:		Array of interrupt irq_chip_types
668  *
669  * Note, that irq_chip_generic can have multiple irq_chip_type
670  * implementations which can be associated to a particular irq line of
671  * an irq_chip_generic instance. That allows to share and protect
672  * state in an irq_chip_generic instance when we need to implement
673  * different flow mechanisms (level/edge) for it.
674  */
675 struct irq_chip_generic {
676 	raw_spinlock_t		lock;
677 	void __iomem		*reg_base;
678 	unsigned int		irq_base;
679 	unsigned int		irq_cnt;
680 	u32			mask_cache;
681 	u32			type_cache;
682 	u32			polarity_cache;
683 	u32			wake_enabled;
684 	u32			wake_active;
685 	unsigned int		num_ct;
686 	void			*private;
687 	struct list_head	list;
688 	struct irq_chip_type	chip_types[0];
689 };
690 
691 /**
692  * enum irq_gc_flags - Initialization flags for generic irq chips
693  * @IRQ_GC_INIT_MASK_CACHE:	Initialize the mask_cache by reading mask reg
694  * @IRQ_GC_INIT_NESTED_LOCK:	Set the lock class of the irqs to nested for
695  *				irq chips which need to call irq_set_wake() on
696  *				the parent irq. Usually GPIO implementations
697  */
698 enum irq_gc_flags {
699 	IRQ_GC_INIT_MASK_CACHE		= 1 << 0,
700 	IRQ_GC_INIT_NESTED_LOCK		= 1 << 1,
701 };
702 
703 /* Generic chip callback functions */
704 void irq_gc_noop(struct irq_data *d);
705 void irq_gc_mask_disable_reg(struct irq_data *d);
706 void irq_gc_mask_set_bit(struct irq_data *d);
707 void irq_gc_mask_clr_bit(struct irq_data *d);
708 void irq_gc_unmask_enable_reg(struct irq_data *d);
709 void irq_gc_ack_set_bit(struct irq_data *d);
710 void irq_gc_ack_clr_bit(struct irq_data *d);
711 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
712 void irq_gc_eoi(struct irq_data *d);
713 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
714 
715 /* Setup functions for irq_chip_generic */
716 struct irq_chip_generic *
717 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
718 		       void __iomem *reg_base, irq_flow_handler_t handler);
719 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
720 			    enum irq_gc_flags flags, unsigned int clr,
721 			    unsigned int set);
722 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
723 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
724 			     unsigned int clr, unsigned int set);
725 
irq_data_get_chip_type(struct irq_data * d)726 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
727 {
728 	return container_of(d->chip, struct irq_chip_type, chip);
729 }
730 
731 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
732 
733 #ifdef CONFIG_SMP
irq_gc_lock(struct irq_chip_generic * gc)734 static inline void irq_gc_lock(struct irq_chip_generic *gc)
735 {
736 	raw_spin_lock(&gc->lock);
737 }
738 
irq_gc_unlock(struct irq_chip_generic * gc)739 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
740 {
741 	raw_spin_unlock(&gc->lock);
742 }
743 #else
irq_gc_lock(struct irq_chip_generic * gc)744 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
irq_gc_unlock(struct irq_chip_generic * gc)745 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
746 #endif
747 
748 #endif /* CONFIG_GENERIC_HARDIRQS */
749 
750 #endif /* !CONFIG_S390 */
751 
752 #endif /* _LINUX_IRQ_H */
753