1 #ifdef __KERNEL__
2 #ifndef _ASM_IRQ_H
3 #define _ASM_IRQ_H
4
5 #include <linux/config.h>
6 #include <asm/machdep.h> /* ppc_md */
7 #include <asm/atomic.h>
8
9 extern void disable_irq(unsigned int);
10 extern void disable_irq_nosync(unsigned int);
11 extern void enable_irq(unsigned int);
12
13 /*
14 * These constants are used for passing information about interrupt
15 * signal polarity and level/edge sensing to the low-level PIC chip
16 * drivers.
17 */
18 #define IRQ_SENSE_MASK 0x1
19 #define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
20 #define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
21
22 #define IRQ_POLARITY_MASK 0x2
23 #define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
24 #define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
25
26 #if defined(CONFIG_40x)
27 #include <asm/ibm4xx.h>
28
29 #ifndef NR_BOARD_IRQS
30 #define NR_BOARD_IRQS 0
31 #endif
32
33 #ifndef UIC_WIDTH /* Number of interrupts per device */
34 #define UIC_WIDTH 32
35 #endif
36
37 #ifndef NR_UICS /* number of UIC devices */
38 #define NR_UICS 1
39 #endif
40
41 #if defined (CONFIG_403)
42 /*
43 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
44 * 32 possible interrupts, a majority of which are not implemented on
45 * all cores. There are six configurable, external interrupt pins and
46 * there are eight internal interrupts for the on-chip serial port
47 * (SPU), DMA controller, and JTAG controller.
48 *
49 */
50
51 #define NR_AIC_IRQS 32
52 #define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
53
54 #elif !defined (CONFIG_403)
55
56 /*
57 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
58 * possible interrupts as well. There are seven, configurable external
59 * interrupt pins and there are 17 internal interrupts for the on-chip
60 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
61 *
62 */
63
64
65 #define NR_UIC_IRQS UIC_WIDTH
66 #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
67 #endif
68 static __inline__ int
irq_cannonicalize(int irq)69 irq_cannonicalize(int irq)
70 {
71 return (irq);
72 }
73
74 #elif defined(CONFIG_44x)
75 #include <asm/ibm44x.h>
76
77 #define NR_UIC_IRQS 32
78 #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
79
80 static __inline__ int
irq_cannonicalize(int irq)81 irq_cannonicalize(int irq)
82 {
83 return (irq);
84 }
85
86 #elif defined(CONFIG_8xx)
87
88 /* Now include the board configuration specific associations.
89 */
90 #include <asm/mpc8xx.h>
91
92 /* The MPC8xx cores have 16 possible interrupts. There are eight
93 * possible level sensitive interrupts assigned and generated internally
94 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
95 * There are eight external interrupts (IRQs) that can be configured
96 * as either level or edge sensitive.
97 *
98 * On some implementations, there is also the possibility of an 8259
99 * through the PCI and PCI-ISA bridges.
100 *
101 * We are "flattening" the interrupt vectors of the cascaded CPM
102 * and 8259 interrupt controllers so that we can uniquely identify
103 * any interrupt source with a single integer.
104 */
105 #define NR_SIU_INTS 16
106 #define NR_CPM_INTS 32
107 #ifndef NR_8259_INTS
108 #define NR_8259_INTS 0
109 #endif
110
111 #define SIU_IRQ_OFFSET 0
112 #define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
113 #define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
114
115 #define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
116
117 /* These values must be zero-based and map 1:1 with the SIU configuration.
118 * They are used throughout the 8xx I/O subsystem to generate
119 * interrupt masks, flags, and other control patterns. This is why the
120 * current kernel assumption of the 8259 as the base controller is such
121 * a pain in the butt.
122 */
123 #define SIU_IRQ0 (0) /* Highest priority */
124 #define SIU_LEVEL0 (1)
125 #define SIU_IRQ1 (2)
126 #define SIU_LEVEL1 (3)
127 #define SIU_IRQ2 (4)
128 #define SIU_LEVEL2 (5)
129 #define SIU_IRQ3 (6)
130 #define SIU_LEVEL3 (7)
131 #define SIU_IRQ4 (8)
132 #define SIU_LEVEL4 (9)
133 #define SIU_IRQ5 (10)
134 #define SIU_LEVEL5 (11)
135 #define SIU_IRQ6 (12)
136 #define SIU_LEVEL6 (13)
137 #define SIU_IRQ7 (14)
138 #define SIU_LEVEL7 (15)
139
140 /* The internal interrupts we can configure as we see fit.
141 * My personal preference is CPM at level 2, which puts it above the
142 * MBX PCI/ISA/IDE interrupts.
143 */
144 #ifndef PIT_INTERRUPT
145 #define PIT_INTERRUPT SIU_LEVEL0
146 #endif
147 #ifndef CPM_INTERRUPT
148 #define CPM_INTERRUPT SIU_LEVEL2
149 #endif
150 #ifndef PCMCIA_INTERRUPT
151 #define PCMCIA_INTERRUPT SIU_LEVEL6
152 #endif
153 #ifndef DEC_INTERRUPT
154 #define DEC_INTERRUPT SIU_LEVEL7
155 #endif
156
157 /* Some internal interrupt registers use an 8-bit mask for the interrupt
158 * level instead of a number.
159 */
160 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
161
162 /* always the same on 8xx -- Cort */
irq_cannonicalize(int irq)163 static __inline__ int irq_cannonicalize(int irq)
164 {
165 return irq;
166 }
167
168 #else /* CONFIG_40x + CONFIG_8xx */
169 /*
170 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
171 * so it is the max of them all
172 */
173 #define NR_IRQS 256
174
175 #ifndef CONFIG_8260
176
177 #define NUM_8259_INTERRUPTS 16
178
179 #else /* CONFIG_8260 */
180
181 /* The 8260 has an internal interrupt controller with a maximum of
182 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
183 * Don't be confused by the 8260 documentation where they list an
184 * "interrupt number" and "interrupt vector". We are only interested
185 * in the interrupt vector. There are "reserved" holes where the
186 * vector number increases, but the interrupt number in the table does not.
187 * (Document errata updates have fixed this...make sure you have up to
188 * date processor documentation -- Dan).
189 */
190 #define NR_SIU_INTS 64
191
192 #define SIU_INT_ERROR ((uint)0x00)
193 #define SIU_INT_I2C ((uint)0x01)
194 #define SIU_INT_SPI ((uint)0x02)
195 #define SIU_INT_RISC ((uint)0x03)
196 #define SIU_INT_SMC1 ((uint)0x04)
197 #define SIU_INT_SMC2 ((uint)0x05)
198 #define SIU_INT_IDMA1 ((uint)0x06)
199 #define SIU_INT_IDMA2 ((uint)0x07)
200 #define SIU_INT_IDMA3 ((uint)0x08)
201 #define SIU_INT_IDMA4 ((uint)0x09)
202 #define SIU_INT_SDMA ((uint)0x0a)
203 #define SIU_INT_TIMER1 ((uint)0x0c)
204 #define SIU_INT_TIMER2 ((uint)0x0d)
205 #define SIU_INT_TIMER3 ((uint)0x0e)
206 #define SIU_INT_TIMER4 ((uint)0x0f)
207 #define SIU_INT_TMCNT ((uint)0x10)
208 #define SIU_INT_PIT ((uint)0x11)
209 #define SIU_INT_IRQ1 ((uint)0x13)
210 #define SIU_INT_IRQ2 ((uint)0x14)
211 #define SIU_INT_IRQ3 ((uint)0x15)
212 #define SIU_INT_IRQ4 ((uint)0x16)
213 #define SIU_INT_IRQ5 ((uint)0x17)
214 #define SIU_INT_IRQ6 ((uint)0x18)
215 #define SIU_INT_IRQ7 ((uint)0x19)
216 #define SIU_INT_FCC1 ((uint)0x20)
217 #define SIU_INT_FCC2 ((uint)0x21)
218 #define SIU_INT_FCC3 ((uint)0x22)
219 #define SIU_INT_MCC1 ((uint)0x24)
220 #define SIU_INT_MCC2 ((uint)0x25)
221 #define SIU_INT_SCC1 ((uint)0x28)
222 #define SIU_INT_SCC2 ((uint)0x29)
223 #define SIU_INT_SCC3 ((uint)0x2a)
224 #define SIU_INT_SCC4 ((uint)0x2b)
225 #define SIU_INT_PC15 ((uint)0x30)
226 #define SIU_INT_PC14 ((uint)0x31)
227 #define SIU_INT_PC13 ((uint)0x32)
228 #define SIU_INT_PC12 ((uint)0x33)
229 #define SIU_INT_PC11 ((uint)0x34)
230 #define SIU_INT_PC10 ((uint)0x35)
231 #define SIU_INT_PC9 ((uint)0x36)
232 #define SIU_INT_PC8 ((uint)0x37)
233 #define SIU_INT_PC7 ((uint)0x38)
234 #define SIU_INT_PC6 ((uint)0x39)
235 #define SIU_INT_PC5 ((uint)0x3a)
236 #define SIU_INT_PC4 ((uint)0x3b)
237 #define SIU_INT_PC3 ((uint)0x3c)
238 #define SIU_INT_PC2 ((uint)0x3d)
239 #define SIU_INT_PC1 ((uint)0x3e)
240 #define SIU_INT_PC0 ((uint)0x3f)
241
242 #endif /* CONFIG_8260 */
243
244 /*
245 * This gets called from serial.c, which is now used on
246 * powermacs as well as prep/chrp boxes.
247 * Prep and chrp both have cascaded 8259 PICs.
248 */
irq_cannonicalize(int irq)249 static __inline__ int irq_cannonicalize(int irq)
250 {
251 if (ppc_md.irq_cannonicalize)
252 return ppc_md.irq_cannonicalize(irq);
253 return irq;
254 }
255
256 #endif
257
258 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
259 /* pedantic: these are long because they are used with set_bit --RR */
260 extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
261 extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
262 extern atomic_t ppc_n_lost_interrupts;
263
264 #endif /* _ASM_IRQ_H */
265 #endif /* __KERNEL__ */
266