1 #ifndef __ASM_SH64_IRQ_H 2 #define __ASM_SH64_IRQ_H 3 4 /* 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 * 9 * include/asm-sh64/irq.h 10 * 11 * Copyright (C) 2000, 2001 Paolo Alberelli 12 * 13 */ 14 15 #include <linux/config.h> 16 17 /* 18 * Encoded IRQs are not considered worth to be supported. 19 * Main reason is that there's no per-encoded-interrupt 20 * enable/disable mechanism (as there was in SH3/4). 21 * An all enabled/all disabled is worth only if there's 22 * a cascaded IC to disable/enable/ack on. Until such 23 * IC is available there's no such support. 24 * 25 * Presumably Encoded IRQs may use extra IRQs beyond 64, 26 * below. Some logic must be added to cope with IRQ_IRL? 27 * in an exclusive way. 28 * 29 * Priorities are set at Platform level, when IRQ_IRL0-3 30 * are set to 0 Encoding is allowed. Otherwise it's not 31 * allowed. 32 */ 33 34 /* Independent IRQs */ 35 #define IRQ_IRL0 0 36 #define IRQ_IRL1 1 37 #define IRQ_IRL2 2 38 #define IRQ_IRL3 3 39 40 #define IRQ_INTA 4 41 #define IRQ_INTB 5 42 #define IRQ_INTC 6 43 #define IRQ_INTD 7 44 45 #define IRQ_SERR 12 46 #define IRQ_ERR 13 47 #define IRQ_PWR3 14 48 #define IRQ_PWR2 15 49 #define IRQ_PWR1 16 50 #define IRQ_PWR0 17 51 52 #define IRQ_DMTE0 18 53 #define IRQ_DMTE1 19 54 #define IRQ_DMTE2 20 55 #define IRQ_DMTE3 21 56 #define IRQ_DAERR 22 57 58 #define IRQ_TUNI0 32 59 #define IRQ_TUNI1 33 60 #define IRQ_TUNI2 34 61 #define IRQ_TICPI2 35 62 63 #define IRQ_ATI 36 64 #define IRQ_PRI 37 65 #define IRQ_CUI 38 66 67 #define IRQ_ERI 39 68 #define IRQ_RXI 40 69 #define IRQ_BRI 41 70 #define IRQ_TXI 42 71 72 #define IRQ_ITI 63 73 74 #define NR_INTC_IRQS 64 75 76 #ifdef CONFIG_SH_CAYMAN 77 #define NR_EXT_IRQS 32 78 #define START_EXT_IRQS 64 79 80 /* PCI bus 2 uses encoded external interrupts on the Cayman board */ 81 #define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0) 82 #define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1) 83 #define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2) 84 #define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3) 85 86 #define START_EXT_IRQS 64 87 #else 88 #define NR_EXT_IRQS 0 89 #endif 90 91 #define NR_IRQS (NR_INTC_IRQS+NR_EXT_IRQS) 92 93 94 /* Default IRQs, fixed */ 95 #define TIMER_IRQ IRQ_TUNI0 96 #define RTC_IRQ IRQ_CUI 97 98 /* Default Priorities, Platform may choose differently */ 99 #define NO_PRIORITY 0 /* Disabled */ 100 #define TIMER_PRIORITY 2 101 #define RTC_PRIORITY TIMER_PRIORITY 102 #define SCIF_PRIORITY 3 103 #define INTD_PRIORITY 3 104 #define IRL3_PRIORITY 4 105 #define INTC_PRIORITY 6 106 #define IRL2_PRIORITY 7 107 #define INTB_PRIORITY 9 108 #define IRL1_PRIORITY 10 109 #define INTA_PRIORITY 12 110 #define IRL0_PRIORITY 13 111 #define TOP_PRIORITY 15 112 113 extern void disable_irq(unsigned int); 114 extern void disable_irq_nosync(unsigned int); 115 extern void enable_irq(unsigned int); 116 117 extern int intc_evt_to_irq[(0xE20/0x20)+1]; 118 int intc_irq_describe(char* p, int irq); 119 120 #ifdef CONFIG_SH_CAYMAN 121 int cayman_irq_demux(int evt); 122 int cayman_irq_describe(char* p, int irq); 123 #define irq_demux(x) cayman_irq_demux(x) 124 #define irq_describe(p, x) cayman_irq_describe(p, x) 125 #else 126 #define irq_demux(x) (intc_evt_to_irq[x]) 127 #define irq_describe(p, x) intc_irq_describe(p, x) 128 #endif 129 130 /* 131 * Function for "on chip support modules". 132 */ 133 134 /* 135 * SH-5 supports Priority based interrupts only. 136 * Interrupt priorities are defined at platform level. 137 */ 138 #define set_ipr_data(a, b, c, d) 139 #define make_ipr_irq(a) 140 #define make_imask_irq(a) 141 142 #endif /* __ASM_SH64_IRQ_H */ 143